https://github.com/yetingk created https://github.com/llvm/llvm-project/pull/75134
Bump to https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0. Actually there is no functional change here. >From ec87b87a67acdcb8faedec327e0938476ddb0893 Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Tue, 12 Dec 2023 11:46:17 +0800 Subject: [PATCH] [RISCV] Bump zicfilp to 0.4 --- clang/test/Preprocessor/riscv-target-features.c | 6 +++--- llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Support/RISCVISAInfo.cpp | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/test/MC/RISCV/attribute-arch.s | 4 ++-- llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 6fc921a8c6ee15..35208b2eae8fbd 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1056,12 +1056,12 @@ // CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zicfilp0p2 -x c -E -dM %s \ +// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zicfilp0p2 -x c -E -dM %s \ +// RUN: -march=rv64i_zicfilp0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s -// CHECK-ZICFILP-EXT: __riscv_zicfilp 2000{{$}} +// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 65dd0d83448ed1..842ebf45305952 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -197,7 +197,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_. ``experimental-zicfilp`` - LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.2.0>`__. + LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. ``experimental-zicond`` LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 6322748430063c..85c34dd6206307 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -174,7 +174,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zfbfmin", RISCVExtensionVersion{0, 8}}, - {"zicfilp", RISCVExtensionVersion{0, 2}}, + {"zicfilp", RISCVExtensionVersion{0, 4}}, {"zicond", RISCVExtensionVersion{1, 0}}, {"ztso", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 030ae06af6d282..b34ccb3ff0f937 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -271,7 +271,7 @@ ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" -; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2" +; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -360,7 +360,7 @@ ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" -; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p2" +; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index aa919f266592f4..3ed48401e43fc8 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -309,5 +309,5 @@ .attribute arch, "rv32i_xcvbi" # CHECK: attribute 5, "rv32i2p1_xcvbi1p0" -.attribute arch, "rv32i_zicfilp0p2" -# CHECK: attribute 5, "rv32i2p1_zicfilp0p2" +.attribute arch, "rv32i_zicfilp0p4" +# CHECK: attribute 5, "rv32i2p1_zicfilp0p4" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 549964eed55518..3de14907899eb6 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V xventanacondops 1.0 Experimental extensions - zicfilp 0.2 This is a long dummy description + zicfilp 0.4 This is a long dummy description zicond 1.0 zacas 1.0 zfbfmin 0.8 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
