https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Tue, 12 Sep 2023 12:28:00 +0800 Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss. The patch adds the instructions in Zicfiss extension. Zicfiss extension is to support shadow stack for control flow integrity. Differential Revision: https://reviews.llvm.org/D152793 --- .../test/Preprocessor/riscv-target-features.c | 9 ++ llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Support/RISCVISAInfo.cpp | 2 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 7 ++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 11 +- .../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71 ++++++++++++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 7 ++ llvm/test/MC/RISCV/attribute-arch.s | 3 + llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +++++++++ llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++ llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++ llvm/test/MC/RISCV/zicfiss-valid.s | 102 ++++++++++++++++++ llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 + 15 files changed, 324 insertions(+), 6 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 43fcb35aba039c..5605a5ed7f29cb 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -119,6 +119,7 @@ // CHECK-NOT: __riscv_zfa {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} +// CHECK-NOT: __riscv_zicfiss {{.*$}} // CHECK-NOT: __riscv_zicond {{.*$}} // CHECK-NOT: __riscv_zimop {{.*$}} // CHECK-NOT: __riscv_zcmop {{.*$}} @@ -1296,3 +1297,11 @@ // RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \ // RUN: -munaligned-access -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-FAST // CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1 + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s +// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 836a4e9ff08e55..53c56e3fb23018 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_. -``experimental-zicfilp`` +``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. ``experimental-zicond`` diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 14079a0eb07603..052abc4a3a1063 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -196,6 +196,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zfbfmin", RISCVExtensionVersion{0, 8}}, {"zicfilp", RISCVExtensionVersion{0, 4}}, + {"zicfiss", RISCVExtensionVersion{0, 4}}, + {"zicond", RISCVExtensionVersion{1, 0}}, {"zimop", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 184000b48987e6..d23f60302f42c7 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + MCRegister Reg = RISCV::X0 + RegNo; + if (Reg != RISCV::X1 && Reg != RISCV::X5) + return MCDisassembler::Fail; + + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -359,6 +370,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder); +static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, + uint64_t Address, + const MCDisassembler *Decoder); + #include "RISCVGenDisassemblerTables.inc" static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, @@ -373,6 +388,16 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, return MCDisassembler::Success; } +static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, + uint64_t Address, + const MCDisassembler *Decoder) { + uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5); + DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid register"); + return MCDisassembler::Success; +} + static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index adf3c84b586a25..ca4cdbb1e0b54a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -79,6 +79,13 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, AssemblerPredicate<(all_of FeatureStdExtZihintntl), "'Zihintntl' (Non-Temporal Locality Hints)">; +def FeatureStdExtZicfiss + : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", + "'Zicfiss' (Shadow stack)">; +def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, + AssemblerPredicate<(all_of FeatureStdExtZicfiss), + "'Zicfiss' (Shadow stack)">; + def FeatureStdExtZifencei : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", "'Zifencei' (fence.i)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index b00cb265a6341d..35e8edf5d2fa72 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2111,16 +2111,17 @@ include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZvk.td" -// Integer -include "RISCVInstrInfoZimop.td" -include "RISCVInstrInfoZicbo.td" -include "RISCVInstrInfoZicond.td" - // Compressed include "RISCVInstrInfoC.td" include "RISCVInstrInfoZc.td" include "RISCVInstrInfoZcmop.td" +// Integer +include "RISCVInstrInfoZimop.td" +include "RISCVInstrInfoZicbo.td" +include "RISCVInstrInfoZicond.td" +include "RISCVInstrInfoZicfiss.td" + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td new file mode 100644 index 00000000000000..631f36624bd8f5 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td @@ -0,0 +1,71 @@ +//===------ RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen -*------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +class RVC_SSInst<bits<5> rs1val, RegisterClass reg_class, string opcodestr> : + RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [], InstFormatOther> { + let Inst{15-13} = 0b011; + let Inst{12} = 0; + let Inst{11-7} = rs1val; + let Inst{6-2} = 0b00000; + let Inst{1-0} = 0b01; + let DecoderMethod = "decodeCSSPushPopchk"; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZicfiss] in { +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk", + "$rs1"> { + let rd = 0; + let imm12 = 0b110011011100; +} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 + +let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp", "$rd"> { + let imm12 = 0b110011011100; + let rs1 = 0b00000; +} +} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2), + "sspush", "$rs2"> { + let rd = 0b00000; + let rs1 = 0b00000; +} +} // Predicates = [HasStdExtZicfiss] + +let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">; + +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">; +} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] + +let Predicates = [HasStdExtZicfiss] in +defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; + +let Predicates = [HasStdExtZicfiss, IsRV64] in +defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; + +//===----------------------------------------------------------------------===/ +// Compress Instruction tablegen backend. +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { +def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>; +def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>; +} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index a3c19115bd3178..24f8d600f1eafc 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -127,6 +127,9 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { markSuperRegs(Reserved, RISCV::X27); } + // Shadow stack pointer. + markSuperRegs(Reserved, RISCV::SSP); + assert(checkAllSuperRegsMarked(Reserved)); return Reserved; } diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index c59c9b294d793e..840fd149d68198 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -137,6 +137,8 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17), (sequence "X%u", 0, 4))>; def GPRX0 : GPRRegisterClass<(add X0)>; +def GPRX1 : GPRRegisterClass<(add X1)>; +def GPRX5 : GPRRegisterClass<(add X5)>; def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>; @@ -165,6 +167,8 @@ def SP : GPRRegisterClass<(add X2)>; def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), (sequence "X%u", 18, 23))>; +def GPRX1X5 : GPRRegisterClass<(add X1, X5)>; + // Floating point registers let RegAltNameIndices = [ABIRegAltName] in { def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; @@ -591,3 +595,6 @@ foreach m = LMULList in { // Special registers def FFLAGS : RISCVReg<0, "fflags">; def FRM : RISCVReg<0, "frm">; + +// Shadow Stack register +def SSP : RISCVReg<0, "ssp">; diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f1c080580fe254..214b02690be03d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -312,5 +312,8 @@ .attribute arch, "rv32i_zicfilp0p4" # CHECK: attribute 5, "rv32i2p1_zicfilp0p4" +.attribute arch, "rv32i_zicfiss0p4" +# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4" + .attribute arch, "rv64i_xsfvfwmaccqqq" # CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s new file mode 100644 index 00000000000000..54893555256d14 --- /dev/null +++ b/llvm/test/MC/RISCV/compressed-zicfiss.s @@ -0,0 +1,53 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x5 + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk t0 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x1 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush ra + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspush x1 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspush ra + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspopchk x5 + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) +c.sspopchk t0 diff --git a/llvm/test/MC/RISCV/rv32zicfiss-invalid.s b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s new file mode 100644 index 00000000000000..1cedcb97e2e7ff --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zicfiss-invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s + +# CHECK-ERR: error: invalid operand for instruction +sspopchk a1 + +# CHECK-ERR: error: invalid operand for instruction +c.sspush t0 + +# CHECK-ERR: error: invalid operand for instruction +c.sspopchk ra + +# CHECK-ERR: error: invalid operand for instruction +sspush a0 + +# CHECK-ERR: error: invalid operand for instruction +ssrdp zero diff --git a/llvm/test/MC/RISCV/rv64zicfiss-invalid.s b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s new file mode 100644 index 00000000000000..1296940455e850 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zicfiss-invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ +# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s + +# CHECK-ERR: error: invalid operand for instruction +sspopchk a1 + +# CHECK-ERR: error: invalid operand for instruction +c.sspush t0 + +# CHECK-ERR: error: invalid operand for instruction +c.sspopchk ra + +# CHECK-ERR: error: invalid operand for instruction +sspush a0 + +# CHECK-ERR: error: invalid operand for instruction +ssrdp zero diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s new file mode 100644 index 00000000000000..fd69d37d7cfa01 --- /dev/null +++ b/llvm/test/MC/RISCV/zicfiss-valid.s @@ -0,0 +1,102 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zicfiss < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-RV64,CHECK-ASM,CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -defsym=RV64=1 -mattr=+a,+experimental-zicfiss < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 -defsym=RV64=1 -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-RV64 %s + +# CHECK-ASM-AND-OBJ: sspopchk ra +# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x1 + +# CHECK-ASM-AND-OBJ: sspopchk ra +# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk ra + +# CHECK-ASM-AND-OBJ: sspopchk t0 +# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk x5 + +# CHECK-ASM-AND-OBJ: sspopchk t0 +# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspopchk t0 + +# CHECK-ASM-AND-OBJ: sspush ra +# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x1 + +# CHECK-ASM-AND-OBJ: sspush ra +# CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush ra + +# check-asm-and-obj: sspush t0 +# check-asm: encoding: [0x73,0x40,0x50,0xce] +# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush x5 + +# check-asm-and-obj: sspush t0 +# check-asm: encoding: [0x73,0x40,0x50,0xce] +# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +sspush t0 + +# CHECK-ASM-AND-OBJ: ssrdp ra +# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssrdp ra + +# CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x48] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.aq a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4c] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.aq a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.rl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.rl a4, ra, (s0) + +# CHECK-ASM-AND-OBJ: ssamoswap.w.aqrl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x4e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.w.aqrl a4, ra, (s0) + +.ifdef RV64 +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x48] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aq a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4c] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.aq a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.rl a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4a] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.rl a4, ra, (s0) + +# CHECK-ASM-AND-OBJ-RV64: ssamoswap.d.aqrl a4, ra, (s0) +# CHECK-ASM-RV64: encoding: [0x2f,0x37,0x14,0x4e] +# CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) +ssamoswap.d.aqrl a4, ra, (s0) +.endif diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 5044177915dbd7..99582da87224c0 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -755,6 +755,7 @@ R"(All available -march extensions for RISC-V Experimental extensions zicfilp 0.4 This is a long dummy description + zicfiss 0.4 zicond 1.0 zimop 0.1 zacas 1.0 >From 76d827e78d74e344d63bcead4477cca69942e7c5 Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Tue, 26 Dec 2023 22:15:27 +0800 Subject: [PATCH 2/3] Add implies of Zicifss. --- llvm/lib/Support/RISCVISAInfo.cpp | 2 + llvm/lib/Target/RISCV/RISCVFeatures.td | 15 +++---- llvm/test/MC/RISCV/attribute-arch.s | 2 +- llvm/test/MC/RISCV/compressed-zicfiss.s | 53 ------------------------- llvm/test/MC/RISCV/zicfiss-valid.s | 20 ++++++++++ 5 files changed, 31 insertions(+), 61 deletions(-) delete mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 052abc4a3a1063..2833445c18ba20 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zhinxmin"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZicntr[] = {"zicsr"}; +static const char *ImpliedExtsZicfiss[] = {"zicsr", "zimop", "zcmop"}; static const char *ImpliedExtsZihpm[] = {"zicsr"}; static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"}; static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", @@ -1096,6 +1097,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"zfinx"}, {ImpliedExtsZfinx}}, {{"zhinx"}, {ImpliedExtsZhinx}}, {{"zhinxmin"}, {ImpliedExtsZhinxmin}}, + {{"zicfiss"}, {ImpliedExtsZicfiss}}, {{"zicntr"}, {ImpliedExtsZicntr}}, {{"zihpm"}, {ImpliedExtsZihpm}}, {{"zk"}, {ImpliedExtsZk}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index ca4cdbb1e0b54a..11a79fa0e99e32 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -79,13 +79,6 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, AssemblerPredicate<(all_of FeatureStdExtZihintntl), "'Zihintntl' (Non-Temporal Locality Hints)">; -def FeatureStdExtZicfiss - : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", - "'Zicfiss' (Shadow stack)">; -def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, - AssemblerPredicate<(all_of FeatureStdExtZicfiss), - "'Zicfiss' (Shadow stack)">; - def FeatureStdExtZifencei : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", "'Zifencei' (fence.i)">; @@ -707,6 +700,14 @@ def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, AssemblerPredicate<(all_of FeatureStdExtZcmop), "'Zcmop' (Compressed May-Be-Operations)">; +def FeatureStdExtZicfiss + : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", + "'Zicfiss' (Shadow stack)", + [FeatureStdExtZicsr, FeatureStdExtZimop, FeatureStdExtZcmop]>; +def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, + AssemblerPredicate<(all_of FeatureStdExtZicfiss), + "'Zicfiss' (Shadow stack)">; + def FeatureStdExtSmaia : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", "'Smaia' (Smaia encompasses all added CSRs and all " diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 214b02690be03d..9ab67ca4b54f84 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -313,7 +313,7 @@ # CHECK: attribute 5, "rv32i2p1_zicfilp0p4" .attribute arch, "rv32i_zicfiss0p4" -# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4" +# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1_zca1p0_zcmop0p2" .attribute arch, "rv64i_xsfvfwmaccqqq" # CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s deleted file mode 100644 index 54893555256d14..00000000000000 --- a/llvm/test/MC/RISCV/compressed-zicfiss.s +++ /dev/null @@ -1,53 +0,0 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+c < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+c < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss -M no-aliases -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# -# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s - -# CHECK-ASM-AND-OBJ: c.sspopchk t0 -# CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) -sspopchk x5 - -# CHECK-ASM-AND-OBJ: c.sspopchk t0 -# CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) -sspopchk t0 - -# CHECK-ASM-AND-OBJ: c.sspush ra -# CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) -sspush x1 - -# CHECK-ASM-AND-OBJ: c.sspush ra -# CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) -sspush ra - -# CHECK-ASM-AND-OBJ: c.sspush ra -# CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) -c.sspush x1 - -# CHECK-ASM-AND-OBJ: c.sspush ra -# CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) -c.sspush ra - -# CHECK-ASM-AND-OBJ: c.sspopchk t0 -# CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) -c.sspopchk x5 - -# CHECK-ASM-AND-OBJ: c.sspopchk t0 -# CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), 'Zicfiss' (Shadow stack) -c.sspopchk t0 diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s index fd69d37d7cfa01..a4ef37ee6288d2 100644 --- a/llvm/test/MC/RISCV/zicfiss-valid.s +++ b/llvm/test/MC/RISCV/zicfiss-valid.s @@ -100,3 +100,23 @@ ssamoswap.d.rl a4, ra, (s0) # CHECK-NO-EXT-RV64: error: instruction requires the following: 'Zicfiss' (Shadow stack) ssamoswap.d.aqrl a4, ra, (s0) .endif + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +c.sspush x1 + +# CHECK-ASM-AND-OBJ: c.sspush ra +# CHECK-ASM: encoding: [0x81,0x60] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +c.sspush ra + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +c.sspopchk x5 + +# CHECK-ASM-AND-OBJ: c.sspopchk t0 +# CHECK-ASM: encoding: [0x81,0x62] +# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +c.sspopchk t0 >From 6b0a9e40eb59b3c6e306bbd3c450477448f1557e Mon Sep 17 00:00:00 2001 From: Yeting Kuo <yeting....@sifive.com> Date: Thu, 28 Dec 2023 16:44:08 +0800 Subject: [PATCH 3/3] Fix decoder conflict. --- .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 ++ llvm/lib/Target/RISCV/RISCVFeatures.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td | 14 +++++++++----- llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 11 +---------- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index d23f60302f42c7..69f481124562f3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -623,6 +623,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit), DecoderTableRISCV32Only_16, "RISCV32Only_16 table (16-bit Instruction)"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16, + "RVZicfiss table (Shadow Stack)"); TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16, "Zcmt table (16-bit Table Jump Instructions)"); TRY_TO_DECODE_FEATURE( diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 11a79fa0e99e32..92795537bdaa5b 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -707,6 +707,7 @@ def FeatureStdExtZicfiss def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, AssemblerPredicate<(all_of FeatureStdExtZicfiss), "'Zicfiss' (Shadow stack)">; +def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; def FeatureStdExtSmaia : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td index 9213b2043ad1b8..6fbfde5ef488c5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td @@ -22,9 +22,13 @@ class CMOPInst<bits<3> imm3, string opcodestr> let Inst{12-11} = 0; } -foreach i = 0...7 in { - let Predicates = [HasStdExtZcmop] in { - defvar n = !add(!mul(i, 2), 1); - def CMOP # n : CMOPInst<i, "cmop." # n>, Sched<[]>; - } // Predicates = [HasStdExtZcmop] +// CMOP1, CMOP5 is used by Zicfiss. +let Predicates = [HasStdExtZcmop, NoHasStdExtZicfiss] in { + def CMOP1 : CMOPInst<0, "cmop.1">, Sched<[]>; + def CMOP5 : CMOPInst<2, "cmop.5">, Sched<[]>; +} + +foreach n = [3, 7, 9, 11, 13, 15] in { + let Predicates = [HasStdExtZcmop] in + def CMOP # n : CMOPInst<!srl(n, 1), "cmop." # n>, Sched<[]>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td index 631f36624bd8f5..d50885b4d0eb73 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td @@ -47,7 +47,7 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2), } } // Predicates = [HasStdExtZicfiss] -let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { +let Predicates = [HasStdExtZicfiss], DecoderNamespace = "Zicfiss" in { let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">; @@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; let Predicates = [HasStdExtZicfiss, IsRV64] in defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">; - -//===----------------------------------------------------------------------===/ -// Compress Instruction tablegen backend. -//===----------------------------------------------------------------------===// - -let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in { -def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>; -def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>; -} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
