https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/71513
>From 1a6da0d00af17ae17e6c569f12f3e34fbbdf611d Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting....@sifive.com>
Date: Tue, 7 Nov 2023 18:48:04 +0800
Subject: [PATCH 1/2] [RISCV][Clang][TargetParser] Support getting feature
unaligned-scalar-mem from mcpu.
This patch suppots a soft coding way to identify whether a cpu has a feature
"unaligned-scalar-mem" by RISCVProcessors.td.
This patch does not provide test case since there is no cpu
support unaligned-scalar-mem in llvm upstream now.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 3 +++
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 1 +
llvm/lib/TargetParser/RISCVTargetParser.cpp | 12 +++++++++---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 9 +++++++--
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index a05f4b7ea64b487..346fb67ff277e9c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,6 +63,9 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const
Arg *A,
D.Diag(clang::diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Mcpu;
}
+
+ if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
+ Features.push_back("+unaligned-scalar-mem");
}
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index a4cb7988eb398b7..5cc8a4a95304537 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -31,6 +31,7 @@ bool parseTuneCPU(StringRef CPU, bool IsRV64);
StringRef getMArchFromMcpu(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
+bool hasFastUnalignedAccess(StringRef CPU);
} // namespace RISCV
} // namespace llvm
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp
b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 30a1023c0673208..85cdd1289a9538f 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -20,7 +20,7 @@ namespace llvm {
namespace RISCV {
enum CPUKind : unsigned {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -28,12 +28,13 @@ enum CPUKind : unsigned {
struct CPUInfo {
StringLiteral Name;
StringLiteral DefaultMarch;
+ bool FastUnalignedAccess;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};
constexpr CPUInfo RISCVCPUInfo[] = {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) \
- {NAME, DEFAULT_MARCH},
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN)
\
+ {NAME, DEFAULT_MARCH, FAST_UNALIGN},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -44,6 +45,11 @@ static const CPUInfo *getCPUInfoByName(StringRef CPU) {
return nullptr;
}
+bool hasFastUnalignedAccess(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ return Info && Info->FastUnalignedAccess;
+}
+
bool parseCPU(StringRef CPU, bool IsRV64) {
const CPUInfo *Info = getCPUInfoByName(CPU);
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 12174fd83f56648..593b5613825ca50 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -49,7 +49,7 @@ static std::string getMArch(const Record &Rec) {
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
- << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
+ << "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -60,9 +60,14 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
+ bool FastUnalignedAccess =
+ any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
+ return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
+ });
+
OS << "PROC(" << Rec->getName() << ", "
<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"" << MArch << "\"})\n";
+ << "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
>From 231d0f97282e5475f821cb5b0bce6934a42b884b Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting....@sifive.com>
Date: Tue, 7 Nov 2023 21:28:15 +0800
Subject: [PATCH 2/2] Add const qualifier for FastUnalignedAccess
---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 593b5613825ca50..fddfefda1007ddc 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -60,7 +60,7 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
- bool FastUnalignedAccess =
+ const bool FastUnalignedAccess =
any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
});
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