[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

[Yeting Kuo via cfe-commits]

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@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
                                  (sequence "X%u", 18, 23))>;
 
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
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yetingk wrote:

Done.

https://github.com/llvm/llvm-project/pull/66043
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