lenary wrote:
ping?
https://github.com/llvm/llvm-project/pull/132481
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Author: Sam Elliott
Date: 2025-03-24T13:04:00-07:00
New Revision: 4fb9650b21fc038ca044ac1ca7fcd5be0b44194a
URL:
https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a
DIFF:
https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a.diff
L
@@ -96,6 +96,21 @@ def simm32 : RISCVOp {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImm
@@ -741,6 +750,28 @@ def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100,
"qc.c.mileaveret">;
} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
+let Predicates = [HasVendorXqciio, IsRV32] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+ def QC_OU
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/132721
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https://github.com/llvm/llvm-project/pull/132721
>From 12e1667575a3b506c5758bd976134e11ccb77f5c Mon Sep 17 00:00:00 2001
From: Harsh Chandel
Date: Mon, 24 Mar 2025 16:15:20 +0530
Subject: [PATCH 1/4] [RISCV] Add Qualcomm uC Xqciio (External Input Output)
exten
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/132721
>From 12e1667575a3b506c5758bd976134e11ccb77f5c Mon Sep 17 00:00:00 2001
From: Harsh Chandel
Date: Mon, 24 Mar 2025 16:15:20 +0530
Subject: [PATCH 1/3] [RISCV] Add Qualcomm uC Xqciio (External Input Output)
exten
@@ -486,6 +486,24 @@ def : SysReg<"mctrctl", 0x34e>;
// Vendor CSRs
//===---
+// XSfmclic
+let FeaturesRequired = [{ {RISCV::FeatureVendorXSfmclic} }] in {
+def : SysReg<"mtvt", 0x307>;
+def : SysReg<"mnxti", 0x345>;
+def : SysReg<"m
https://github.com/lenary commented:
I commented about the predicates (before i saw the other comments). I thought
they'd be ok to do in a follow-up, but you should just to the refactoring now
as it won't quite be NFC as I expected.
https://github.com/llvm/llvm-project/pull/132259
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/132721
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lenary wrote:
Do you hit the same problem with `llvm::Bitset` as you do with `std::bitset`.
https://github.com/llvm/llvm-project/pull/132895
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/132520
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@@ -230,10 +230,16 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
// with stack arguments.
TFI->spillFPBP(MF);
+ LLVM_DEBUG(llvm::dbgs() << "Before calculateCallFrameInfo \n");
lenary wrote:
Oh yeah, oops, lots of it. will remove.
https://gith
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
lenary wrote:
For Info, the last time this was proposed was in 2020:
https://reviews.llvm.org/D79521 - at that time, no vendor extensions had been
accepted upstream, and there was not yet a policy for upstream supporting
vendor extensions.
https://github.com/llvm/llvm-project/pull/132481
lenary wrote:
> Is there a reason why these aren't lowercase like the rest?
They match the existing names documented in
https://starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf - we could
check them in clang case-insensitively, though.
https://github.com/llvm/llvm-project/pull/1324
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/132481
This Change adds support for two SiFive vendor attributes in clang:
- "SiFive-CLIC-preemptible"
- "SiFive-CLIC-stack-swap"
These can be given together, and can be combined with "machine", but
cannot be combined w
https://github.com/lenary approved this pull request.
LGTM. Thanks Harsh!
https://github.com/llvm/llvm-project/pull/132184
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@@ -378,6 +370,14 @@ def FeatureStdExtZca
"part of the C extension, excluding compressed "
"floating point loads/stores">;
+def FeatureStdExtC
+: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
+ RISCVExte
https://github.com/lenary approved this pull request.
LGTM, with one comment.
https://github.com/llvm/llvm-project/pull/132259
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https://github.com/llvm/llvm-project/pull/132259
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@@ -856,6 +856,19 @@ void RISCVISAInfo::updateImplication() {
});
}
+ // Add Zcd if C and D are enabled.
+ if (Exts.count("c") && Exts.count("d") && !Exts.count("zcd")) {
+auto Version = findDefaultVersion("zcd");
+Exts["zcd"] = *Version;
+ }
+
+
@@ -378,6 +370,14 @@ def FeatureStdExtZca
"part of the C extension, excluding compressed "
"floating point loads/stores">;
+def FeatureStdExtC
+: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
+ RISCVExte
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/132259
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@@ -25,8 +25,8 @@ addi a0, a1, 0
# CHECK: # encoding: [0xe0,0x1f]
addi s0, sp, 1020
-# CHECK: .option arch, -c
-.option arch, -c
+# CHECK: .option arch, -c, -zca
+.option arch, -c, -zca
lenary wrote:
This is because your predicates need a little bit of work,
lenary wrote:
There are lots of bugs like this in this area, this is not the only feature
like this. Should this be fixed in a more general way?
https://github.com/llvm/llvm-project/pull/132167
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h
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https://github.com/llvm/llvm-project/pull/131094
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https://github.com/lenary approved this pull request.
LGTM but Craig may have more comments.
https://github.com/llvm/llvm-project/pull/131996
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@@ -96,6 +96,21 @@ def simm32 : RISCVOp {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImm
https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/131094
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@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store
@@ -780,6 +780,14 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
+ if (Exts.count("zclsd") != 0) {
+if (XLen != 32)
+ return getError("'zclsd' is only supported for 'rv32'");
+
+if (Exts.count("zcf") != 0)
+
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https://github.com/llvm/llvm-project/pull/128833
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https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/130219
The Xqci 0.7.0 spec just came out, with some updates to Xqciint, bringing it to
v0.4. The main update of any relevance is that `qc.c.mienter` and
`qc.c.mienter.nest` now update both the stack pointer and the fra
lenary wrote:
> Is there any documentation thats say what instructions these hint encodings
> belong to?
Not explicitly, but these overlap with `SLTI` and `C.SLLI` if I'm reading our
docs correctly. We do intend to move these to use aliases, but we'd like to
land them like this first.
https:
https://github.com/lenary approved this pull request.
LGTM.
I think we've given plenty of time for further comments on supporting this
extension (or not), and given last I heard on the call that @asb was happy for
this to land, I think we should proceed.
https://github.com/llvm/llvm-project/p
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/130779
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https://github.com/llvm/llvm-project/pull/131182
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https://github.com/lenary approved this pull request.
LGTM.
Thank you for doing this PR for Xqcili support, it's great to see interest in
this from the RISC-V community beyond Qualcomm. In future, it would be great to
coordinate on what you are planning to upstream, as we (Qualcomm) have
down
https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/130012
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https://github.com/llvm/llvm-project/pull/130219
>From 30cc00694a8c1d57f201101121d008e89444743a Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Thu, 6 Mar 2025 17:25:44 -0800
Subject: [PATCH 1/2] [RISCV] Update to Xqciint v0.4
The Xqci 0.7.0 spec just came ou
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https://github.com/llvm/llvm-project/pull/129957
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@@ -382,6 +410,10 @@ void
RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
// Get the number of bytes to allocate from the FrameInfo.
uint64_t FrameSize = MFI.getStackSize();
+ // QCI Interrupts use at least 96 bytes of stack space
+ if (RVFI->useQC
@@ -2116,6 +2214,11 @@ bool RISCVFrameLowering::canUseAsEpilogue(const
MachineBasicBlock &MBB) const {
MachineBasicBlock *TmpMBB = const_cast(&MBB);
const auto *RVFI = MF->getInfo();
+ // Qe do not want QC.C.MILEAVERET to be subject to shrink-wrapping - it must
-
@@ -2828,8 +2828,17 @@ targets. This attribute may be attached to a function
definition and instructs
the backend to generate appropriate function entry/exit code so that it can be
used directly as an interrupt service routine.
-Permissible values for this parameter are ``sup
@@ -20831,9 +20831,20 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
StringRef Kind =
MF.getFunction().getFnAttribute("interrupt").getValueAsString();
-if (!(Kind == "supervisor" || Kind == "machine"))
+constexpr StringRef SupportedInterruptKinds[] = {
@@ -1892,9 +1970,23 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
if (MI != MBB.end() && !MI->isDebugInstr())
DL = MI->getDebugLoc();
- // Emit CM.PUSH with base SPimm & evaluate Push stack
RISCVMachineFunctionInfo *RVFI = MF->getInfo();
- if (RVFI->isPusha
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/128815
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https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/129300
These were left over from when Craig removed
`__attribute__((interrupt("user")))` support in
05d0caef6081e1a6cb23a5a5afe43dc82e8ca558.
The tests change "interrupt"="user" into "interrupt"="machine" as they are
@@ -974,17 +974,20 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI));
// Generate new FP.
- if (hasFP(MF) && RVFI->getPushPopKind(MF) !=
- RISCVMachineFunctionInfo::PushPopKind::VendorXqc
lenary wrote:
@topperc the two useful changes since you last reviewed are:
- Adding a Release Note
- Changing the conditions around frame pointers to ensure we don't emit a `add
s0, sp, -` (as before), but that we do emit the `.cfi_def_cfa s0, 0`
which informs dwarf/cfi that the way to calculat
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/128731
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https://github.com/lenary commented:
Looks good with Craig's requested changes.
https://github.com/llvm/llvm-project/pull/128833
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https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/8] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/8] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock
&MBB,
}
}
+static bool isPush(unsigned Opcode) {
+ switch (Opcode) {
+ case RISCV::CM_PUSH:
+ case RISCV::QC_CM_PUSH:
+ case RISCV::QC_CM_PUSHFP:
+return true;
+ default:
+return fals
@@ -783,6 +783,54 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock
&MBB,
}
}
+static bool isPush(unsigned Opcode) {
+ switch (Opcode) {
+ case RISCV::CM_PUSH:
+ case RISCV::QC_CM_PUSH:
+ case RISCV::QC_CM_PUSHFP:
+return true;
+ default:
+return fals
@@ -141,9 +141,38 @@ class RISCVMachineFunctionInfo : public
MachineFunctionInfo {
// We cannot use fixed locations for the callee saved spill slots if the
// function uses a varargs save area.
// TODO: Use a separate placement for vararg registers to enable Zcmp.
@@ -120,12 +144,7 @@ bool RISCVPushPopOpt::runOnMachineFunction(MachineFunction
&Fn) {
// If Zcmp extension is not supported, abort.
const RISCVSubtarget *Subtarget = &Fn.getSubtarget();
- if (!Subtarget->hasStdExtZcmp())
-return false;
-
- // If frame pointer elimi
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/7] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/6] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
https://github.com/lenary approved this pull request.
LGTM. I edited the description for readability, so please use it as the message
when squashing this PR.
https://github.com/llvm/llvm-project/pull/128710
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https://github.com/llvm/llvm-project/pull/128710
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@@ -25,3 +65,27 @@ defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
}
+
+//===--===//
+// XR
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/128773
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https://github.com/lenary commented:
Only one nit, otherwise looks good I think. I didn't closely inspect the
encodings.
https://github.com/llvm/llvm-project/pull/128773
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@@ -0,0 +1,35 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmp -M no-aliases
-show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: invalid operand for instruction
+qc.cm.mvsa01 a1, a2
+
+# CHECK-ERROR: error:
@@ -0,0 +1,95 @@
+//=== RISCVInstrInfoXqccmp.td --*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/6] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
@@ -0,0 +1,35 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmp -M no-aliases
-show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: invalid operand for instruction
+qc.cm.mvsa01 a1, a2
+
+# CHECK-ERROR: error:
https://github.com/lenary edited
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@@ -0,0 +1,95 @@
+//=== RISCVInstrInfoXqccmp.td --*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/4] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/3] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/128731
>From 6f8c6d152033505db6f6b1f8a424c01fcfc05c0d Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 24 Feb 2025 23:07:05 -0800
Subject: [PATCH 1/2] [RISCV] Add Xqccmp Assembly Support
Xqccmp is a new spec by Qu
lenary wrote:
I realise this extension will generate questions about what we do for CodeGen
support for this extension. I have been thinking about this, and I do think it
will be possible to extend the current codegen (prolog epilog inserter mostly)
to support this, fairly easily. I can put up
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/128731
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to solve
the push/pop + frame pointers issue. Broadly, it takes the Zcmp instructions
and reverse the order they push/pop registers in, which
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/124706
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/124706
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@@ -0,0 +1,117 @@
+# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS,CHECK-IMM %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experiment
@@ -721,6 +721,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst
&MI, uint64_t &Size,
"Qualcomm uC Conditional Move custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
"Qu
@@ -1046,6 +1046,20 @@ struct RISCVOperand final : public MCParsedAsmOperand {
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
}
+ bool isImm32() const {
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+if (!isImm())
+
@@ -34,6 +34,21 @@ def uimm11 : RISCVUImmLeafOp<11>;
def simm26 : RISCVSImmLeafOp<26>;
+// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
+// sign-/zero-extension. This is represented internally as a signed 32-bit
value.
+def imm32 : RISCVOp {
+ let
https://github.com/lenary commented:
Thanks for the comments Craig!
https://github.com/llvm/llvm-project/pull/124706
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https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/124706
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https://github.com/lenary approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/124237
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https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/124174
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https://github.com/lenary approved this pull request.
Two tiny issues, but I think I'm happy for this to land.
https://github.com/llvm/llvm-project/pull/121394
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lenary wrote:
You still have a whitespace change to this file?
https://github.com/llvm/llvm-project/pull/121394
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@@ -238,3 +247,11 @@ void
RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
Policy.OnlyBottomUp = false;
}
}
+
+bool RISCVSubtarget::useLoadStorePairs() const {
+ return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
+}
lenary wrote:
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/121394
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https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/124174
This denotes RVC-compatible GPR Pairs, which are used by the Zclsd extension.
C API PR: riscv-non-isa/riscv-c-api-doc#102
>From d26d237f6586b879aab96b5f604e2e85156e778f Mon Sep 17 00:00:00 2001
From: Sam Elliott
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/124174
>From d26d237f6586b879aab96b5f604e2e85156e778f Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Thu, 23 Jan 2025 10:48:08 -0800
Subject: [PATCH 1/2] [RISCV] Support cR Inline Asm Constraint
This denotes RVC-comp
lenary wrote:
Please can you undo these whitespace changes, given you're not really making
changes to this file
https://github.com/llvm/llvm-project/pull/121394
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@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals :
SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+
+def FeatureVendorMIPSCMove
https://github.com/lenary commented:
Some small notes, the one about using RISCVExtension will probably have the
most knock-on work (run both the llvm and the clang test suites after that
change, to see where that info gets to)
https://github.com/llvm/llvm-project/pull/121394
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