https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/137881
>From 77e11986173c1687db5694544337026badb37448 Mon Sep 17 00:00:00 2001 From: Sam Elliott <quic_aelli...@quicinc.com> Date: Tue, 29 Apr 2025 14:28:43 -0700 Subject: [PATCH 1/2] [RISCV] Xqci Extensions v0.10.0 This updates all the extensions to their version in the v0.10.0 spec. All changes from this version are already implemented or are not relevant to LLVM. --- .../Driver/print-supported-extensions-riscv.c | 14 +- llvm/docs/RISCVUsage.rst | 40 ++--- llvm/lib/Target/RISCV/RISCVFeatures.td | 146 +++++++++--------- llvm/test/CodeGen/RISCV/attributes.ll | 18 +-- .../TargetParser/RISCVISAInfoTest.cpp | 26 ++-- 5 files changed, 122 insertions(+), 122 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b10850aadddc3..d96077e787960 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -200,21 +200,21 @@ // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) -// CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension) +// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension) -// CHECK-NEXT: xqcibm 0.4 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) -// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +// CHECK-NEXT: xqcibm 0.7 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) +// CHECK-NEXT: xqcicli 0.3 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) // CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension) // CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) -// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension) -// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension) +// CHECK-NEXT: xqcicsr 0.3 'Xqcicsr' (Qualcomm uC CSR Extension) +// CHECK-NEXT: xqciint 0.7 'Xqciint' (Qualcomm uC Interrupts Extension) // CHECK-NEXT: xqciio 0.1 'Xqciio' (Qualcomm uC External Input Output Extension) // CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension) // CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension) // CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension) -// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension) -// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) +// CHECK-NEXT: xqcilo 0.3 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension) +// CHECK-NEXT: xqcilsm 0.5 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) // CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension) // CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension) // CHECK-NEXT: xqcisync 0.2 'Xqcisync' (Qualcomm uC Sync Delay Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index d0689b779f551..49635273a036f 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -440,58 +440,58 @@ The current vendor extensions supported are: LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. ``experimental-Xqcia`` - LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqciac`` - LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcibi`` - LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcibm`` - LLVM implements `version 0.4 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.7 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcicli`` - LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.3 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcicm`` - LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcics`` - LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcicsr`` - LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. - -``experimental-Xqciio`` - LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.3 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqciint`` - LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.7 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. + +``experimental-Xqciio`` + LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcilb`` - LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcili`` - LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcilia`` - LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcilo`` - LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcilsm`` - LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.5 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcisim`` - LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcisls`` - LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqcisync`` - LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.2 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``Xmipscmov`` LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 18d341aa5b5ca..be172462c2953 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1342,45 +1342,23 @@ def HasVendorXwchc AssemblerPredicate<(all_of FeatureVendorXwchc), "'Xwchc' (WCH/QingKe additional compressed opcodes)">; -// Qualcomm Extension(s) +// Qualcomm Extensions -def FeatureVendorXqcicsr - : RISCVExperimentalExtension<0, 2, "Qualcomm uC CSR Extension">; -def HasVendorXqcicsr - : Predicate<"Subtarget->hasVendorXqcicsr()">, - AssemblerPredicate<(all_of FeatureVendorXqcicsr), - "'Xqcicsr' (Qualcomm uC CSR Extension)">; - -def FeatureVendorXqcisls - : RISCVExperimentalExtension<0, 2, - "Qualcomm uC Scaled Load Store Extension">; -def HasVendorXqcisls - : Predicate<"Subtarget->hasVendorXqcisls()">, - AssemblerPredicate<(all_of FeatureVendorXqcisls), - "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">; +def FeatureVendorXqccmp + : RISCVExperimentalExtension<0, 1, "Qualcomm 16-bit Push/Pop and Double Moves", + [FeatureStdExtZca]>; +def HasVendorXqccmp + : Predicate<"Subtarget->hasVendorXqccmp()">, + AssemblerPredicate<(all_of FeatureVendorXqccmp), + "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">; def FeatureVendorXqcia - : RISCVExperimentalExtension<0, 4, "Qualcomm uC Arithmetic Extension">; + : RISCVExperimentalExtension<0, 6, "Qualcomm uC Arithmetic Extension">; def HasVendorXqcia : Predicate<"Subtarget->hasVendorXqcia()">, AssemblerPredicate<(all_of FeatureVendorXqcia), "'Xqcia' (Qualcomm uC Arithmetic Extension)">; -def FeatureVendorXqcics - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">; -def HasVendorXqcics - : Predicate<"Subtarget->hasVendorXqcics()">, - AssemblerPredicate<(all_of FeatureVendorXqcics), - "'Xqcics' (Qualcomm uC Conditional Select Extension)">; - -def FeatureVendorXqcilsm - : RISCVExperimentalExtension<0, 2, - "Qualcomm uC Load Store Multiple Extension">; -def HasVendorXqcilsm - : Predicate<"Subtarget->hasVendorXqcilsm()">, - AssemblerPredicate<(all_of FeatureVendorXqcilsm), - "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">; - def FeatureVendorXqciac : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension", [FeatureStdExtZca]>; @@ -1389,8 +1367,24 @@ def HasVendorXqciac AssemblerPredicate<(all_of FeatureVendorXqciac), "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">; +def FeatureVendorXqcibi + : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension", + [FeatureStdExtZca]>; +def HasVendorXqcibi + : Predicate<"Subtarget->hasVendorXqcibi()">, + AssemblerPredicate<(all_of FeatureVendorXqcibi), + "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">; + +def FeatureVendorXqcibm + : RISCVExperimentalExtension<0, 7, "Qualcomm uC Bit Manipulation Extension", + [FeatureStdExtZca]>; +def HasVendorXqcibm + : Predicate<"Subtarget->hasVendorXqcibm()">, + AssemblerPredicate<(all_of FeatureVendorXqcibm), + "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">; + def FeatureVendorXqcicli - : RISCVExperimentalExtension<0, 2, + : RISCVExperimentalExtension<0, 3, "Qualcomm uC Conditional Load Immediate Extension">; def HasVendorXqcicli : Predicate<"Subtarget->hasVendorXqcicli()">, @@ -1405,35 +1399,49 @@ def HasVendorXqcicm AssemblerPredicate<(all_of FeatureVendorXqcicm), "'Xqcicm' (Qualcomm uC Conditional Move Extension)">; -def FeatureVendorXqciio - : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">; -def HasVendorXqciio - : Predicate<"Subtarget->hasVendorXqciio()">, - AssemblerPredicate<(all_of FeatureVendorXqciio), - "'Xqciio' (Qualcomm uC External Input Output Extension)">; +def FeatureVendorXqcics + : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">; +def HasVendorXqcics + : Predicate<"Subtarget->hasVendorXqcics()">, + AssemblerPredicate<(all_of FeatureVendorXqcics), + "'Xqcics' (Qualcomm uC Conditional Select Extension)">; + +def FeatureVendorXqcicsr + : RISCVExperimentalExtension<0, 3, "Qualcomm uC CSR Extension">; +def HasVendorXqcicsr + : Predicate<"Subtarget->hasVendorXqcicsr()">, + AssemblerPredicate<(all_of FeatureVendorXqcicsr), + "'Xqcicsr' (Qualcomm uC CSR Extension)">; def FeatureVendorXqciint - : RISCVExperimentalExtension<0, 4, "Qualcomm uC Interrupts Extension", + : RISCVExperimentalExtension<0, 7, "Qualcomm uC Interrupts Extension", [FeatureStdExtZca]>; def HasVendorXqciint : Predicate<"Subtarget->hasVendorXqciint()">, AssemblerPredicate<(all_of FeatureVendorXqciint), "'Xqciint' (Qualcomm uC Interrupts Extension)">; +def FeatureVendorXqciio + : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">; +def HasVendorXqciio + : Predicate<"Subtarget->hasVendorXqciio()">, + AssemblerPredicate<(all_of FeatureVendorXqciio), + "'Xqciio' (Qualcomm uC External Input Output Extension)">; + def FeatureVendorXqcilb : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension", [FeatureStdExtZca]>; - -def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">, - AssemblerPredicate<(all_of FeatureVendorXqcilb), +def HasVendorXqcilb + : Predicate<"Subtarget->hasVendorXqcilb()">, + AssemblerPredicate<(all_of FeatureVendorXqcilb), "'Xqcilb' (Qualcomm uC Long Branch Extension)">; def FeatureVendorXqcili : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension", [FeatureStdExtZca]>; - -def HasVendorXqcili : Predicate<"Subtarget->hasVendorXqcili()">, - AssemblerPredicate<(all_of FeatureVendorXqcili), +def HasVendorXqcili + : Predicate<"Subtarget->hasVendorXqcili()">, + AssemblerPredicate<(all_of FeatureVendorXqcili), "'Xqcili' (Qualcomm uC Load Large Immediate Extension)">; def FeatureVendorXqcilia @@ -1444,53 +1452,45 @@ def HasVendorXqcilia AssemblerPredicate<(all_of FeatureVendorXqcilia), "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">; -def FeatureVendorXqcibm - : RISCVExperimentalExtension<0, 4, "Qualcomm uC Bit Manipulation Extension", - [FeatureStdExtZca]>; -def HasVendorXqcibm - : Predicate<"Subtarget->hasVendorXqcibm()">, - AssemblerPredicate<(all_of FeatureVendorXqcibm), - "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">; - -def FeatureVendorXqcibi - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension", - [FeatureStdExtZca]>; -def HasVendorXqcibi - : Predicate<"Subtarget->hasVendorXqcibi()">, - AssemblerPredicate<(all_of FeatureVendorXqcibi), - "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">; - def FeatureVendorXqcilo - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension", + : RISCVExperimentalExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension", [FeatureStdExtZca]>; def HasVendorXqcilo : Predicate<"Subtarget->hasVendorXqcilo()">, AssemblerPredicate<(all_of FeatureVendorXqcilo), "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">; -def FeatureVendorXqccmp - : RISCVExperimentalExtension<0, 1, - "Qualcomm 16-bit Push/Pop and Double Moves", - [FeatureStdExtZca]>; -def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">, - AssemblerPredicate<(all_of FeatureVendorXqccmp), - "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">; +def FeatureVendorXqcilsm + : RISCVExperimentalExtension<0, 5, + "Qualcomm uC Load Store Multiple Extension">; +def HasVendorXqcilsm + : Predicate<"Subtarget->hasVendorXqcilsm()">, + AssemblerPredicate<(all_of FeatureVendorXqcilsm), + "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">; def FeatureVendorXqcisim : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension", [FeatureStdExtZca]>; def HasVendorXqcisim : Predicate<"Subtarget->hasVendorXqcisim()">, - AssemblerPredicate<(all_of FeatureVendorXqcisim), - "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">; + AssemblerPredicate<(all_of FeatureVendorXqcisim), + "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">; + +def FeatureVendorXqcisls + : RISCVExperimentalExtension<0, 2, + "Qualcomm uC Scaled Load Store Extension">; +def HasVendorXqcisls + : Predicate<"Subtarget->hasVendorXqcisls()">, + AssemblerPredicate<(all_of FeatureVendorXqcisls), + "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">; def FeatureVendorXqcisync : RISCVExperimentalExtension<0, 2, "Qualcomm uC Sync Delay Extension", [FeatureStdExtZca]>; def HasVendorXqcisync : Predicate<"Subtarget->hasVendorXqcisync()">, - AssemblerPredicate<(all_of FeatureVendorXqcisync), - "'Xqcisync' (Qualcomm uC Sync Delay Extension)">; + AssemblerPredicate<(all_of FeatureVendorXqcisync), + "'Xqcisync' (Qualcomm uC Sync Delay Extension)">; // Rivos Extension(s) diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 49e05f9acb4b2..3a445b6bac6e7 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -101,8 +101,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s ; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s ; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s @@ -428,24 +428,24 @@ ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XWCHC: .attribute 5, "rv32i2p1_zca1p0_xwchc2p2" ; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1" -; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4" +; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p6" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3" ; RV32XQCIBI: .attribute 5, "rv32i2p1_zca1p0_xqcibi0p2" -; RV32XQCIBM: .attribute 5, "rv32i2p1_zca1p0_xqcibm0p4" -; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" +; RV32XQCIBM: .attribute 5, "rv32i2p1_zca1p0_xqcibm0p7" +; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p3" ; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" -; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2" -; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4" +; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p3" +; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p7" ; RV32XQCIIO: .attribute 5, "rv32i2p1_xqciio0p1" ; RV32XQCILB: .attribute 5, "rv32i2p1_zca1p0_xqcilb0p2" ; RV32XQCILI: .attribute 5, "rv32i2p1_zca1p0_xqcili0p2" ; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2" -; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2" -; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2" +; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p3" +; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p5" ; RV32XQCISIM: attribute 5, "rv32i2p1_zca1p0_xqcisim0p2" -; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p2" ; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2" +; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p2" ; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0" ; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0" ; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index b8d33e81e6c90..8d9a672c46075 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -682,12 +682,12 @@ TEST(ParseArchString, RejectsConflictingExtensions) { } for (StringRef Input : - {"rv64i_xqcisls0p2", "rv64i_xqcia0p4", "rv64i_xqciac0p3", - "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2", - "rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p4", - "rv64i_xqciio0p1", "rv64i_xqcilo0p2", "rv64i_xqcilia0p2", - "rv64i_xqcibm0p4", "rv64i_xqcibi0p2", "rv64i_xqcili0p2", - "rv64i_xqcisim0p2", "rv64i_xqcilb0p2", "rv64i_xqcisync0p2"}) { + {"rv64i_xqcia0p6", "rv64i_xqciac0p3", "rv64i_xqcibi0p2", + "rv64i_xqcibm0p7", "rv64i_xqcicli0p3", "rv64i_xqcicm0p2", + "rv64i_xqcics0p2", "rv64i_xqcicsr0p3", "rv64i_xqciint0p7", + "rv64i_xqciio0p1", "rv64i_xqcilb0p2", "rv64i_xqcili0p2", + "rv64i_xqcilia0p2", "rv64i_xqcilo0p3", "rv64i_xqcilsm0p5", + "rv64i_xqcisim0p2", "rv64i_xqcisls0p2", "rv64i_xqcisync0p2"}) { EXPECT_THAT( toString(RISCVISAInfo::parseArchString(Input, true).takeError()), ::testing::EndsWith(" is only supported for 'rv32'")); @@ -1171,21 +1171,21 @@ Experimental extensions ssctr 1.0 svukte 0.3 xqccmp 0.1 - xqcia 0.4 + xqcia 0.6 xqciac 0.3 xqcibi 0.2 - xqcibm 0.4 - xqcicli 0.2 + xqcibm 0.7 + xqcicli 0.3 xqcicm 0.2 xqcics 0.2 - xqcicsr 0.2 - xqciint 0.4 + xqcicsr 0.3 + xqciint 0.7 xqciio 0.1 xqcilb 0.2 xqcili 0.2 xqcilia 0.2 - xqcilo 0.2 - xqcilsm 0.2 + xqcilo 0.3 + xqcilsm 0.5 xqcisim 0.2 xqcisls 0.2 xqcisync 0.2 >From c3393664e428f8055a0605c85626f18ee3f60296 Mon Sep 17 00:00:00 2001 From: Sam Elliott <quic_aelli...@quicinc.com> Date: Tue, 29 Apr 2025 21:30:49 -0700 Subject: [PATCH 2/2] Fixups --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index d96077e787960..ffc876e1735a5 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -200,7 +200,7 @@ // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) -// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension) +// CHECK-NEXT: xqcia 0.6 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension) // CHECK-NEXT: xqcibm 0.7 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 49635273a036f..94ebd064fb1c7 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -440,7 +440,7 @@ The current vendor extensions supported are: LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. ``experimental-Xqcia`` - LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. + LLVM implements `version 0.6 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. ``experimental-Xqciac`` LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.10.0>`__ by Qualcomm. These instructions are only available for riscv32. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index be172462c2953..81f7917347e71 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1431,7 +1431,7 @@ def HasVendorXqciio def FeatureVendorXqcilb : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension", [FeatureStdExtZca]>; -def HasVendorXqcilb +def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">, AssemblerPredicate<(all_of FeatureVendorXqcilb), "'Xqcilb' (Qualcomm uC Long Branch Extension)">; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
