https://github.com/lenary created https://github.com/llvm/llvm-project/pull/137854
All the changes for v0.2 and v0.3 are either already implemented, or irrelevant to the compiler implementation. >From f156620203b61fbe48c80b4b45c451f9a6c6eed9 Mon Sep 17 00:00:00 2001 From: Sam Elliott <quic_aelli...@quicinc.com> Date: Tue, 29 Apr 2025 11:10:54 -0700 Subject: [PATCH] [RISCV] Xqccmp v0.3 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b10850aadddc3..ee95807d5ccf5 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -199,7 +199,7 @@ // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) -// CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) +// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) // CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index d0689b779f551..8b8d9cf45a2db 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -437,7 +437,7 @@ The current vendor extensions supported are: LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW". ``experimental-Xqccmp`` - LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. + LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. ``experimental-Xqcia`` LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 18d341aa5b5ca..c0b469788c473 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1469,7 +1469,7 @@ def HasVendorXqcilo "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">; def FeatureVendorXqccmp - : RISCVExperimentalExtension<0, 1, + : RISCVExperimentalExtension<0, 3, "Qualcomm 16-bit Push/Pop and Double Moves", [FeatureStdExtZca]>; def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 49e05f9acb4b2..e50dea06fbb45 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -427,7 +427,7 @@ ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0" ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XWCHC: .attribute 5, "rv32i2p1_zca1p0_xwchc2p2" -; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1" +; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p3" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3" ; RV32XQCIBI: .attribute 5, "rv32i2p1_zca1p0_xqcibi0p2" @@ -667,7 +667,7 @@ ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" -; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p1" +; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3" ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index b8d33e81e6c90..b21ceb6008dfd 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -695,13 +695,13 @@ TEST(ParseArchString, RejectsConflictingExtensions) { for (StringRef Input : {"rv32idc_xqciac0p3", "rv32i_zcd_xqciac0p3", "rv32idc_xqcicm0p2", - "rv32i_zcd_xqcicm0p2", "rv32idc_xqccmp0p1", "rv32i_zcd_xqccmp0p1"}) { + "rv32i_zcd_xqcicm0p2", "rv32idc_xqccmp0p3", "rv32i_zcd_xqccmp0p3"}) { EXPECT_THAT( toString(RISCVISAInfo::parseArchString(Input, true).takeError()), ::testing::EndsWith("extension when 'd' extension is enabled")); } - for (StringRef Input : {"rv32i_zcmp_xqccmp0p1", "rv64i_zcmp_xqccmp0p1"}) { + for (StringRef Input : {"rv32i_zcmp_xqccmp0p3", "rv64i_zcmp_xqccmp0p3"}) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), "'zcmp' and 'xqccmp' extensions are incompatible"); } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
