which toolchain version supports sdiv and udiv instructions?
Hello, I tried codesourcy arm-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu.tar.bz2, and get below err infos. Error: selected processor does not support ARM mode `sdiv R2,R0,R1' Error: selected processor does not support ARM mode `udiv R2,R0,R1' Does it mean this toolchain version don't support both instructions? and which toolchain can support them? Thanks a lot! Xiao ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: which toolchain version supports sdiv and udiv instructions?
On 29 June 2012 15:13, Xiao Jiang wrote: > Hello, > > I tried codesourcy > arm-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu.tar.bz2, and get > below err infos. > > Error: selected processor does not support ARM mode `sdiv R2,R0,R1' > Error: selected processor does not support ARM mode `udiv R2,R0,R1' > > Does it mean this toolchain version don't support both instructions? and > which toolchain can support them? Hi Xaio. I can't speak for the CodeSourcery toolchain, but these instructions first appeared for Thumb-2 mode in binutils 2.20 and ARM mode in binutils 2.21. You can check the version you have with 'arm-none-linux-gnueabi-as --version'. We ship binutils 2.22 with the Linaro Toolchain Binaries which is available at: https://launchpad.net/linaro-toolchain-binaries Check which CPU you're building for. The Thumb-2 instructions are present on the Cortex-M series, Cortex-R series, Cortex-A7, and Cortex-A15. The ARM versions are present on the Cortex-A7 and Cortex-A15 only. You might be building for something earlier like the ARMv5T. -- Michael ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: which toolchain version supports sdiv and udiv instructions?
On 29 June 2012 15:46, Xiao Jiang wrote: > Michael Hope wrote: >> >> On 29 June 2012 15:13, Xiao Jiang wrote: >> >>> >>> Hello, >>> >>> I tried codesourcy >>> arm-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu.tar.bz2, and get >>> below err infos. >>> >>> Error: selected processor does not support ARM mode `sdiv R2,R0,R1' >>> Error: selected processor does not support ARM mode `udiv R2,R0,R1' >>> >>> Does it mean this toolchain version don't support both instructions? and >>> which toolchain can support them? >>> >> >> >> > > Hi Michael, > >> Hi Xaio. I can't speak for the CodeSourcery toolchain, but these >> instructions first appeared for Thumb-2 mode in binutils 2.20 and ARM >> mode in binutils 2.21. You can check the version you have with >> 'arm-none-linux-gnueabi-as --version'. We ship binutils 2.22 with the >> Linaro Toolchain Binaries which is available at: >> >> > > Thanks for your quick reply :). I got the version as follows, seems > it's version can support it. > > $ arm-2012.03/bin/arm-none-linux-gnueabi-as --version > GNU assembler (Sourcery CodeBench Lite 2012.03-57) 2.21.53.20110905 > Copyright 2011 Free Software Foundation, Inc. > This program is free software; you may redistribute it under the terms of > the GNU General Public License version 3 or later. > This program has absolutely no warranty. > This assembler was configured for a target of `arm-none-linux-gnueabi'. > > I need to build for Cortex-A15, and a silly question, how can I test > toolchain support for the instructions? I test it via below simple > assemble code. > > $ cat DIV.s > LDR R0, =300 > MOV R1, #5 > SDIV R2, R0, R1 > UDIV R2, R0, R1 > $ arm-2012.03/bin/arm-none-linux-gnueabi-gcc -g -c -o DIV.o DIV.s > DIV.s: Assembler messages: > DIV.s:3: Error: selected processor does not support ARM mode `sdiv R2,R0,R1' > DIV.s:4: Error: selected processor does not support ARM mode `udiv R2,R0,R1' This works for me: .syntax unified .text .cpu cortex-a15 .type divit, %function divit: sdivr0, r0, r1 bx lr -- Michael ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: which toolchain version supports sdiv and udiv instructions?
Michael Hope wrote: On 29 June 2012 15:13, Xiao Jiang wrote: Hello, I tried codesourcy arm-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu.tar.bz2, and get below err infos. Error: selected processor does not support ARM mode `sdiv R2,R0,R1' Error: selected processor does not support ARM mode `udiv R2,R0,R1' Does it mean this toolchain version don't support both instructions? and which toolchain can support them? Hi Michael, Hi Xaio. I can't speak for the CodeSourcery toolchain, but these instructions first appeared for Thumb-2 mode in binutils 2.20 and ARM mode in binutils 2.21. You can check the version you have with 'arm-none-linux-gnueabi-as --version'. We ship binutils 2.22 with the Linaro Toolchain Binaries which is available at: Thanks for your quick reply :). I got the version as follows, seems it's version can support it. $ arm-2012.03/bin/arm-none-linux-gnueabi-as --version GNU assembler (Sourcery CodeBench Lite 2012.03-57) 2.21.53.20110905 Copyright 2011 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or later. This program has absolutely no warranty. This assembler was configured for a target of `arm-none-linux-gnueabi'. I need to build for Cortex-A15, and a silly question, how can I test toolchain support for the instructions? I test it via below simple assemble code. $ cat DIV.s LDRR0, =300 MOVR1, #5 SDIVR2, R0, R1 UDIVR2, R0, R1 $ arm-2012.03/bin/arm-none-linux-gnueabi-gcc -g -c -o DIV.o DIV.s DIV.s: Assembler messages: DIV.s:3: Error: selected processor does not support ARM mode `sdiv R2,R0,R1' DIV.s:4: Error: selected processor does not support ARM mode `udiv R2,R0,R1' Thanks again! Xiao https://launchpad.net/linaro-toolchain-binaries Check which CPU you're building for. The Thumb-2 instructions are present on the Cortex-M series, Cortex-R series, Cortex-A7, and Cortex-A15. The ARM versions are present on the Cortex-A7 and Cortex-A15 only. You might be building for something earlier like the ARMv5T. -- Michael ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Auto builder failures
Michael, Lots of fails disappear in the precise repawned tests. But there is a new one which pass in previous test but fail in the new test. ~uweigand/gcc-linaro/lp-1010826-4.7-p2/+merge/112036 armv7l-precise-cbuild339-ursa4-cortexa9hfr1 -PASS: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread simulation test +UNSUPPORTED: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread simulation test What's about this one? ~michaelh1/gcc-linaro/later-split-symrefs/+merge/112479 armv7l-natty-cbuild339-tcpanda05-cortexa9r1 -PASS: 27_io/basic_filebuf/close/char/9964.cc execution test +FAIL: 27_io/basic_filebuf/close/char/9964.cc execution test Thanks! -Zhenqiang On 28 June 2012 09:19, Zhenqiang Chen wrote: > On 28 June 2012 05:55, Michael Hope wrote: >> We've had a few testsuite failures recently which were due to the auto >> builder itself. I've started a log at: >> https://wiki.linaro.org/WorkingGroups/ToolChain/CBuild/FailureLog >> >> so we can track the incident rate and see if there's a pattern. >> >> Zhenqiang, if you see an unexpected failure could you respawn the >> build and notify me? > > OK. > > -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Auto builder failures
On 29 June 2012 14:57, Zhenqiang Chen wrote: > Michael, > > Lots of fails disappear in the precise repawned tests. But there is a > new one which pass in previous test but fail in the new test. > > ~uweigand/gcc-linaro/lp-1010826-4.7-p2/+merge/112036 > armv7l-precise-cbuild339-ursa4-cortexa9hfr1 > > -PASS: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread simulation test > +UNSUPPORTED: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread > simulation test Not sure there. Ulrich, could that real? > What's about this one? > ~michaelh1/gcc-linaro/later-split-symrefs/+merge/112479 > armv7l-natty-cbuild339-tcpanda05-cortexa9r1 > > -PASS: 27_io/basic_filebuf/close/char/9964.cc execution test > +FAIL: 27_io/basic_filebuf/close/char/9964.cc execution test Yip, that's common but undiagnosed. I've added it to the list. > Thanks! > -Zhenqiang > On 28 June 2012 09:19, Zhenqiang Chen wrote: >> On 28 June 2012 05:55, Michael Hope wrote: >>> We've had a few testsuite failures recently which were due to the auto >>> builder itself. I've started a log at: >>> https://wiki.linaro.org/WorkingGroups/ToolChain/CBuild/FailureLog >>> >>> so we can track the incident rate and see if there's a pattern. >>> >>> Zhenqiang, if you see an unexpected failure could you respawn the >>> build and notify me? >> >> OK. >> >> -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Auto builder failures
On 29 June 2012 11:28, Michael Hope wrote: > On 29 June 2012 14:57, Zhenqiang Chen wrote: >> Michael, >> >> Lots of fails disappear in the precise repawned tests. But there is a >> new one which pass in previous test but fail in the new test. >> >> ~uweigand/gcc-linaro/lp-1010826-4.7-p2/+merge/112036 >> armv7l-precise-cbuild339-ursa4-cortexa9hfr1 >> >> -PASS: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread simulation >> test >> +UNSUPPORTED: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread >> simulation test > > Not sure there. Ulrich, could that real? If you check the log in previous test http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115000~uweigand~lp-1010826-4.7-p2/logs/armv7l-precise-cbuild335-ursa5-cortexa9hfr1/testsuite-diff.txt, the case is not shown as "UNSUPPORTED". So it seams it is a test environment issue. Thanks! -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: which toolchain version supports sdiv and udiv instructions?
Michael Hope wrote: This works for me: .syntax unified .text .cpu cortex-a15 Got it, I need specified cpu mode here :) Many thanks! Xiao .type divit, %function divit: sdivr0, r0, r1 bx lr -- Michael ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Auto builder failures
Another two cases fail in precise test: -PASS: c-c++-common/simulate-thread/bitfields-3.c -O0 -g thread simulation test +UNSUPPORTED: c-c++-common/simulate-thread/bitfields-3.c -O0 -g thread simulation test -PASS: gcc.dg/simulate-thread/atomic-other-short.c -O0 -g thread simulation test +UNSUPPORTED: gcc.dg/simulate-thread/atomic-other-short.c -O0 -g thread simulation test In previous test, we have -PASS: c-c++-common/simulate-thread/bitfields-1.c -O0 -g thread simulation test +UNSUPPORTED: c-c++-common/simulate-thread/bitfields-1.c -O0 -g thread simulation test -Zhenqiang On 29 June 2012 11:40, Zhenqiang Chen wrote: > On 29 June 2012 11:28, Michael Hope wrote: >> On 29 June 2012 14:57, Zhenqiang Chen wrote: >>> Michael, >>> >>> Lots of fails disappear in the precise repawned tests. But there is a >>> new one which pass in previous test but fail in the new test. >>> >>> ~uweigand/gcc-linaro/lp-1010826-4.7-p2/+merge/112036 >>> armv7l-precise-cbuild339-ursa4-cortexa9hfr1 >>> >>> -PASS: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread simulation >>> test >>> +UNSUPPORTED: gcc.dg/simulate-thread/atomic-other-int.c -O0 -g thread >>> simulation test >> >> Not sure there. Ulrich, could that real? > > If you check the log in previous test > http://ex.seabright.co.nz/build/gcc-linaro-4.7+bzr115000~uweigand~lp-1010826-4.7-p2/logs/armv7l-precise-cbuild335-ursa5-cortexa9hfr1/testsuite-diff.txt, > the case is not shown as "UNSUPPORTED". > > So it seams it is a test environment issue. > > Thanks! > -Zhenqiang ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
