Re: Make m32c build, fix PSImode truncation
DJ Delorie writes: >> Sorry for missing the truncation patterns, I should have grepped >> more than m32c.md. They look a lot like normal moves though. Is >> truncation really not a noop, or are the patterns there to work >> around something (probably this :-))? > > Not sure which pattern you're talking about, but in general, the > m32c's registers are either 16-bit or 24-bit. You can move a pair of > 16-bit registers into a 24-bit register and it truncates as part of > the move, likewise from 32-bit memory to 24-bit reg. Note that moves > to other 32-bit destinations do *not* truncate, nor can 24-bit > registers hold 32-bit values (duh). The 24-bit registers may also > hold a 16-bit value. The pattern in this case was: (define_insn "truncsipsi2_24" [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm") (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))] "TARGET_A24" "@ ; no-op trunc si %1 to psi %0 mov.l\t%1,%0 ldc\t%1,%0 stc\t%1,%0" [(set_attr "flags" "n,sz,n,n")] ) (the ICE I mentioned was on -mcpu=m32cm, forgot to mention that sorry). It looked like alternatives 0 and 1 were really moves, with alternative 0 being a no-op move. The question was really whether: (set (reg:PSI foo) (truncate:PSI (reg:SI bar))) and: (set (reg:PSI foo) (subreg:PSI (reg:SI bar) 0)) are fundamentally different on this target. In other words, does m32c really want to set TRULY_NOOP_TRUNCATION to false for SImode->PSImode truncations, but can't because the interface is broken for partial ints? It looked to me like the answer was "no" in both cases: truncation from SImode to PSImode seems to work just like a lowpart subreg on this target. The corresponding move pattern seems to be: (define_insn "movpsi_op" [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, RpiRaa*Rmm") (match_operand:PSI 1 "m32c_any_operand" "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))] "TARGET_A24 && m32c_mov_ok (operands, PSImode)" "@ mov.l:s\t%1,%0 mov.l\t%1,%0 ldc\t%1,%0 stc\t%1,%0 push.l\t%1 pushc\t%1 popc\t%0 #" [(set_attr "flags" "sz,sz,n,n,n,n,n,*")] ) and AIUI alternative 1 in the truncsipsi2_24 pattern is basically acting like alternative 1 in movpsi_op. If that's right, what do you think of the patch I posted yesterday? Thanks, Richard
Re: [PATCH] Don't instrument with -fsanitize=thread accesses to DECL_HARD_REGISTER vars (PR tree-optimization/57104)
On Mon, Apr 29, 2013 at 9:14 PM, Jakub Jelinek wrote:
> Hi!
>
> DECL_HARD_REGISTER vars don't live in memory, thus they can't be
> addressable.
>
> The following patch fixes the ICE, ok for trunk/4.8?
Ok.
Thanks,
Richard.
> 2013-04-29 Jakub Jelinek
>
> PR tree-optimization/57104
> * tsan.c (instrument_expr): Don't instrument accesses to
> DECL_HARD_REGISTER VAR_DECLs.
>
> * gcc.dg/pr57104.c: New test.
>
> --- gcc/tsan.c.jj 2013-04-24 12:07:12.0 +0200
> +++ gcc/tsan.c 2013-04-29 21:06:48.975888478 +0200
> @@ -128,7 +128,9 @@ instrument_expr (gimple_stmt_iterator gs
> return false;
> }
>
> - if (TREE_READONLY (base))
> + if (TREE_READONLY (base)
> + || (TREE_CODE (base) == VAR_DECL
> + && DECL_HARD_REGISTER (base)))
> return false;
>
>if (size == 0
> --- gcc/testsuite/gcc.dg/pr57104.c.jj 2013-04-29 21:09:46.812948131 +0200
> +++ gcc/testsuite/gcc.dg/pr57104.c 2013-04-29 21:09:39.0 +0200
> @@ -0,0 +1,12 @@
> +/* PR tree-optimization/57104 */
> +/* { dg-do compile { target { x86_64-*-linux* && lp64 } } } */
> +/* { dg-options "-fsanitize=thread" } */
> +
> +register int r asm ("r14");
> +int v;
> +
> +int
> +foo (void)
> +{
> + return r + v;
> +}
>
> Jakub
Re: [Fortran-Dev] Some ubounds -> extent changes
Tobias Burnus wrote: This patch changes some ubounds to extent. The patch is relative to my type patch - but it also applies without. It also fixes a bunch fo testsuite failures. Build and regtested on x86-64-gnu-linux. I have now committed it to the branch as Rev. 198440. Additionally, I have merged the trunk into the branch (Rev. 198442). Tobias
[PATCH, wwwdocs] Fix PR 50642
Hi,
The following patch overrides the default @smallexample attributes defined by
makeinfo. It includes a html.css file where the smallexample attributes are
defined to use a medium font size with a light blue background for readability
and clarity.
2013-04-30 Shakthi Kannan
PR wwwdocs/50642
* Makefile.in: Use --css-include with makeinfo.
* gcc/doc/include/html.css: New CSS file for HTML docs.
---
Makefile.in | 2 +-
gcc/doc/include/html.css | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
create mode 100644 gcc/doc/include/html.css
diff --git a/Makefile.in b/Makefile.in
index bfbaf03..ea70c0d 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -381,7 +381,7 @@ RUNTEST = @RUNTEST@
# sub-makes. It lets flags be given on the command line while still
# using the makeinfo from the object tree.
# (Default to avoid splitting info files by setting the threshold high.)
-MAKEINFOFLAGS = --split-size=500
+MAKEINFOFLAGS = --split-size=500
--css-include=$$r/$(HOST_SUBDIR)/../gcc/doc/include/html.css
# -
# Programs producing files for the HOST machine
diff --git a/gcc/doc/include/html.css b/gcc/doc/include/html.css
new file mode 100644
index 000..6cc0284
--- /dev/null
+++ b/gcc/doc/include/html.css
@@ -0,0 +1,6 @@
+pre.smallexample {
+font-family: sans-serif;
+font-size: medium;
+padding: 4px;
+background: #f2f2f9
+}
\ No newline at end of file
--
1.7.11.7
Re: [Fortran-dev] Implement TS29113 type handling
Tobias Burnus wrote: This patch implements the TS29113 type handling. I have now committed this patch as Rev. 198447, http://gcc.gnu.org/ml/gcc-cvs/2013-04/msg01155.html The commit contains the -m32 corrections of Dominique, http://gcc.gnu.org/ml/fortran/2013-04/msg00248.html Tobias
Re: [PATCH, ARM, iWMMXT] PR target/54338 - Include IWMMXT_GR_REGS in ALL_REGS
Hi, On 08/04/13 06:28, Xinyu Qi wrote: At 2013-04-02 17:50:03,"Ramana Radhakrishnan" wrote: On 04/02/13 10:40, Xinyu Qi wrote: Hi, According to Vladimir Makarov's analysis, the root cause of PR target/54338 is that ALL_REGS doesn't contain IWMMXT_GR_REGS in REG_CLASS_CONTENTS. It seems there is no reason to exclude the IWMMXT_GR_REGS from ALL_REGS as IWMMXT_GR_REGS are the real registers. This patch simply makes ALL_REGS include IWMMXT_GR_REGS to fix this PR. Since the test case gcc.target/arm/mmx-2.c would fail for the same reason and become pass with this fix, no extra test case need to be add. Pass arm.exp test. Patch attached. Testing just with arm.exp is not enough. Ok if no regressions running the entire regression testsuite for C and C++ for arm*-*-*eabi with an iwmmxt configuration. Hi Ramana, I run the full dejagnu test with -march=iwmmxt2 specified in the whole progress for this patch. No regression but a lot of new pass found in the test. Please help to commit it. ChangeLog 2013-04-02 Xinyu Qi PR target/54338 * config/arm/arm.h (REG_CLASS_CONTENTS): Include IWMMXT_GR_REGS in ALL_REGS. It looks to me as if this should also be applied to the 4.8 branch - Xinyu do you agree? If so is the backport OK for 4.8? Thanks, Matt -- Matthew Gretton-Dann Toolchain Working Group, Linaro
[PATCH] Fix PRs 56957 and 57105
Hello,
After Steven's changes tightening the add/remove insn interface, we found a
problem in the selective scheduling when we incorrectly determined whether
an insn should be removed (and a fresh one emitted) or just moved to a
scheduling point. Fixed by just comparing INSN_UIDs of the insn below and
the chosen expr above and abandoning other too clever code for checking
whether an insn was changed or extra insns were emitted.
Some extra cleanups are possible after this patch, but I'd wait a bit to
see if there is any fallout first.
Bootstrapped and tested on ia64 and x86-64, committed after offline
approval from Alexander.
Andrey
2013-04-30 Andrey Belevantsev
gcc:
PR rtl-optimization/56957
PR rtl-optimization/57105
* sel-sched.c (move_op_orig_expr_found): Remove insn_emitted
variable. Use just INSN_UID for determining whether an insn
should be only disconnected from the insn stream.
* sel-sched-ir.h (EXPR_WAS_CHANGED): Remove.
gcc/testsuite:
PR rtl-optimization/57105
* gcc.dg/pr57105.c: New test.
Index: gcc/ChangeLog
===
*** gcc/ChangeLog (revision 198448)
--- gcc/ChangeLog (revision 198449)
***
*** 1,3
--- 1,13
+ 2013-04-30 Andrey Belevantsev
+
+ PR rtl-optimization/56957
+ PR rtl-optimization/57105
+
+ * sel-sched.c (move_op_orig_expr_found): Remove insn_emitted
+ variable. Use just INSN_UID for determining whether an insn
+ should be only disconnected from the insn stream.
+ * sel-sched-ir.h (EXPR_WAS_CHANGED): Remove.
+
2013-04-30 Jakub Jelinek
PR tree-optimization/57104
Index: gcc/testsuite/gcc.dg/pr57105.c
===
*** gcc/testsuite/gcc.dg/pr57105.c (revision 0)
--- gcc/testsuite/gcc.dg/pr57105.c (revision 198449)
***
*** 0
--- 1,18
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
+ /* { dg-options "-Os -fselective-scheduling2 -g" } */
+ int bar (int);
+ int *baz (int *);
+
+ void
+ foo (int a)
+ {
+ while (bar (0))
+ {
+ int *c = baz (0);
+ if (a)
+ {
+ int i = *baz (c);
+ }
+ bar (*baz (c));
+ }
+ }
Index: gcc/testsuite/ChangeLog
===
*** gcc/testsuite/ChangeLog (revision 198448)
--- gcc/testsuite/ChangeLog (revision 198449)
***
*** 1,3
--- 1,8
+ 2013-04-30 Andrey Belevantsev
+
+ PR rtl-optimization/57105
+ * gcc.dg/pr57105.c: New test.
+
2013-04-30 Jakub Jelinek
PR tree-optimization/57104
Index: gcc/sel-sched.c
===
*** gcc/sel-sched.c (revision 198448)
--- gcc/sel-sched.c (revision 198449)
*** move_op_orig_expr_found (insn_t insn, ex
*** 6051,6064
cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
void *static_params)
{
! bool only_disconnect, insn_emitted;
moveop_static_params_p params = (moveop_static_params_p) static_params;
copy_expr_onside (params->c_expr, INSN_EXPR (insn));
track_scheduled_insns_and_blocks (insn);
! insn_emitted = handle_emitting_transformations (insn, expr, params);
! only_disconnect = (params->uid == INSN_UID (insn)
! && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
/* Mark that we've disconnected an insn. */
if (only_disconnect)
--- 6051,6063
cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
void *static_params)
{
! bool only_disconnect;
moveop_static_params_p params = (moveop_static_params_p) static_params;
copy_expr_onside (params->c_expr, INSN_EXPR (insn));
track_scheduled_insns_and_blocks (insn);
! handle_emitting_transformations (insn, expr, params);
! only_disconnect = params->uid == INSN_UID (insn);
/* Mark that we've disconnected an insn. */
if (only_disconnect)
Index: gcc/sel-sched-ir.h
===
*** gcc/sel-sched-ir.h (revision 198448)
--- gcc/sel-sched-ir.h (revision 198449)
*** typedef expr_def *expr_t;
*** 191,198
#define EXPR_WAS_RENAMED(EXPR) ((EXPR)->was_renamed)
#define EXPR_CANT_MOVE(EXPR) ((EXPR)->cant_move)
- #define EXPR_WAS_CHANGED(EXPR) (EXPR_HISTORY_OF_CHANGES (EXPR).length () > 0)
-
/* Insn definition for list of original insns in find_used_regs. */
struct _def
{
--- 191,196
Re: [patch, mips] Fix for PR target/56942
(Top post is gmail's fault ;-) Hello, I dont like this at all. At the very least, if we go this way, then all places where next_active_insn is used should be updated. Otherwise this is just confusion proliferation. Before my patch most ports used the "active" variants and I specifically did non fix the "real" variants. It is marked fixme for a reason: The JUMP_TABLE_DATA should always follow immediately after the label. Copying the fixme is a step in the wrong direction. Please do not commit this patch! Ciao! Steven On 4/30/13, Richard Sandiford wrote: > Steve Ellcey writes: >> OK, here is patch to next_real_insn to keep the ordering property intact >> and fix the bug. OK for checkin? > > Thanks, looks good to me, but an rtl/middle-end/global maintainer > would need to approve it. > > Richard >
Ping: [PATCH, PR 42371] Remove references to functions from symbol table during inlining
Ping.
Thanks,
Martin
- Forwarded message from Martin Jambor -
Date: Wed, 17 Apr 2013 17:45:17 +0200
From: Martin Jambor
To: GCC Patches
Cc: Jan Hubicka
Subject: [PATCH, PR 42371] Remove references to functions from symbol table
during inlining
Hi,
the patch below is a fix for PR 42371 removing references to functions
from symbol table when we know that all their uses were inlined. This
then allows us to remove out-of-line copies of functions when they are
not needed.
The patch adds ability to count the uses of a parameter value that are
all well described by jump functions and call graph indirect edges (or
mark that we do not have uses under control). These counts are then
combined or transferred to a new helper structure (ipa_cst_ref_desc)
associated with constant jump functions when functions are inlined and
decremented when the reference is used to turn an indirect call graph
edges into a direct ones. When the count eventually drops to zero,
the other information in the structure are used to identify and remove
an item in the appropriate reference list in the symbol table. The
data structures allow for non-trivial duplication when whole trees of
inlined call graph nodes are duplicated.
I currently allocate the new structures only when a constant pointer
to a function is passed as a parameter. It is trivial to have one for
all references but I'm not sure what good that would be, at least not
now. Perhaps once we will also attempt to track references to virtual
tables but it will be much more difficult to prove it does not escape
somewhere in the callee(s).
Bootstrapped and tested on x86_64-linux without any problems. OK for
trunk?
Thanks,
Martin
2013-03-22 Martin Jambor
PR middle-end/42371
* ipa-prop.h (IPA_UNDESCRIBED_USE): New macro.
(ipa_constant_data): New type.
(ipa_jump_func): Use ipa_constant_data to hold information about
constant jump functions.
(ipa_get_jf_constant): Adjust to jump function type changes.
(ipa_get_jf_constant_rdesc): New function.
(ipa_param_descriptor): New field controlled_uses.
(ipa_get_controlled_uses): New function.
(ipa_set_controlled_uses): Likewise.
* ipa-ref.h (ipa_find_reference): Declare.
* ipa-prop.c (ipa_cst_ref_desc): New type.
(ipa_print_node_jump_functions_for_edge): Adjust for jump function type
changes.
(ipa_set_jf_constant): Likewise. Also create reference descriptions.
New parameter cs. Adjust all callers.
(ipa_analyze_params_uses): Detect uncontrolled and controlled uses.
(remove_described_reference): New function.
(jfunc_rdesc_usable): Likewise.
(try_make_edge_direct_simple_call): Decrement controlled use count,
attempt to remove reference if it hits zero.
(combine_controlled_uses_counters): New function.
(propagate_controlled_uses): Likewise.
(ipa_propagate_indirect_call_infos): Call propagate_controlled_uses.
(ipa_edge_duplication_hook): Duplicate reference descriptions.
(ipa_print_node_params): Print described use counter.
(ipa_write_jump_function): Adjust to jump function type changes.
(ipa_read_jump_function): New parameter CS, pass it to
ipa_set_jf_constant. Adjust caller.
(ipa_write_node_info): Stream controlled use count
(ipa_read_node_info): Likewise.
* cgraph.c (cgraph_mark_address_taken_node): Bail out instead of
asserting.
* ipa-cp.c (ipcp_discover_new_direct_edges): Decrement controlled use
count. Remove cloning-added reference if it reaches zero.
* ipa-ref.c (ipa_find_reference): New function.
testsuite/
* gcc.dg/ipa/remref-0.c: New test.
* gcc.dg/ipa/remref-1a.c: Likewise.
* gcc.dg/ipa/remref-1b.c: Likewise.
* gcc.dg/ipa/remref-2a.c: Likewise.
* gcc.dg/ipa/remref-2b.c: Likewise.
Index: src/gcc/ipa-prop.c
===
*** src.orig/gcc/ipa-prop.c
--- src/gcc/ipa-prop.c
*** static struct cgraph_2edge_hook_list *ed
*** 62,67
--- 62,83
static struct cgraph_2node_hook_list *node_duplication_hook_holder;
static struct cgraph_node_hook_list *function_insertion_hook_holder;
+ /* Description of a reference to an IPA constant. */
+ struct ipa_cst_ref_desc
+ {
+ /* Edge that corresponds to the statement which took the reference. */
+ struct cgraph_edge *cs;
+ /* Linked list of duplicates created when call graph edges are cloned. */
+ struct ipa_cst_ref_desc *next_duplicate;
+ /* Number of references in IPA structures, IPA_UNDESCRIBED_USE if the value
+ if out of control. */
+ int refcount;
+ };
+
+ /* Allocation pool for reference descriptions. */
+
+ static alloc_pool ipa_refdesc_pool;
+
/* Return index of the formal whose tree is PTREE in function which
corresponds
to INFO.
Ping: [PATCH, PR 56988] Honor by_ref in IPA-CP transformation phase
Ping.
Thanks,
Martin
- Forwarded message from Martin Jambor -
Date: Fri, 19 Apr 2013 11:05:58 +0200
From: Martin Jambor
To: GCC Patches
Cc: Jan Hubicka
Subject: [PATCH, PR 56988] Honor by_ref in IPA-CP transformation phase
Hi,
the following patch fixes PR 56988 by distinguishing between by
reference and by value aggregate replacement value. While it is OK to
ignore the difference in the last phases of propagation/decision
making because any discrepancies have already been weeded out there,
the testcase clearly shows we have to make sure we do not confuse the
two when looking at the statements again.
Bootstrapped and tested on trunk on x86_64-linux. OK for trunk now
and for the 4.8 branch after a round of testing there?
Thanks,
Martin
2013-04-18 Martin Jambor
PR middle-end/56988
* ipa-prop.h (ipa_agg_replacement_value): New flag by_ref.
* ipa-cp.c (ipa_get_indirect_edge_target_1): Also check that by_ref
flags match.
(find_aggregate_values_for_callers_subset): Fill in the by_ref flag of
ipa_agg_replacement_value structures.
(known_aggs_to_agg_replacement_list): Likewise.
* ipa-prop.c (write_agg_replacement_chain): Stream by_ref flag.
(read_agg_replacement_chain): Likewise.
(ipcp_transform_function): Also check that by_ref flags match.
testsuite/
* gcc.dg/ipa/pr56988.c: New test.
Index: src/gcc/ipa-cp.c
===
--- src.orig/gcc/ipa-cp.c
+++ src/gcc/ipa-cp.c
@@ -1508,7 +1508,8 @@ ipa_get_indirect_edge_target_1 (struct c
while (agg_reps)
{
if (agg_reps->index == param_index
- && agg_reps->offset == ie->indirect_info->offset)
+ && agg_reps->offset == ie->indirect_info->offset
+ && agg_reps->by_ref == ie->indirect_info->by_ref)
{
t = agg_reps->value;
break;
@@ -3042,11 +3043,12 @@ find_aggregate_values_for_callers_subset
struct cgraph_edge *cs;
vec inter = vNULL;
struct ipa_agg_jf_item *item;
+ struct ipcp_param_lattices *plats = ipa_get_parm_lattices (dest_info, i);
int j;
/* Among other things, the following check should deal with all by_ref
mismatches. */
- if (ipa_get_parm_lattices (dest_info, i)->aggs_bottom)
+ if (plats->aggs_bottom)
continue;
FOR_EACH_VEC_ELT (callers, j, cs)
@@ -3068,6 +3070,7 @@ find_aggregate_values_for_callers_subset
v->index = i;
v->offset = item->offset;
v->value = item->value;
+ v->by_ref = plats->aggs_by_ref;
v->next = res;
res = v;
}
@@ -3097,6 +3100,7 @@ known_aggs_to_agg_replacement_list (vec<
v->index = i;
v->offset = item->offset;
v->value = item->value;
+ v->by_ref = aggjf->by_ref;
v->next = res;
res = v;
}
Index: src/gcc/ipa-prop.c
===
--- src.orig/gcc/ipa-prop.c
+++ src/gcc/ipa-prop.c
@@ -3674,9 +3674,15 @@ write_agg_replacement_chain (struct outp
for (av = aggvals; av; av = av->next)
{
+ struct bitpack_d bp;
+
streamer_write_uhwi (ob, av->offset);
streamer_write_uhwi (ob, av->index);
stream_write_tree (ob, av->value, true);
+
+ bp = bitpack_create (ob->main_stream);
+ bp_pack_value (&bp, av->by_ref, 1);
+ streamer_write_bitpack (&bp);
}
}
@@ -3694,11 +3700,14 @@ read_agg_replacement_chain (struct lto_i
for (i = 0; i offset = streamer_read_uhwi (ib);
av->index = streamer_read_uhwi (ib);
av->value = stream_read_tree (ib, data_in);
+ bp = streamer_read_bitpack (ib);
+ av->by_ref = bp_unpack_value (&bp, 1);
av->next = aggvals;
aggvals = av;
}
@@ -3917,7 +3926,7 @@ ipcp_transform_function (struct cgraph_n
if (v->index == index
&& v->offset == offset)
break;
- if (!v)
+ if (!v || v->by_ref != by_ref)
continue;
gcc_checking_assert (is_gimple_ip_invariant (v->value));
Index: src/gcc/ipa-prop.h
===
--- src.orig/gcc/ipa-prop.h
+++ src/gcc/ipa-prop.h
@@ -386,6 +386,8 @@ struct GTY(()) ipa_agg_replacement_value
tree value;
/* The paramter index. */
int index;
+ /* Whether the value was passed by reference. */
+ bool by_ref;
};
typedef struct ipa_agg_replacement_value *ipa_agg_replacement_value_p;
Index: src/gcc/testsuite/gcc.dg/ipa/pr56988.c
===
--- /dev/null
+++ src/gcc/testsuite/gcc.dg/ipa/pr56988.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+/* { dg-add-options bind_pic_locally } */
+
+struct S
+{
+ int a, b, c;
+};
+
+volatile int g;
+
+static
Re: [C++ Patch/RFC] PR 57092
Hi, On 04/29/2013 04:48 PM, Jason Merrill wrote: On 04/29/2013 05:05 AM, Paolo Carlini wrote: in this 4.8/4.9 Regression, finish_decltype_type doesn't handle ADDR_EXPR. Hmm...we're seeing the regression because previously finish_decltype_type would have just returned the type of the template parameter so it wouldn't ever see the ADDR_EXPR at instantiation time. But we want to form a DECLTYPE_TYPE so that the mangling is correct. Perhaps the right solution is to handle this case specially in tsubst/DECLTYPE_TYPE: If id is true and the original expr is a TEMPLATE_PARM_INDEX, just instantiate the type of the template parm rather than its value. thanks for your feedback. Are we sure that tsubst_copy_and_build, as called by tsubst/DECLTYPE_TYPE, can't return an ADDR_EXPR in other cases besides TEMPLATE_PARM_INDEX as input? I'm wondering if handling the additional TREE_CODE in finish_decltype_type isn't overall preferable (assuming we wouldn't end up soon handling all sorts of *_EXPR ;) Paolo.
[PATCH] Fix PR57122, bug in split_edge
The following fixes PR57122 where splitting an edge from the
loop latch is wrongly detected as latch-edge split (happens
in case an irreducible region is inside the loop).
Bootstrap and regtest pending on x86_64-unknown-linux-gnu.
Richard.
2013-04-30 Richard Biener
PR middle-end/57122
* cfghooks.c (split_edge): Properly check for the loop
latch edge.
* gcc.dg/torture/pr57122.c: New testcase.
Index: gcc/cfghooks.c
===
--- gcc/cfghooks.c (revision 198441)
+++ gcc/cfghooks.c (working copy)
@@ -662,7 +662,9 @@ split_edge (edge e)
loop = find_common_loop (src->loop_father, dest->loop_father);
add_bb_to_loop (ret, loop);
- if (loop->latch == src)
+ /* If we split the latch edge of loop adjust the latch block. */
+ if (loop->latch == src
+ && loop->header == dest)
loop->latch = ret;
}
Index: gcc/testsuite/gcc.dg/torture/pr57122.c
===
--- gcc/testsuite/gcc.dg/torture/pr57122.c (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr57122.c (working copy)
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+
+unsigned a;
+int b, c;
+
+void f(void)
+{
+ if(a)
+{
+ for(a = 0; a < 2; a++)
+ a /= 7;
+
+ for(;; a++)
+ {
+ if(a)
+ lbl1:
+ b++;
+
+ if(c)
+ goto lbl1;
+lbl2:
+ ;
+ }
+}
+
+ goto lbl2;
+}
Re: Ping: [PATCH, PR 56988] Honor by_ref in IPA-CP transformation phase
> 2013-04-18 Martin Jambor > > PR middle-end/56988 > * ipa-prop.h (ipa_agg_replacement_value): New flag by_ref. > * ipa-cp.c (ipa_get_indirect_edge_target_1): Also check that by_ref > flags match. > (find_aggregate_values_for_callers_subset): Fill in the by_ref flag of > ipa_agg_replacement_value structures. > (known_aggs_to_agg_replacement_list): Likewise. > * ipa-prop.c (write_agg_replacement_chain): Stream by_ref flag. > (read_agg_replacement_chain): Likewise. > (ipcp_transform_function): Also check that by_ref flags match. > > testsuite/ > * gcc.dg/ipa/pr56988.c: New test. OK, thanks! Honza
Re: [C++ Patch/RFC] PR 57092
On 04/30/2013 08:03 AM, Paolo Carlini wrote: I'm wondering if handling the additional TREE_CODE in finish_decltype_type isn't overall preferable (assuming we wouldn't end up soon handling all sorts of *_EXPR ;) That's exactly the problem; it wouldn't stop with ADDR_EXPR, we would need to handle any form of expression that could be a template non-type argument. Jason
Re: [patch, mips] Fix for PR target/56942
Steven Bosscher writes: > I dont like this at all. At the very least, if we go this way, > then all places where next_active_insn is used should be updated. > Otherwise this is just confusion proliferation. You mean all places where next_active_insn is used to get the jump table? That would be fine with me, but as author of the original change, I'm going to ask you to do that if you feel strongly about it :-) Otherwise Steve's patch seems fine to me. > Before my patch most > ports used the "active" variants and I specifically did non fix the > "real" variants. It is marked fixme for a reason: The JUMP_TABLE_DATA > should always follow immediately after the label. Copying the fixme is > a step in the wrong direction. Please do not commit this patch! But you didn't respond to my main point. It always used to be the case that all "active" insns were also "real". I.e. "real" was a _more_ restrictive condition than "active". Having insns that are "active" but not "real" is a change to the interface and also (IMO) doesn't make much sense in terms of English usage. Don't get me wrong: I like the change to use something other than JUMP_INSN to store the jump table, and thanks for making it. I just don't think we should "break" the next_*_insn hierachy at the same time. Richard
[PATCH] Fix PR57107
This fixes PR57107, a latent bug in clobber sinking. We cannot
do without keeping virtual SSA form up-to-date when sinking clobbers
through multiple forwarders.
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk
(latent on the branch I think).
Richard.
2013-04-30 Richard Biener
PR middle-end/57107
* tree-eh.c (sink_clobbers): Preserve virtual SSA form.
* g++.dg/torture/pr57107.C: New testcase.
Index: gcc/tree-eh.c
===
*** gcc/tree-eh.c (revision 198441)
--- gcc/tree-eh.c (working copy)
*** sink_clobbers (basic_block bb)
*** 3342,3348
if (!any_clobbers)
return 0;
! succbb = single_succ (bb);
dgsi = gsi_after_labels (succbb);
gsi = gsi_last_bb (bb);
for (gsi_prev (&gsi); !gsi_end_p (gsi); gsi_prev (&gsi))
--- 3342,3365
if (!any_clobbers)
return 0;
! edge succe = single_succ_edge (bb);
! succbb = succe->dest;
!
! /* See if there is a virtual PHI node to take an updated virtual
! operand from. */
! gimple vphi = NULL;
! tree vuse = NULL_TREE;
! for (gsi = gsi_start_phis (succbb); !gsi_end_p (gsi); gsi_next (&gsi))
! {
! tree res = gimple_phi_result (gsi_stmt (gsi));
! if (virtual_operand_p (res))
! {
! vphi = gsi_stmt (gsi);
! vuse = res;
! break;
! }
! }
!
dgsi = gsi_after_labels (succbb);
gsi = gsi_last_bb (bb);
for (gsi_prev (&gsi); !gsi_end_p (gsi); gsi_prev (&gsi))
*** sink_clobbers (basic_block bb)
*** 3353,3359
continue;
if (gimple_code (stmt) == GIMPLE_LABEL)
break;
- unlink_stmt_vdef (stmt);
lhs = gimple_assign_lhs (stmt);
/* Unfortunately we don't have dominance info updated at this
point, so checking if
--- 3370,3375
*** sink_clobbers (basic_block bb)
*** 3365,3385
&& TREE_CODE (TREE_OPERAND (lhs, 0)) == SSA_NAME
&& !SSA_NAME_IS_DEFAULT_DEF (TREE_OPERAND (lhs, 0)))
{
gsi_remove (&gsi, true);
release_defs (stmt);
continue;
}
gsi_remove (&gsi, false);
! /* Trigger the operand scanner to cause renaming for virtual
! operands for this statement.
!??? Given the simple structure of this code manually
!figuring out the reaching definition should not be too hard. */
! if (gimple_vuse (stmt))
! gimple_set_vuse (stmt, NULL_TREE);
! gsi_insert_before (&dgsi, stmt, GSI_SAME_STMT);
}
! return TODO_update_ssa_only_virtuals;
}
/* At the end of inlining, we can lower EH_DISPATCH. Return true when
--- 3381,3413
&& TREE_CODE (TREE_OPERAND (lhs, 0)) == SSA_NAME
&& !SSA_NAME_IS_DEFAULT_DEF (TREE_OPERAND (lhs, 0)))
{
+ unlink_stmt_vdef (stmt);
gsi_remove (&gsi, true);
release_defs (stmt);
continue;
}
+
+ /* As we do not change stmt order when sinking across a
+ forwarder edge we can keep virtual operands in place. */
gsi_remove (&gsi, false);
! gsi_insert_before (&dgsi, stmt, GSI_NEW_STMT);
!
! /* But adjust virtual operands if we sunk across a PHI node. */
! if (vuse)
! {
! gimple use_stmt;
! imm_use_iterator iter;
! use_operand_p use_p;
! FOR_EACH_IMM_USE_STMT (use_stmt, iter, vuse)
! FOR_EACH_IMM_USE_ON_STMT (use_p, iter)
! SET_USE (use_p, gimple_vdef (stmt));
! /* Adjust the incoming virtual operand. */
! SET_USE (PHI_ARG_DEF_PTR_FROM_EDGE (vphi, succe), gimple_vuse (stmt));
! SET_USE (gimple_vuse_op (stmt), vuse);
! }
}
! return 0;
}
/* At the end of inlining, we can lower EH_DISPATCH. Return true when
Index: gcc/testsuite/g++.dg/torture/pr57107.C
===
*** gcc/testsuite/g++.dg/torture/pr57107.C (revision 0)
--- gcc/testsuite/g++.dg/torture/pr57107.C (working copy)
***
*** 0
--- 1,193
+ // { dg-do compile }
+
+ typedef long unsigned int size_t;
+ namespace std {
+ }
+ namespace std __attribute__ ((__visibility__ ("default"))) {
+ template struct __traitor {
+ enum {
+ __value = bool(_Sp::__value) || bool(_Tp::__value) };
+ };
+ template struct __is_integer {
+ enum {
+ __value = 0 };
+ };
+ template struct __is_floating {
+ enum {
+ __value = 0 };
+ };
+ template struct __is_pointer {
+ enum {
+ __value = 0 };
+ };
+ template struct __is_normal_iterator {
+ enum {
+ __value = 0 };
+ };
+ template struct __is_arithmetic : public
__traitor<__is_integer<_Tp>, __is_floating<_Tp> > {
+ };
+ template st
Re: [PATCH, wwwdocs] Fix PR 50642
On Tue, 30 Apr 2013, Shakthi Kannan wrote: > The following patch overrides the default @smallexample attributes > defined by makeinfo. It includes a html.css file where the smallexample > attributes are defined to use a medium font size with a light blue > background for readability and clarity. > > 2013-04-30 Shakthi Kannan > > PR wwwdocs/50642 > * Makefile.in: Use --css-include with makeinfo. onlinedocs copies of manuals are generated by maintainer-scripts/update_web_docs_svn, which doesn't use any makefiles. -- Joseph S. Myers jos...@codesourcery.com
Re: [build, driver] RFC: Support compressed debug sections
"Joseph S. Myers" writes:
> On Thu, 11 Apr 2013, Rainer Orth wrote:
>
>> +gz=
>> +Common Driver JoinedOrMissing
>> +-gz=Generate compressed debug sections in format
>
> Although handled entirely in specs, I think it's best to use the Enum .opt
> facility to list the valid arguments to this option, so the option
> handling machinery can properly detect invalid arguments. (And, since an
I already wondered how to do this with specs, but your suggestion worked
seamlessly, thanks.
> empty argument isn't meaningful, use Joined rather than JoinedOrMissing.)
Done. This was a leftover from a failed attempt to handle -gz[=format]
in a single clause.
> The integer values assigned to each valid argument string are of course
> arbitrary since nothing will use them.
Right, so I've just used numeric constants.
>> +@item -gz@r{[}=@var{type}@r{]}
>> +@opindex gz
>> +Produce compressed debug sections in DWARF format (if that is
>> +supported). If @var{type} is not given, the default type depends on the
>> +capabilities of the assembler and linker used. @var{type} may be one of
>> +@option{none} (don't compress debug sections), @option{zlib} (use zlib
>> +compression in ELF gABI format), or @option{zlib-gnu} (use zlib
>> +compression in tradition GNU format).
>
> "traditional".
Fixed.
The patch now underwent additonal testing on i386-pc-solaris2.11. The
following tools were handled correctly:
* Solaris as: not yet capable of generating compressed debug sections.
Planned, but command line options not yet known.
* GNU as 2.23.1 built without zlib: just warns about
--compressed-debug-sections, but exits successfully.
* GNU as 2.23.2 with zlib.
* Solaris 11.2 ld: no compressed debug support yet.
* Test version of Solaris 12/11.2 ld: almost final now, command line
option changed to -z compress-sections since the ELF gABI spec allows
compresion of any non-allocable section. I may follow this lead for
gas/gld/gold, so the default for --compress-debug-sections (zlib-gnu)
can remain unchanged, but the --compress-sections default would be
zlib, following the gABI.
* GNU ld 2.23.2: I hadn't realized that gld can decompress on input, but
always produces uncompressed output.
* GNU gold 2.23.2: can read and write compressed sections.
Ok for mainline now?
Thanks.
Rainer
2013-04-10 Rainer Orth
* configure.ac (gcc_cv_as_compress_debug): Check for assembler
compressed debug support.
(gcc_cv_ld_compress_debug): Check for linker compressed debug
support.
* configure: Regenerate.
* config.in: Regenerate.
* common.opt (compressed_debug_sections): New enum.
(gz, gz=): New options.
* gcc.c (LINK_COMPRESS_DEBUG_SPEC, ASM_COMPRESS_DEBUG_SPEC):
Define.
(LINK_COMMAND_SPEC): Invoke LINK_COMPRESS_DEBUG_SPEC.
(asm_options): Invoke ASM_COMPRESS_DEBUG_SPEC.
* opts.c (common_handle_option): Handle OPT_gz, OPT_gz_.
* doc/invoke.texi (Option Summary, Debugging Options): Add
-gz[=type].
(Debugging Options): Document -gz[=type].
# HG changeset patch
# Parent a871a025093e293206f64a1d3b34ac7db53ee187
Enable --compress-debug-sections
diff --git a/gcc/common.opt b/gcc/common.opt
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -2407,6 +2407,28 @@ gxcoff+
Common JoinedOrMissing Negative(gcoff)
Generate debug information in extended XCOFF format
+Enum
+Name(compressed_debug_sections) Type(int)
+
+; Since -gz= is completely handled in specs, the values aren't used and we
+; assign arbitrary constants.
+EnumValue
+Enum(compressed_debug_sections) String(none) Value(0)
+
+EnumValue
+Enum(compressed_debug_sections) String(zlib) Value(1)
+
+EnumValue
+Enum(compressed_debug_sections) String(zlib-gnu) Value(2)
+
+gz
+Common Driver
+Generate compressed debug sections
+
+gz=
+Common Driver Joined Enum(compressed_debug_sections)
+-gz= Generate compressed debug sections in format
+
h
Driver Joined Separate
diff --git a/gcc/configure.ac b/gcc/configure.ac
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -4261,6 +4261,30 @@ if test x"$insn" != x; then
[Define if your assembler supports the --debug-prefix-map option.])])
fi
+gcc_GAS_CHECK_FEATURE([compressed debug sections],
+ gcc_cv_as_compress_debug
+ [# gas compiled without zlib cannot compress debug sections and warns
+ # about it, but still exits successfully. So check for this, too.
+ if $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s 2>&1 | grep -i warning > /dev/null
+ then
+ gcc_cv_as_compress_debug=0
+ elif $gcc_cv_as --compress-debug-sections -o conftest.o conftest.s > /dev/null 2>&1
+ then
+ gcc_cv_as_compress_debug=1
+ gcc_cv_as_compress_debug_option="--compress-debug-sections"
+ gcc_cv_as_no_compress_debug_option="--nocompress-debug-sections"
+ else
+ gcc_cv_as_compress_debug=0
+ # FIXME: Future gas versions will support ELF gABI style via
+ # --compress-debu
Re: [patch] Fix node weight updates during ipa-cp (issue7812053)
On Mon, Apr 29, 2013 at 12:35 PM, H.J. Lu wrote: > On Mon, Apr 29, 2013 at 10:31 AM, Teresa Johnson wrote: >> FYI, Fixed in r198416. >> >> Thanks, >> Teresa >> > > I noticed that sometimes GCC generates: > > _8 = memcpy (ret_6, s_2(D), len_4); > _8 = memcpy (ret_6, s_2(D), len_4); > memcpy (_17, buffer_12(D), add_16); > memcpy (_17, buffer_12(D), add_16); > memcpy (_25, _28, _27); > memcpy (_25, _28, _27); > memcpy (_39, buffer_2, len_4); > memcpy (_39, buffer_2, len_4); > memcpy (_16, &fillbuf, pad_1); > memcpy (_16, &fillbuf, pad_1); I am getting this too with a profiledbootstrap with LTO. However, this isn't due to my changes. I had confirmed that after reverting my changes (r197595 and now the follow-on fix r198416) this problem still occurs. Teresa > ... > > > > -- > H.J. -- Teresa Johnson | Software Engineer | tejohn...@google.com | 408-460-2413
Re: [patch, mips] Fix for PR target/56942
Richard Sandiford writes: > Steven Bosscher writes: >> I dont like this at all. At the very least, if we go this way, >> then all places where next_active_insn is used should be updated. >> Otherwise this is just confusion proliferation. > > You mean all places where next_active_insn is used to get the jump table? > That would be fine with me, but as author of the original change, > I'm going to ask you to do that if you feel strongly about it :-) > Otherwise Steve's patch seems fine to me. > >> Before my patch most >> ports used the "active" variants and I specifically did non fix the >> "real" variants. It is marked fixme for a reason: The JUMP_TABLE_DATA >> should always follow immediately after the label. Copying the fixme is >> a step in the wrong direction. Please do not commit this patch! > > But you didn't respond to my main point. It always used to be the > case that all "active" insns were also "real". I.e. "real" was a > _more_ restrictive condition than "active". Gah, I really wish proof reads before hitting "send" were as effective as those after. Obviously that should read: "active" was a _more_ restrictive condition than "real". Richard
Re: MEM_REF representation problem, and folding fix
On Mon, Apr 29, 2013 at 11:20 PM, Bernd Schmidt wrote: > Currently, MEM_REF contains two pointer arguments, one which is supposed > to be a base object and another which is supposed to be a constant > offset. This representation is somewhat problematic, as not all machines > treat pointer values as essentially integers. On machines where size_t > is smaller than a pointer, for example m32c where it's due to > limitations in the compiler, or the port I've been working on recently > where pointers contain a segment selector that does not participate in > additions, this is not an accurate representation, and it does cause > real issues. > > It would be better to use a representation more like POINTER_PLUS with a > pointer and a real sizetype integer. Can someone explain the comment in > tree.def which states that the type of the constant offset is used for > TBAA purposes? It states "MEM_REF is equivalent to > ((typeof(c))p)->x [...]", so why not represent it as MEM_REF <(desired > type)p, (size_t)c>? Because if p is not of desired type then we have to emit a separate stmt with a type conversion (which are all useless now, btw). Initially I played with having an extra type operand, but all hell breaks lose if you have tree->exp.operand[] be a TREE_TYPE. So I settled for the convenient place of using the constants type. > The following patch works around one instance of the problem. When we > fold an offset addition, the addition must be performed in sizetype, > otherwise we may get unwanted overflow. This bug triggers on m32c for > example, where an offset of 65528 (representing -8) and and offset of 8 > are added, yielding an offset of 65536 instead of zero. Solved by > performing the intermediate computation in sizetype. Ah, yes. Note that this is why we have mem_ref_offset () in tree.c. So a better fix would be to use return fold_build2 (MEM_REF, type, build_fold_addr_expr (base), double_int_to_tree (type1, tree_to_double_int (arg1).sext (TYPE_PRECISION (TREE_TYPE (arg1))) + coffset)); that is, perform the arithmetic using double_int. Note that + arg1 = fold_convert (size_type_node, arg1); would no longer sign-extend arg1, you'd need to use ssize_type_node. And using [s]size_type_node for the offset would wreck targets that have 16bit sizetype and 24bit pointer type (it would truncate parts of the offset). Richard. > Bootstrapped and tested on x86_64-linux (all languages except Ada) with > no changes in the tests, and tested on m32c-elf where it fixes 22 > failures. Ok? > > Bernd
[PATCH] Convert profile scaling computations to rounding divides (issue9050044)
Follow-on patch to r197595 to complete the replacement of truncating divides
in profile scaling code with rounding divide equivalents using helper routines
in basic-block.h. See http://gcc.gnu.org/ml/gcc-patches/2013-04/msg00321.html
for background.
In addition to bootstrap and profiledbootstrap builds and tests (with and
without LTO), I built and tested performance of the SPEC cpu2006 benchmarks
with FDO on a Nehalem system. I didn't see any performance changes that
looked significant.
Ok for trunk?
Thanks,
Teresa
2013-04-30 Teresa Johnson
* loop-unswitch.c (unswitch_loop): Use helper routines with rounding
divides.
* cfg.c (update_bb_profile_for_threading): Ditto.
* tree-inline.c (copy_bb): Ditto.
(copy_edges_for_bb): Ditto.
(initialize_cfun): Ditto.
(copy_cfg_body): Ditto.
(expand_call_inline): Ditto.
* ipa-inline-analysis.c (estimate_edge_size_and_time): Ditto.
(estimate_node_size_and_time): Ditto.
(inline_merge_summary): Ditto.
* cgraphclones.c (cgraph_clone_edge): Ditto.
(cgraph_clone_node): Ditto.
* sched-rgn.c (compute_dom_prob_ps): Ditto.
(compute_trg_info): Ditto.
Index: loop-unswitch.c
===
--- loop-unswitch.c (revision 198416)
+++ loop-unswitch.c (working copy)
@@ -436,12 +436,10 @@ unswitch_loop (struct loop *loop, basic_block unsw
emit_insn_after (seq, BB_END (switch_bb));
e = make_edge (switch_bb, true_edge->dest, 0);
e->probability = prob;
- /* Update to use apply_probability(). */
- e->count = latch_edge->count * prob / REG_BR_PROB_BASE;
+ e->count = apply_probability (latch_edge->count, prob);
e = make_edge (switch_bb, FALLTHRU_EDGE (unswitch_on)->dest, EDGE_FALLTHRU);
e->probability = false_edge->probability;
- /* Update to use apply_probability(). */
- e->count = latch_edge->count * (false_edge->probability) / REG_BR_PROB_BASE;
+ e->count = apply_probability (latch_edge->count, false_edge->probability);
if (irred_flag)
{
Index: cfg.c
===
--- cfg.c (revision 198416)
+++ cfg.c (working copy)
@@ -848,8 +848,7 @@ update_bb_profile_for_threading (basic_block bb, i
/* Compute the probability of TAKEN_EDGE being reached via threaded edge.
Watch for overflows. */
if (bb->frequency)
-/* Update to use GCOV_COMPUTE_SCALE. */
-prob = edge_frequency * REG_BR_PROB_BASE / bb->frequency;
+prob = GCOV_COMPUTE_SCALE (edge_frequency, bb->frequency);
else
prob = 0;
if (prob > taken_edge->probability)
Index: tree-inline.c
===
--- tree-inline.c (revision 198416)
+++ tree-inline.c (working copy)
@@ -1519,13 +1519,11 @@ copy_bb (copy_body_data *id, basic_block bb, int f
basic_block_info automatically. */
copy_basic_block = create_basic_block (NULL, (void *) 0,
(basic_block) prev->aux);
- /* Update to use apply_scale(). */
- copy_basic_block->count = bb->count * count_scale / REG_BR_PROB_BASE;
+ copy_basic_block->count = apply_scale (bb->count, count_scale);
/* We are going to rebuild frequencies from scratch. These values
have just small importance to drive canonicalize_loop_headers. */
- /* Update to use EDGE_FREQUENCY. */
- freq = ((gcov_type)bb->frequency * frequency_scale / REG_BR_PROB_BASE);
+ freq = apply_scale ((gcov_type)bb->frequency, frequency_scale);
/* We recompute frequencies after inlining, so this is quite safe. */
if (freq > BB_FREQ_MAX)
@@ -1891,8 +1889,7 @@ copy_edges_for_bb (basic_block bb, gcov_type count
&& old_edge->dest->aux != EXIT_BLOCK_PTR)
flags |= EDGE_FALLTHRU;
new_edge = make_edge (new_bb, (basic_block) old_edge->dest->aux, flags);
-/* Update to use apply_scale(). */
- new_edge->count = old_edge->count * count_scale / REG_BR_PROB_BASE;
+ new_edge->count = apply_scale (old_edge->count, count_scale);
new_edge->probability = old_edge->probability;
}
@@ -2066,10 +2063,10 @@ initialize_cfun (tree new_fndecl, tree callee_fnde
struct function *src_cfun = DECL_STRUCT_FUNCTION (callee_fndecl);
gcov_type count_scale;
- /* Update to use GCOV_COMPUTE_SCALE. */
if (ENTRY_BLOCK_PTR_FOR_FUNCTION (src_cfun)->count)
-count_scale = (REG_BR_PROB_BASE * count
- / ENTRY_BLOCK_PTR_FOR_FUNCTION (src_cfun)->count);
+count_scale
+= GCOV_COMPUTE_SCALE (count,
+ ENTRY_BLOCK_PTR_FOR_FUNCTION (src_cfun)->count);
else
count_scale = REG_BR_PROB_BASE;
@@ -2253,10 +2250,10 @@ copy_cfg_body (copy_body_data * id, gcov_type coun
int incoming_frequency = 0;
gcov_type incoming_count = 0;
- /* Update to use GCOV_COMPUTE_SCALE. */
if (ENTRY_BLOCK_PTR_FOR_FUNCTION
Re: [WIP RFH] #pragma omp declare simd (aka OpenMP elemental functions) parsing
On 04/29/2013 02:32 PM, Jakub Jelinek wrote: Should I copy the parser->omp_declare_simd_clauses vector pointer say into cp_declarator structure so that grokfndecl could grab it from there? That sounds good. Also, for the attributes I wonder if it wouldn't be better to finally replace the PARM_DECLs in the clauses say with parameter indexes, because otherwise it might be difficult to adjust those during instantiation etc. Yes, that will probably be easier to deal with. Jason
[PATCH, fixincludes] Fix NULL on AIX
AIX headers do not have a complete definition of NULL and the GCC
build complains about "missing sentinel".
The appended patch substitutes a more complete definition of NULL that
satisfies GCC/G++.
I also updated the void_null fix, which was discussed in 2011 to
substitute a more complete definition of NULL. void_null no longer
triggers on AIX because of the "__cplusplus" bypass, which appears in
AIX header files. I can omit void_null from the patch or remove the
fix completely if it no longer is applicable to any target.
(Yes, I will update fixinclude tests, but I first want agreement on
the fix itself.)
Bootstrapped on powerpc-ibm-aix7.1.0.0.
Thanks, David
* inclhack.def (aix_null): New.
(void_null): Substitute newer definition of NULL.
* fixincl.x: Regenerate.
Index: inclhack.def
===
--- inclhack.def(revision 198437)
+++ inclhack.def(working copy)
@@ -617,6 +617,31 @@
};
/*
+ * Fix AIX definition of NULL for G++.
+ */
+fix = {
+hackname = aix_null;
+mach = "*-*-aix*";
+files = curses.h, dbm.h, locale.h, stdio.h, stdlib.h, string.h,
+time.h, unistd.h, wchar.h, sys/dir.h, sys/param.h, sys/types.h;
+bypass= __null;
+select= "#define[ \t]+NULL[ \t]+\\(*0L*\\)*";
+c_fix = format;
+c_fix_arg = "#ifndef NULL\n"
+ "#ifdef __cplusplus\n"
+ "#ifdef __GNUG__\n"
+ "#define NULL\t__null\n"
+ "#else\t /* ! __GNUG__ */\n"
+ "#define NULL\t0L\n"
+ "#endif\t /* __GNUG__ */\n"
+ "#else\t /* ! __cplusplus */\n"
+ "#define NULL\t((void *)0)\n"
+ "#endif\t /* __cplusplus */\n"
+ "#endif\t /* !NULL */";
+test_text = "# define\tNULL \t(0L) /* typed NULL */";
+};
+
+/*
* pthread.h on AIX defines PTHREAD_ONCE_INIT, PTHREAD_MUTEX_INITIALIZER,
* PTHREAD_COND_INITIALIZER and PTHREAD_RWLOCK_INITIALIZER without enough
* braces.
@@ -4552,23 +4577,24 @@
*/
fix = {
hackname = void_null;
-files = curses.h;
-files = dbm.h;
-files = locale.h;
-files = stdio.h;
-files = stdlib.h;
-files = string.h;
-files = time.h;
-files = unistd.h;
-files = sys/dir.h;
-files = sys/param.h;
-files = sys/types.h;
+files = curses.h, dbm.h, locale.h, stdio.h, stdlib.h, string.h,
+time.h, unistd.h, sys/dir.h, sys/param.h, sys/types.h;
/* avoid changing C++ friendly NULL */
bypass= __cplusplus;
bypass= __null;
select= "^#[ \t]*define[ \t]+NULL[ \t]+\\(\\(void[ \t]*\\*\\)0\\)";
c_fix = format;
-c_fix_arg = "#define NULL 0";
+c_fix_arg = "#ifndef NULL\n"
+ "#ifdef __cplusplus\n"
+ "#ifdef __GNUG__\n"
+ "#define NULL\t__null\n"
+ "#else\t /* ! __GNUG__ */\n"
+ "#define NULL\t0L\n"
+ "#endif\t /* __GNUG__ */\n"
+ "#else\t /* ! __cplusplus */\n"
+ "#define NULL\t((void *)0)\n"
+ "#endif\t /* __cplusplus */\n"
+ "#endif\t /* !NULL */";
test_text = "# define\tNULL \t((void *)0) /* typed NULL */";
};
[Patch, Fortran] Permit allocatable/pointer attributes with BIND(C)
TS29113 permits the allocatable/pointer attribute with BIND(C); this
patch allows it now with -std=f2008ts.
While the TS allows it also for scalars, this patch only permits it for
arrays. The reason is that TS29113 requires the use of the array
descriptor - and adding the support for scalars is something I would
like to defer until the new descriptor is ready. (Similarly for
character(len=:) and character(len=*) dummy arguments with Bind(C),
which also use the array descriptor.)
Build and regtested on x86-84-gnu-linux.
OK for the trunk?
Tobias
PS: Admittedly, this feature is only of limited use on the trunk;
however, for Fortran-dev, it is very useful.
2013-04-30 Tobias Burnus
* decl.c (gfc_verify_c_interop_param): Permit allocatable
and pointer with -std=f2008ts.
2013-04-30 Tobias Burnus
* gfortran.dg/bind_c_array_params.f03: Update dg-error.
* gfortran.dg/bind_c_usage_27.f90: New.
* gfortran.dg/bind_c_usage_28.f90: New.
diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index f9891c9..0187911 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -1061,20 +1061,27 @@ gfc_verify_c_interop_param (gfc_symbol *sym)
/* We have to make sure that any param to a bind(c) routine does
not have the allocatable, pointer, or optional attributes,
according to J3/04-007, section 5.1. */
- if (sym->attr.allocatable == 1)
- {
- gfc_error ("Variable '%s' at %L cannot have the "
- "ALLOCATABLE attribute because procedure '%s'"
- " is BIND(C)", sym->name, &(sym->declared_at),
- sym->ns->proc_name->name);
- retval = false;
- }
+ if (sym->attr.allocatable == 1
+ && !gfc_notify_std (GFC_STD_F2008_TS, "Variable '%s' at %L with "
+ "ALLOCATABLE attribute in procedure '%s' "
+ "with BIND(C)", sym->name,
+ &(sym->declared_at),
+ sym->ns->proc_name->name))
+ retval = false;
+
+ if (sym->attr.pointer == 1
+ && !gfc_notify_std (GFC_STD_F2008_TS, "Variable '%s' at %L with "
+ "POINTER attribute in procedure '%s' "
+ "with BIND(C)", sym->name,
+ &(sym->declared_at),
+ sym->ns->proc_name->name))
+ retval = false;
- if (sym->attr.pointer == 1)
+ if ((sym->attr.allocatable || sym->attr.pointer) && !sym->as)
{
- gfc_error ("Variable '%s' at %L cannot have the "
- "POINTER attribute because procedure '%s'"
- " is BIND(C)", sym->name, &(sym->declared_at),
+ gfc_error ("Scalar variable '%s' at %L with POINTER or "
+ "ALLOCATABLE in procedure '%s' with BIND(C) is not yet"
+ " supported", sym->name, &(sym->declared_at),
sym->ns->proc_name->name);
retval = false;
}
diff --git a/gcc/testsuite/gfortran.dg/bind_c_array_params.f03 b/gcc/testsuite/gfortran.dg/bind_c_array_params.f03
index 810f642..0e9903c 100644
--- a/gcc/testsuite/gfortran.dg/bind_c_array_params.f03
+++ b/gcc/testsuite/gfortran.dg/bind_c_array_params.f03
@@ -9,7 +9,7 @@ contains
integer(c_int), dimension(:) :: assumed_array
end subroutine sub0
- subroutine sub1(deferred_array) bind(c) ! { dg-error "cannot" }
+ subroutine sub1(deferred_array) bind(c) ! { dg-error "TS 29113: Variable 'deferred_array' at .1. with POINTER attribute in procedure 'sub1' with BIND.C." }
integer(c_int), pointer :: deferred_array(:)
end subroutine sub1
end module bind_c_array_params
--- /dev/null 2013-04-30 09:21:48.687062896 +0200
+++ gcc/gcc/testsuite/gfortran.dg/bind_c_usage_27.f90 2013-04-30 16:13:02.245613916 +0200
@@ -0,0 +1,17 @@
+! { dg-do compile }
+! { dg-options "-std=f2008ts" }
+!
+! Contributed by Reinhold Bader
+!
+use iso_c_binding
+type, bind(C) :: cstruct
+ integer :: i
+end type
+interface
+ subroutine psub(this, that) bind(c, name='Psub')
+ import :: c_float, cstruct
+ real(c_float), pointer :: this(:)
+ type(cstruct), allocatable :: that(:)
+ end subroutine psub
+ end interface
+end
--- /dev/null 2013-04-30 09:21:48.687062896 +0200
+++ gcc/gcc/testsuite/gfortran.dg/bind_c_usage_28.f90 2013-04-30 16:23:42.15958 +0200
@@ -0,0 +1,20 @@
+! { dg-do compile }
+! { dg-options "-std=f2008" }
+!
+! Contributed by Reinhold Bader
+!
+use iso_c_binding
+type, bind(C) :: cstruct
+ integer :: i
+end type
+interface
+ subroutine psub(this) bind(c, name='Psub') ! { dg-error "TS 29113: Variable 'this' at .1. with POINTER attribute in procedure 'psub' with BIND.C." }
+ import :: c_float, cstruct
+ real(c_float), pointer :: this(:)
+ end subroutine psub
+ subroutine psub2(that) bind(c, name='Psub2') ! { dg-error "TS 29113: Variable 'that' at .1. with ALLOCATABLE attribute in procedure 'psub2' with BIND.C." }
+ import :: c_float, cstruct
+ type(cstruct), allocatable :: that(:)
+ end subroutine psub2
+ end interface
+end
Re: [PATCH, wwwdocs] Fix PR 50642
Hi, - Original Message - | From: "Joseph S. Myers" | | onlinedocs copies of manuals are generated by | maintainer-scripts/update_web_docs_svn, which doesn't use any makefiles. \-- Could you please list the pre-requisite steps needed to run the above? I had used "configure; make; make html; make install-html" to test the patch and the CSS. Thanks for your reply. SK -- Shakthi Kannan skannan at redhat dot com
[AArch64] Improve description of CM instructions in RTL
Comparison operators can be described in RTL in a more accurate
manner than simply using UNSPECs. Do this.
We need the split cases for DI mode to give reload a sensible
alternative. Without these, reload would churn out some truly
ugly code along the lines of:
> fmov d0, x0
> cmp d0, d0, #0
> fmov x0, d0
Regression tested on aarch64-none-elf and aarch64-none-linux-gnu
with no regressions.
OK?
Thanks,
James
---
gcc/
2013-04-30 James Greenhalgh
* config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...
(cmgeu): ...This.
(cmhi): Rename to...
(cmgtu): ...This.
* config/aarch64/aarch64-simd.md
(simd_mode): Add SF.
(aarch64_vcond_internal): Use new names for unsigned comparison insns.
(aarch64_cm): Rewrite to not use UNSPECs.
* config/aarch64/aarch64.md (*cstore_neg): Rename to...
(cstore_neg): ...This.
* config/aarch64/iterators.md
(VALLF): new.
(unspec): Remove UNSPEC_CM.
(COMPARISONS): New.
(UCOMPARISONS): Likewise.
(optab): Add missing comparisons.
(n_optab): New.
(cmp_1): Likewise.
(cmp_2): Likewise.
(CMP): Likewise.
(cmp): Remove.
(VCMP_S): Likewise.
(VCMP_U): Likewise.
(V_cmp_result): Add DF, SF modes.
(v_cmp_result): Likewise.
(v): Likewise.
(vmtype): Likewise.
* config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 6093341..2ae2881 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -230,8 +230,8 @@
BUILTIN_VSDQ_I_DI (BINOP, cmle, 0)
BUILTIN_VSDQ_I_DI (BINOP, cmlt, 0)
/* Implemented by aarch64_cm. */
- BUILTIN_VSDQ_I_DI (BINOP, cmhs, 0)
- BUILTIN_VSDQ_I_DI (BINOP, cmhi, 0)
+ BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
+ BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
/* Implemented by aarch64_. */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 32ea587..3893444 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -21,7 +21,7 @@
; Main data types used by the insntructions
-(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI"
+(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"
(const_string "unknown"))
@@ -1728,12 +1728,12 @@
case LTU:
case GEU:
- emit_insn (gen_aarch64_cmhs (mask, operands[4], operands[5]));
+ emit_insn (gen_aarch64_cmgeu (mask, operands[4], operands[5]));
break;
case LEU:
case GTU:
- emit_insn (gen_aarch64_cmhi (mask, operands[4], operands[5]));
+ emit_insn (gen_aarch64_cmgtu (mask, operands[4], operands[5]));
break;
case NE:
@@ -3170,48 +3170,181 @@
)
-;; cm(eq|ge|le|lt|gt)
+;; cm(eq|ge|gt|lt|le)
+;; Note, we have constraints for Dz and Z as different expanders
+;; have different ideas of what should be passed to this pattern.
-(define_insn "aarch64_cm"
+(define_insn "aarch64_cm"
[(set (match_operand: 0 "register_operand" "=w,w")
-(unspec:
- [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")
- (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]
- VCMP_S))]
+ (neg:
+ (COMPARISONS:
+ (match_operand:VDQ 1 "register_operand" "w,w")
+ (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")
+ )))]
"TARGET_SIMD"
"@
- cm\t%0, %1, %2
- cm\t%0, %1, #0"
+ cm\t%0, %, %
+ cm\t%0, %1, #0"
[(set_attr "simd_type" "simd_cmp")
(set_attr "simd_mode" "")]
)
-;; cm(hs|hi|tst)
+(define_insn_and_split "aarch64_cmdi"
+ [(set (match_operand:DI 0 "register_operand" "=w,w,r")
+ (neg:DI
+ (COMPARISONS:DI
+ (match_operand:DI 1 "register_operand" "w,w,r")
+ (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r")
+ )))]
+ "TARGET_SIMD"
+ "@
+ cm\t%d0, %d, %d
+ cm\t%d0, %d1, #0
+ #"
+ "reload_completed
+ /* We need to prevent the split from
+ happening in the 'w' constraint cases. */
+ && GP_REGNUM_P (REGNO (operands[0]))
+ && GP_REGNUM_P (REGNO (operands[1]))"
+ [(set (reg:CC CC_REGNUM)
+(compare:CC
+ (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 0)
+(neg:DI
+ (COMPARISONS:DI
+ (match_operand 3 "cc_register" "")
+ (const_int 0]
+ {
+enum machine_mode mode = SELECT_CC_MODE (, operands[1], operands[2]);
+rtx cc_reg = aarch64_gen_compare_reg (, operands[1], operands[2]);
+rtx comparison = gen_rtx_ (mode, operands[1], operands[2]);
+emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
+DONE;
+ }
+ [(set_attr "simd_type" "simd_cmp")
+ (set_attr "simd_mode" "DI")]
+)
-(define_insn "aarch64_cm"
+;; cm(hs|hi)
+
+(d
RFA: Use gen_int_mode in plus_constant
This patch fixes out the GEN_INT/gen_int_mode that Richard pointed out
in the wide-int review. It also passes "mode" rather than "VOIDmode"
to immed_double_int_const. (As discussed in that thread, the latter
change shouldn't make any difference in practice, but is still more
correct in principle.)
Bootstrapped & regression-tested on x86_64-linux-gnu. OK to install?
Richard
gcc/
* explow.c (plus_constant): Pass "mode" to immed_double_int_const.
Use gen_int_mode rather than GEN_INT.
Index: gcc/explow.c
===
--- gcc/explow.c2013-02-25 09:41:58.0 +
+++ gcc/explow.c2013-04-30 15:52:57.270362112 +0100
@@ -106,10 +106,10 @@ plus_constant (enum machine_mode mode, r
if (overflow)
gcc_unreachable ();
- return immed_double_int_const (v, VOIDmode);
+ return immed_double_int_const (v, mode);
}
- return GEN_INT (INTVAL (x) + c);
+ return gen_int_mode (INTVAL (x) + c, mode);
case CONST_DOUBLE:
{
@@ -124,7 +124,7 @@ plus_constant (enum machine_mode mode, r
To fix, add constant support wider than CONST_DOUBLE. */
gcc_assert (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_DOUBLE_INT);
- return immed_double_int_const (v, VOIDmode);
+ return immed_double_int_const (v, mode);
}
case MEM:
[AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.
If the end goal of a VEC_COND_EXPR is to pick between
{-1, -1, -1, -1} and {0, 0, 0, 0}
then we do not need to do a bit select, this is just
a move of the generated mask to the result operand.
This patch checks for this case, and emits the
appropriate instructions. This can save us loading the
two constant masks and performing a bsl.
The midend turns GE_EXPR style tree codes in to VEC_COND_EXPRS,
so fixing this folding up earlier in the compiler is not helpful.
Regression tested for aarch64-none-elf with no regressions.
OK?
Thanks,
James
---
gcc/
2013-04-30 James Greenhalgh
* config/aarch64/aarch64-simd.md
(vcond_internal): Handle special cases for constant masks.
(vcond): Allow nonmemory_operands for outcome vectors.
(vcondu): Likewise.
(vcond): New.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 3893444..dfe4acb 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1683,11 +1683,13 @@
(match_operator 3 "comparison_operator"
[(match_operand:VDQ 4 "register_operand")
(match_operand:VDQ 5 "nonmemory_operand")])
- (match_operand:VDQ 1 "register_operand")
- (match_operand:VDQ 2 "register_operand")))]
+ (match_operand:VDQ 1 "nonmemory_operand")
+ (match_operand:VDQ 2 "nonmemory_operand")))]
"TARGET_SIMD"
{
int inverse = 0, has_zero_imm_form = 0;
+ rtx op1 = operands[1];
+ rtx op2 = operands[2];
rtx mask = gen_reg_rtx (mode);
switch (GET_CODE (operands[3]))
@@ -1746,11 +1748,26 @@
}
if (inverse)
-emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[2],
-operands[1]));
- else
-emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[1],
-operands[2]));
+{
+ op1 = operands[2];
+ op2 = operands[1];
+}
+
+/* If we have (a = (b CMP c) ? -1 : 0);
+ Then we can simply move the generated mask. */
+
+if (op1 == CONSTM1_RTX (mode)
+ && op2 == CONST0_RTX (mode))
+ emit_move_insn (operands[0], mask);
+else
+ {
+ if (!REG_P (op1))
+ op1 = force_reg (mode, op1);
+ if (!REG_P (op2))
+ op2 = force_reg (mode, op2);
+ emit_insn (gen_aarch64_simd_bsl (operands[0], mask,
+ op1, op2));
+ }
DONE;
})
@@ -1761,13 +1778,15 @@
(match_operator 3 "comparison_operator"
[(match_operand:VDQF 4 "register_operand")
(match_operand:VDQF 5 "nonmemory_operand")])
- (match_operand:VDQF 1 "register_operand")
- (match_operand:VDQF 2 "register_operand")))]
+ (match_operand:VDQF 1 "nonmemory_operand")
+ (match_operand:VDQF 2 "nonmemory_operand")))]
"TARGET_SIMD"
{
int inverse = 0;
int use_zero_form = 0;
int swap_bsl_operands = 0;
+ rtx op1 = operands[1];
+ rtx op2 = operands[2];
rtx mask = gen_reg_rtx (mode);
rtx tmp = gen_reg_rtx (mode);
@@ -1912,11 +1931,27 @@
}
if (swap_bsl_operands)
-emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[2],
-operands[1]));
- else
-emit_insn (gen_aarch64_simd_bsl (operands[0], mask, operands[1],
-operands[2]));
+{
+ op1 = operands[2];
+ op2 = operands[1];
+}
+
+/* If we have (a = (b CMP c) ? -1 : 0);
+ Then we can simply move the generated mask. */
+
+if (op1 == CONSTM1_RTX (mode)
+ && op2 == CONST0_RTX (mode))
+ emit_move_insn (operands[0], mask);
+else
+ {
+ if (!REG_P (op1))
+ op1 = force_reg (mode, op1);
+ if (!REG_P (op2))
+ op2 = force_reg (mode, op2);
+ emit_insn (gen_aarch64_simd_bsl (operands[0], mask,
+ op1, op2));
+ }
+
DONE;
})
@@ -1926,8 +1961,8 @@
(match_operator 3 "comparison_operator"
[(match_operand:VALL 4 "register_operand")
(match_operand:VALL 5 "nonmemory_operand")])
- (match_operand:VALL 1 "register_operand")
- (match_operand:VALL 2 "register_operand")))]
+ (match_operand:VALL 1 "nonmemory_operand")
+ (match_operand:VALL 2 "nonmemory_operand")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_vcond_internal (operands[0], operands[1],
@@ -1936,6 +1971,22 @@
DONE;
})
+(define_expand "vcond"
+ [(set (match_operand: 0 "register_operand")
+ (if_then_else:
+ (match_operator 3 "comparison_operator"
+ [(match_operand:VDQF 4 "register_operand")
+ (match_operand:VDQF 5 "nonmemory_operand")])
+ (match_operand: 1 "nonmemory_operand")
+ (match_operand: 2 "nonmemory_operand")))]
+ "TARGET_SIMD"
+{
+ emit_insn (gen_aarch64_vcond_internal (
+ operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4], operands[5]));
+ DONE;
+})
(define_expand "vcondu"
[(set (match_operand:VDQ 0 "register_operand")
@@ -1943,8 +1994,8 @@
(match_operator 3 "comparison_operator"
[(match_operand:VDQ 4 "register_operand")
(match_operand:VDQ 5 "nonmemory_operand")])
- (match_operand:VDQ 1 "register_operand")
- (match_operand:VDQ 2 "register_operand")))]
+ (match_operand:VDQ 1 "nonmem
[AArch64 Testsuite] Fix fallout from FCM changes.
Hi,
gcc.target/aarch64/scalar_intrinsics.c uses the vcled_s64 style
intrinsics. As these now just map to a C operation, we need to first
ensure that the arguments to these functions make their way to the
SIMD register set.
For the >= 0 and < 0 opertaions idiom recognition will convert
them to shifts, so we also need to mop up the expectations on numbers
of shifts and generation of cmge d0, d0, #0.
Tested to ensure test still passes.
Thanks,
James
---
gcc/testsuite/
2013-04-30 James Greenhalgh
* gcc.target/aarch64/scalar_intrinsics.c (force_simd): New.
(test_vceqd_s64): Force arguments to SIMD registers.
(test_vceqzd_s64): Likewise.
(test_vcged_s64): Likewise.
(test_vcled_s64): Likewise.
(test_vcgezd_s64): Likewise.
(test_vcged_u64): Likewise.
(test_vcgtd_s64): Likewise.
(test_vcltd_s64): Likewise.
(test_vcgtzd_s64): Likewise.
(test_vcgtd_u64): Likewise.
(test_vclezd_s64): Likewise.
(test_vcltzd_s64): Likewise.
(test_vtst_s64): Likewise.
(test_vtst_u64): Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index 1b85308..e984b8e 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -1,7 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
-#include "../../../config/aarch64/arm_neon.h"
+#include
+
+/* Used to force a variable to a SIMD register. */
+#define force_simd(V1) asm volatile ("mov %d0, %d1" \
+ : "=w"(V1) \
+ : "w"(V1) \
+ : /* No clobbers */);
/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */
@@ -31,7 +37,12 @@ test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
uint64x1_t
test_vceqd_s64 (int64x1_t a, int64x1_t b)
{
- return vceqd_s64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vceqd_s64 (a, b);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
@@ -39,7 +50,11 @@ test_vceqd_s64 (int64x1_t a, int64x1_t b)
uint64x1_t
test_vceqzd_s64 (int64x1_t a)
{
- return vceqzd_s64 (a);
+ uint64x1_t res;
+ force_simd (a);
+ res = vceqzd_s64 (a);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
@@ -47,21 +62,36 @@ test_vceqzd_s64 (int64x1_t a)
uint64x1_t
test_vcged_s64 (int64x1_t a, int64x1_t b)
{
- return vcged_s64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcged_s64 (a, b);
+ force_simd (res);
+ return res;
}
uint64x1_t
test_vcled_s64 (int64x1_t a, int64x1_t b)
{
- return vcled_s64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcled_s64 (a, b);
+ force_simd (res);
+ return res;
}
-/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+/* Idiom recognition will cause this testcase not to generate
+ the expected cmge instruction, so do not check for it. */
uint64x1_t
test_vcgezd_s64 (int64x1_t a)
{
- return vcgezd_s64 (a);
+ uint64x1_t res;
+ force_simd (a);
+ res = vcgezd_s64 (a);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
@@ -69,7 +99,12 @@ test_vcgezd_s64 (int64x1_t a)
uint64x1_t
test_vcged_u64 (uint64x1_t a, uint64x1_t b)
{
- return vcged_u64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcged_u64 (a, b);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
@@ -77,13 +112,23 @@ test_vcged_u64 (uint64x1_t a, uint64x1_t b)
uint64x1_t
test_vcgtd_s64 (int64x1_t a, int64x1_t b)
{
- return vcgtd_s64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcgtd_s64 (a, b);
+ force_simd (res);
+ return res;
}
uint64x1_t
test_vcltd_s64 (int64x1_t a, int64x1_t b)
{
- return vcltd_s64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcltd_s64 (a, b);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
@@ -91,7 +136,11 @@ test_vcltd_s64 (int64x1_t a, int64x1_t b)
uint64x1_t
test_vcgtzd_s64 (int64x1_t a)
{
- return vcgtzd_s64 (a);
+ uint64x1_t res;
+ force_simd (a);
+ res = vcgtzd_s64 (a);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
@@ -99,7 +148,12 @@ test_vcgtzd_s64 (int64x1_t a)
uint64x1_t
test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
{
- return vcgtd_u64 (a, b);
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcgtd_u64 (a, b);
+ force_simd (res);
+ return res;
}
/* { dg-final { scan-assembler-times "\\tcmle\\td\[
[AArch64] Add combiner patterns for FAC instructions
Hi, This patch adds patterns to allow the combiner to generate FAC instructions. Regression tested on aarch64-none-elf with no regressions. OK? Thanks, James --- gcc/ 2013-04-30 James Greenhalgh * config/aarch64/aarch64-simd.md (*aarch64_fac): New. * config/aarch64/iterators.md (FAC_COMPARISONS): New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index dfe4acb..21c2a68 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3400,6 +3400,23 @@ (set_attr "simd_mode" "")] ) +;; fac(ge|gt) +;; Note we can also handle what would be fac(le|lt) by +;; generating fac(ge|gt). + +(define_insn "*aarch64_fac" + [(set (match_operand: 0 "register_operand" "=w") + (neg: + (FAC_COMPARISONS: + (abs:VALLF (match_operand:VALLF 1 "register_operand" "w")) + (abs:VALLF (match_operand:VALLF 2 "register_operand" "w")) + )))] + "TARGET_SIMD" + "fac\t%0, %, %" + [(set_attr "simd_type" "simd_fcmp") + (set_attr "simd_mode" "")] +) + ;; addp (define_insn "aarch64_addp" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0b9f9e8..00e315d 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -553,6 +553,9 @@ ;; Unsigned comparison operators. (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) +;; Unsigned comparison operators. +(define_code_iterator FAC_COMPARISONS [lt le ge gt]) + ;; --- ;; Code Attributes ;; ---
[AArch64] Rewrite vca Neon patterns in C.
Hi,
This patch renames the vac neon intrinsics to vca
as required by the newest version of the neon intrinsics spec.
While we are there, we also update all the vca* intrinsics to
a C implimentation.
Regression tested on aarch64-none-elf with no regressions.
OK?
Thanks,
James
---
gcc/
2013-04-30 James Greenhalgh
* config/aarch64/arm_neon.h
(vac_f<32, 64>): Rename to...
(vca_f<32, 64>): ...this, reimpliment in C.
(vca_f<32, 64>): Reimpliment in C.
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d822130..5f1ab11 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -4545,50 +4545,6 @@ vabsq_s64 (int64x2_t a)
return result;
}
-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-vacged_f64 (float64_t a, float64_t b)
-{
- float64_t result;
- __asm__ ("facge %d0,%d1,%d2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
-vacges_f32 (float32_t a, float32_t b)
-{
- float32_t result;
- __asm__ ("facge %s0,%s1,%s2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-vacgtd_f64 (float64_t a, float64_t b)
-{
- float64_t result;
- __asm__ ("facgt %d0,%d1,%d2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
-vacgts_f32 (float32_t a, float32_t b)
-{
- float32_t result;
- __asm__ ("facgt %s0,%s1,%s2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline int16_t __attribute__ ((__always_inline__))
vaddlv_s8 (int8x8_t a)
{
@@ -5062,138 +5018,6 @@ vbslq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
return result;
}
-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-vcage_f32 (float32x2_t a, float32x2_t b)
-{
- uint32x2_t result;
- __asm__ ("facge %0.2s, %1.2s, %2.2s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-vcageq_f32 (float32x4_t a, float32x4_t b)
-{
- uint32x4_t result;
- __asm__ ("facge %0.4s, %1.4s, %2.4s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-vcageq_f64 (float64x2_t a, float64x2_t b)
-{
- uint64x2_t result;
- __asm__ ("facge %0.2d, %1.2d, %2.2d"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-vcagt_f32 (float32x2_t a, float32x2_t b)
-{
- uint32x2_t result;
- __asm__ ("facgt %0.2s, %1.2s, %2.2s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-vcagtq_f32 (float32x4_t a, float32x4_t b)
-{
- uint32x4_t result;
- __asm__ ("facgt %0.4s, %1.4s, %2.4s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-vcagtq_f64 (float64x2_t a, float64x2_t b)
-{
- uint64x2_t result;
- __asm__ ("facgt %0.2d, %1.2d, %2.2d"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-vcale_f32 (float32x2_t a, float32x2_t b)
-{
- uint32x2_t result;
- __asm__ ("facge %0.2s, %2.2s, %1.2s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
-vcaleq_f32 (float32x4_t a, float32x4_t b)
-{
- uint32x4_t result;
- __asm__ ("facge %0.4s, %2.4s, %1.4s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
-vcaleq_f64 (float64x2_t a, float64x2_t b)
-{
- uint64x2_t result;
- __asm__ ("facge %0.2d, %2.2d, %1.2d"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
-vcalt_f32 (float32x2_t a, float32x2_t b)
-{
- uint32x2_t result;
- __asm__ ("facgt %0.2s, %2.2s, %1.2s"
- : "=w"(result)
- : "w
[AArch64] Add testcases for FAC, FCM changes.
Hi,
This patch adds two testcases for the scalar and vector versions
of the vca* intrinsics.
New tests pass on aarch64-none-elf.
OK?
Thanks,
James
---
gcc/testsuite/
2013-04-30 James Greenhalgh
* gcc.target/aarch64/scalar-vca.c: New.
* gcc.target/aarch64/vect-vca.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar-vca.c b/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
new file mode 100644
index 000..b118814
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(TEST, CMP, SUFFIX, WIDTH, F)\
+int \
+test_fca##TEST##SUFFIX##_float##WIDTH##_t (void) \
+{ \
+ int ret = 0;\
+ int i = 0;\
+ uint##WIDTH##_t output[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+{ \
+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \
+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \
+ /* Inhibit optimization of our linear test loop. */ \
+ asm volatile ("" : : : "memory"); \
+ output[i] = f1 CMP f2 ? -1 : 0; \
+} \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+{ \
+ output[i] = vca##TEST##SUFFIX##_f##WIDTH (input_##SUFFIX##1[i], \
+ input_##SUFFIX##2[i]) \
+ ^ output[i]; \
+ /* Inhibit autovectorization of our scalar test loop. */ \
+ asm volatile ("" : : : "memory"); \
+} \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ret |= output[i]; \
+ \
+ return ret;\
+}
+
+TEST (ge, >=, s, 32, f)
+/* { dg-final { scan-assembler "facge\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (ge, >=, d, 64, )
+/* { dg-final { scan-assembler "facge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+TEST (gt, >, s, 32, f)
+/* { dg-final { scan-assembler "facgt\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (gt, >, d, 64, )
+/* { dg-final { scan-assembler "facgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+
+int
+main (int argc, char **argv)
+{
+ if (test_fcages_float32_t ())
+abort ();
+ if (test_fcaged_float64_t ())
+abort ();
+ if (test_fcagts_float32_t ())
+abort ();
+ if (test_fcagtd_float64_t ())
+abort ();
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-vca.c b/gcc/testsuite/gcc.target/aarch64/vect-vca.c
new file mode 100644
index 000..c0cf2ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-vca.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \
+int \
+test_vca##T##_float##WIDTH##x##LANES##_t (void)\
+{ \
+ int ret = 0;\
+ int i = 0;\
+ uint##WIDTH##_t output[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+{ \
+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \
+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \
+ /* Inhibit optimization of our linear test loop. */ \
+ asm volatile ("" : : : "memory"); \
+ output[i] = f1 CMP f2 ? -1 : 0; \
+} \
+ \
+ for (i = 0; i < NUM_TESTS; i += LANES)\
+{ \
+ float##WIDTH##x##LANES##_t in1 = \
+ vld1##Q##_f##WIDTH (input_##SUFFIX##1 + i); \
+ float##WIDTH##x##LANES##_t in2 = \
+ vld1##Q##_f##WIDTH (input_##SUFFIX##2 + i); \
+ uint##WIDTH##x##LANES##_t expected_out =\
+ vld1##Q##_u##WIDTH (output + i);\
+ uint##WIDTH##x##LANES##_t out = \
+ veor##Q##_u##WIDTH (vca##T##Q##_f##WIDTH (in1, in2), \
+ expected_out);\
+ vst1##Q##_u##WIDTH (output + i, out);\
+} \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ret |= output[i]; \
+ \
+ return ret;\
+}
+
+#define BUILD_VARIANTS(T, CMP) \
+TEST (T, CMP, s, 32, 2, , f) \
+TEST (T, CMP, s, 32, 4, q, f) \
+TEST (T, CMP, d, 64, 2, q, )
+
+BUILD_VARIANTS (ge, >=)
+/* { dg-final { scan-assembler "facge\\tv\
[AArch64] Refactor vector max and min RTL and builtins.
Hi, This patch moves around the max/min infrastructure such that we can more uniformly access the backend RTL patterns and such that it uses the standard pattern names. We also fixup the bugs this introduces in arm_neon.h which expected the older names. Regression tested on aarch64-none-elf with no issues. Thanks, James --- gcc/ 2013-04-30 James Greenhalgh * config/aarch64/aarch64-simd-builtins.def (reduc_smax_): New. (reduc_smin_): Likewise. (reduc_umax_): Likewise. (reduc_umin_): Likewise. (reduc_smax_nan_): Likewise. (reduc_smin_nan_): Likewise. (fmax): Remove. (fmin): Likewise. (smax): Update for V2SF, V4SF and V2DF modes. (smin): Likewise. (smax_nan): New. (smin_nan): Likewise. * config/aarch64/aarch64-simd.md (3): Rename to... (3): ...This, refactor. (s3): New. (3): Likewise. (reduc__): Refactor. (reduc__v4sf): Likewise. (reduc__v2si): Likewise. (aarch64_: Remove. * config/aarch64/arm_neon.h (vmax_f<32,64>): Rewrite to use new builtin names. (vmin_f<32,64>): Likewise. * config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. (FMAXMIN): New. (su): Add mappings for smax, smin, umax, umin. (maxmin): New. (FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. (FMAXMIN): Rename as... (FMAXMIN_UNS): ...This. (maxminv): Remove. (fmaxminv): Likewise. (fmaxmin): Likewise. (maxmin_uns): New. (maxmin_uns_op): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 620406b..97a597e 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -234,18 +234,26 @@ BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0) BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0) - /* Implemented by aarch64_. */ - BUILTIN_VDQF (BINOP, fmax, 0) - BUILTIN_VDQF (BINOP, fmin, 0) - /* Implemented by aarch64_addv. */ BUILTIN_VDQF (UNOP, addv, 0) - /* Implemented by 3. */ - BUILTIN_VDQ_BHSI (BINOP, smax, 3) - BUILTIN_VDQ_BHSI (BINOP, smin, 3) + /* Implemented by reduc__. */ + BUILTIN_VDQIF (UNOP, reduc_smax_, 10) + BUILTIN_VDQIF (UNOP, reduc_smin_, 10) + BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10) + BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10) + BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10) + BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10) + + /* Implemented by 3. + smax variants map to fmaxnm, + smax_nan variants map to fmax. */ + BUILTIN_VDQIF (BINOP, smax, 3) + BUILTIN_VDQIF (BINOP, smin, 3) BUILTIN_VDQ_BHSI (BINOP, umax, 3) BUILTIN_VDQ_BHSI (BINOP, umin, 3) + BUILTIN_VDQF (BINOP, smax_nan, 3) + BUILTIN_VDQF (BINOP, smin_nan, 3) /* Implemented by 2. */ BUILTIN_VDQF (UNOP, btrunc, 2) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 21c2a68..8a48739 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -940,12 +940,12 @@ ) ;; Max/Min operations. -(define_insn "3" +(define_insn "3" [(set (match_operand:VQ_S 0 "register_operand" "=w") (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w") (match_operand:VQ_S 2 "register_operand" "w")))] "TARGET_SIMD" - "\t%0., %1., %2." + "\t%0., %1., %2." [(set_attr "simd_type" "simd_minmax") (set_attr "simd_mode" "")] ) @@ -1417,44 +1417,23 @@ ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring ;; NaNs. -(define_insn "smax3" +(define_insn "3" [(set (match_operand:VDQF 0 "register_operand" "=w") -(smax:VDQF (match_operand:VDQF 1 "register_operand" "w") +(FMAXMIN:VDQF (match_operand:VDQF 1 "register_operand" "w") (match_operand:VDQF 2 "register_operand" "w")))] "TARGET_SIMD" - "fmaxnm\\t%0., %1., %2." + "fnm\\t%0., %1., %2." [(set_attr "simd_type" "simd_fminmax") (set_attr "simd_mode" "")] ) -(define_insn "smin3" +(define_insn "3" [(set (match_operand:VDQF 0 "register_operand" "=w") -(smin:VDQF (match_operand:VDQF 1 "register_operand" "w") - (match_operand:VDQF 2 "register_operand" "w")))] + (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") + (match_operand:VDQF 2 "register_operand" "w")] + FMAXMIN_UNS))] "TARGET_SIMD" - "fminnm\\t%0., %1., %2." - [(set_attr "simd_type" "simd_fminmax") - (set_attr "simd_mode" "")] -) - -;; FP 'across lanes' max and min ops. - -(define_insn "reduc_s_v4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")] - FMAXMINV))] - "TARGET_SIMD" - "fnmv\\t%s0, %1.4s"; - [(set_attr "simd_type" "simd_fminmaxv") - (set_attr "simd_mode" "V4SF")] -) - -(define_insn "reduc_s_" - [(set (match_operand:V2F 0 "register_operand" "=w") - (unspec:V2F [(match_op
[AArch64] Fold max and min reduction builtins to tree.
Hi, This patch folds the signed versions of min and max reduction builtins to tree form. We can't safely fold the unsigned versions as they do not currently have the correct type. We must use TARGET_GIMPLE_FOLD_BUILTIN as REDUC_MIN_EXPR is not a valid GENERIC code. Regression tested on aarch64-none-elf with no regressions. Thanks, James --- gcc/ 2013-04-30 James Greenhalgh * config/aarch64/aarch64-builtins (aarch64_gimple_fold_builtin): Fold reduc__ builtins. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 3016f25..8eb32c6 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1372,6 +1372,21 @@ aarch64_gimple_fold_builtin (gimple_stmt_iterator *gsi) args[0], NULL_TREE); break; + BUILTIN_VDQIF (UNOP, reduc_smax_, 10) + new_stmt = gimple_build_assign_with_ops ( + REDUC_MAX_EXPR, + gimple_call_lhs (stmt), + args[0], + NULL_TREE); + break; + BUILTIN_VDQIF (UNOP, reduc_smin_, 10) + new_stmt = gimple_build_assign_with_ops ( + REDUC_MIN_EXPR, + gimple_call_lhs (stmt), + args[0], + NULL_TREE); + break; + default: break; }
Re: [wwwdocs] C++14 support for binary literals says Noinstead of Yes
I've updated the webpage. Jason
[AARCH64] Split movtf_aarch64 pattern
Hi, The attached patch is part of the ongoing work to enhance instruction scheduling opportunities in AArch64. This patch splits a few alternatives of the movtf_aarch64 pattern, which used to issue 2 consecutive instructions. Tested successfully with a full aarch64-elf regression run. OK for trunk? Thanks Sofiane aarch64-split-movtf.diff Description: Binary data
Re: [wwwdocs] C++14 support for binary literals says Noinstead of Yes
On Tue, Apr 30, 2013 at 11:23:49AM -0400, Jason Merrill wrote: > I've updated the webpage. Perhaps it would be nice if we had some testsuite coverage for it too, right now unless I'm blind there are exactly 2 testcases, using one 0b... number in each in g++.dg/. At least port gcc.dg/binary-constants-*.c to C++ (or move to c-c++-common/) and perhaps have something where the numbers are used in some C++ only contexts (templates, constexprs, whatever). Jakub
Re: [PATCH, fixincludes] Fix NULL on AIX
Hi David, Looks good to me, but for a small nit: On Tue, Apr 30, 2013 at 7:40 AM, David Edelsohn wrote: > +c_fix_arg = "#ifndef NULL\n" > + "#ifdef __cplusplus\n" > + "#ifdef __GNUG__\n" > + "#define NULL\t__null\n" > + "#else\t /* ! __GNUG__ */\n" > + "#define NULL\t0L\n" > + "#endif\t /* __GNUG__ */\n" > + "#else\t /* ! __cplusplus */\n" > + "#define NULL\t((void *)0)\n" > + "#endif\t /* __cplusplus */\n" > + "#endif\t /* !NULL */"; I'd really prefer a "here string": c-fix-arg = <<- _EOF_ #ifndef NULL #ifdef __cplusplus #ifdef __GNUG__ #define NULL__null #else /* ! __GNUG__ */ #define NULL0L #endif /* __GNUG__ */ #else /* ! __cplusplus */ #define NULL((void *)0) #endif /* __cplusplus */ #endif /* !NULL */ _EOF_; Unless there is some reason you want to emphasize tabs with the "\t" escapes. I think the "here string" is easier to read.
[AArch64] Refactor reduc_plus patterns.
Hi,
This patch refactors the reduc_plus RTL patterns in the
AArch64 back-end. We do this to provide a more uniform
interface for arm_neon.h builtins. Because of this we can rewrite
the intrinsics in arm_neon.h to use these standard pattern names,
and allow the signed varients to fold to tree where appropriate.
Patch regression tested on aarch64-none-elf with no regressions.
Thanks,
James
---
gcc/
2013-04-30 James Greenhalgh
* config/aarch64/aarch64-builtins.c
(aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_.
* config/aarch64/aarch64-simd-builtins.def
(reduc_splus_): Add new modes.
(reduc_uplus_): New.
* config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove.
(reduc_uplus_v4sf): Likewise.
(reduc_splus_v4sf): Likewise.
(aarch64_addv): Likewise.
(reduc_uplus_): Likewise.
(reduc_splus_): Likewise.
(aarch64_addvv2di): Likewise.
(reduc_uplus_v2di): Likewise.
(reduc_splus_v2di): Likewise.
(aarch64_addvv2si): Likewise.
(reduc_uplus_v2si): Likewise.
(reduc_splus_v2si): Likewise.
(reduc_plus_): New.
(reduc_plus_v2di): Likewise.
(reduc_plus_v2si): Likewise.
(reduc_plus_v4sf): Likewise.
(aarch64_addpv4sf): Likewise.
* config/aarch64/arm_neon.h
(vaddv_<8, 16, 32, 64): Rewrite using builtins.
* config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV,
add UNSPEC_SADDV, UNSPEC_UADDV.
(SUADDV): New.
(sur): Add UNSPEC_SADDV, UNSPEC_UADDV.
gcc/testsuite/
2013-04-30 James Greenhalgh
* gcc.target/aarch64/vect-vaddv.c: New.
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 8eb32c6..4fdfe24 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -1365,7 +1365,7 @@ aarch64_gimple_fold_builtin (gimple_stmt_iterator *gsi)
switch (fcode)
{
- BUILTIN_VDQF (UNOP, addv, 0)
+ BUILTIN_VALL (UNOP, reduc_splus_, 10)
new_stmt = gimple_build_assign_with_ops (
REDUC_PLUS_EXPR,
gimple_call_lhs (stmt),
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 97a597e..e420173 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -234,8 +234,9 @@
BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
- /* Implemented by aarch64_addv. */
- BUILTIN_VDQF (UNOP, addv, 0)
+ /* Implemented by reduc_plus_. */
+ BUILTIN_VALL (UNOP, reduc_splus_, 10)
+ BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
/* Implemented by reduc__. */
BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 8a48739..13384aa 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1438,156 +1438,70 @@
(set_attr "simd_mode" "")]
)
-;; FP 'across lanes' add.
+;; 'across lanes' add.
-(define_insn "aarch64_addpv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=w")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")]
- UNSPEC_FADDV))]
- "TARGET_SIMD"
- "faddp\\t%0.4s, %1.4s, %1.4s"
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "simd_mode" "V4SF")]
-)
-
-(define_expand "reduc_uplus_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=w")
- (match_operand:V4SF 1 "register_operand" "w"))]
- "TARGET_SIMD"
-{
- rtx tmp = gen_reg_rtx (V4SFmode);
- emit_insn (gen_aarch64_addpv4sf (tmp, operands[1]));
- emit_insn (gen_aarch64_addpv4sf (operands[0], tmp));
- DONE;
-})
-
-(define_expand "reduc_splus_v4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=w")
- (match_operand:V4SF 1 "register_operand" "w"))]
- "TARGET_SIMD"
-{
- rtx tmp = gen_reg_rtx (V4SFmode);
- emit_insn (gen_aarch64_addpv4sf (tmp, operands[1]));
- emit_insn (gen_aarch64_addpv4sf (operands[0], tmp));
- DONE;
-})
-
-(define_expand "aarch64_addvv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=w")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "w")]
- UNSPEC_FADDV))]
- "TARGET_SIMD"
-{
- emit_insn (gen_reduc_splus_v4sf (operands[0], operands[1]));
- DONE;
-})
-
-(define_insn "aarch64_addv"
- [(set (match_operand:V2F 0 "register_operand" "=w")
- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
- UNSPEC_FADDV))]
- "TARGET_SIMD"
- "faddp\\t%0, %1."
- [(set_attr "simd_type" "simd_fadd")
- (set_attr "simd_mode" "")]
-)
-
-(define_expand "reduc_uplus_"
- [(set (match_operand:V2F 0 "register_operand" "=w")
- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
- UNSPEC_FADDV))]
- "TARGET_SIMD"
- ""
-)
-
-(define_expand "reduc_splus_"
- [(set (match_operand:V2F 0 "register_operand" "=w")
- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
- UNSPEC
Re: Re: [wwwdocs] C++14 support for binary literals says Noinstead of Yes
On 04/30/13, Jakub Jelinek wrote: On Tue, Apr 30, 2013 at 11:23:49AM -0400, Jason Merrill wrote: > I've updated the webpage. Perhaps it would be nice if we had some testsuite coverage for it too, right now unless I'm blind there are exactly 2 testcases, using one 0b... number in each in g++.dg/. At least port gcc.dg/binary-constants-*.c to C++ (or move to c-c++-common/) and perhaps have something where the numbers are used in some C++ only contexts (templates, constexprs, whatever). Jakub I've been meaning to throw together a user-defined literal test for octal and hex. I'll add binary literals too. I've used literals on octal and hex numbers and I know they work but it would be nice to have in the testsuite. Usage of literal operators on octal, hex, and now binary literals are explicitly called out in the standard (somewhere). Ed
Re: [patch] Fix node weight updates during ipa-cp (issue7812053)
On Tue, Apr 30, 2013 at 7:02 AM, Teresa Johnson wrote: > On Mon, Apr 29, 2013 at 12:35 PM, H.J. Lu wrote: >> On Mon, Apr 29, 2013 at 10:31 AM, Teresa Johnson >> wrote: >>> FYI, Fixed in r198416. >>> >>> Thanks, >>> Teresa >>> >> >> I noticed that sometimes GCC generates: >> >> _8 = memcpy (ret_6, s_2(D), len_4); >> _8 = memcpy (ret_6, s_2(D), len_4); >> memcpy (_17, buffer_12(D), add_16); >> memcpy (_17, buffer_12(D), add_16); >> memcpy (_25, _28, _27); >> memcpy (_25, _28, _27); >> memcpy (_39, buffer_2, len_4); >> memcpy (_39, buffer_2, len_4); >> memcpy (_16, &fillbuf, pad_1); >> memcpy (_16, &fillbuf, pad_1); > > I am getting this too with a profiledbootstrap with LTO. However, this > isn't due to my changes. I had confirmed that after reverting my > changes (r197595 and now the follow-on fix r198416) this problem still > occurs. > > Teresa There is a strayed debug_gimple_stmt. I am checking in this patch to fix it. -- H.J. --- diff --git a/gcc/value-prof.c b/gcc/value-prof.c index 3348d7f..b665b1c 100644 --- a/gcc/value-prof.c +++ b/gcc/value-prof.c @@ -416,7 +416,6 @@ stream_in_histogram_value (struct lto_input_block *ib, gimple stmt) new_val->n_counters = ncounters; for (i = 0; i < ncounters; i++) new_val->hvalue.counters[i] = streamer_read_gcov_count (ib); - debug_gimple_stmt (stmt); if (!next_p) gimple_add_histogram_value (cfun, stmt, new_val); else
Re: [C++ Patch/RFC] PR 57092
On 04/30/2013 03:14 PM, Jason Merrill wrote: On 04/30/2013 08:03 AM, Paolo Carlini wrote: I'm wondering if handling the additional TREE_CODE in finish_decltype_type isn't overall preferable (assuming we wouldn't end up soon handling all sorts of *_EXPR ;) That's exactly the problem; it wouldn't stop with ADDR_EXPR, we would need to handle any form of expression that could be a template non-type argument. Ok. Currently, in some cases (see, eg, template/canon-type-9.C) we have that id is true and DECLTYPE_TYPE_EXPR (t) is a TEMPLATE_PARM_INDEX but the tsubst_copy_and_build call returns a TEMPLATE_PARM_INDEX again, not an ADDR_EXPR, not an expression, and inside finish_decltype_type the instantiation_dependent_expression_p returns true. Shall we also additionally check something like EXPR_P (type) in the special casing? And then, is just type = TREE_TYPE (type) instead of calling finish_decltype_type enough? Too many questions, I know, if you feel like just working on this issue and handle yourself the tricky details I'm still missing, just let me know... Thanks, Paolo.
Re: RFA: Use gen_int_mode in plus_constant
Richard Sandiford wrote:
>This patch fixes out the GEN_INT/gen_int_mode that Richard pointed out
>in the wide-int review. It also passes "mode" rather than "VOIDmode"
>to immed_double_int_const. (As discussed in that thread, the latter
>change shouldn't make any difference in practice, but is still more
>correct in principle.)
>
>Bootstrapped & regression-tested on x86_64-linux-gnu. OK to install?
Ok.
Thanks,
Richard.
>Richard
>
>gcc/
> * explow.c (plus_constant): Pass "mode" to immed_double_int_const.
> Use gen_int_mode rather than GEN_INT.
>
>Index: gcc/explow.c
>===
>--- gcc/explow.c 2013-02-25 09:41:58.0 +
>+++ gcc/explow.c 2013-04-30 15:52:57.270362112 +0100
>@@ -106,10 +106,10 @@ plus_constant (enum machine_mode mode, r
> if (overflow)
> gcc_unreachable ();
>
>-return immed_double_int_const (v, VOIDmode);
>+return immed_double_int_const (v, mode);
> }
>
>- return GEN_INT (INTVAL (x) + c);
>+ return gen_int_mode (INTVAL (x) + c, mode);
>
> case CONST_DOUBLE:
> {
>@@ -124,7 +124,7 @@ plus_constant (enum machine_mode mode, r
>To fix, add constant support wider than CONST_DOUBLE. */
> gcc_assert (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_DOUBLE_INT);
>
>- return immed_double_int_const (v, VOIDmode);
>+ return immed_double_int_const (v, mode);
> }
>
> case MEM:
[gomp4] Some nesting region check adjustments
Hi!
I've adjusted what I could now in check_omp_nesting_restrictions to match
the 4.0 draft.
2013-04-30 Jakub Jelinek
* omp-low.c (check_omp_nesting_restrictions): Diagnose
OpenMP constructs nested inside simd region. Don't treat
#pragma omp simd as work-sharing region. Disallow work-sharing
constructs inside of critical region. Complain if ordered
region is nested inside of parallel region without loop
region in between.
(scan_omp_1_stmt): Call check_omp_nesting_restrictions even
for GOMP_{cancel{,lation_point},taskyield,taskwait} calls.
* gfortran.dg/gomp/appendix-a/a.35.5.f90: Add dg-error.
--- gcc/omp-low.c.jj2013-04-23 16:15:06.0 +0200
+++ gcc/omp-low.c 2013-04-30 10:26:40.402771053 +0200
@@ -1859,9 +1859,21 @@ scan_omp_single (gimple stmt, omp_contex
static bool
check_omp_nesting_restrictions (gimple stmt, omp_context *ctx)
{
+ if (ctx != NULL
+ && gimple_code (ctx->stmt) == GIMPLE_OMP_FOR
+ && (gimple_omp_for_kind (ctx->stmt) == GF_OMP_FOR_KIND_SIMD
+ || gimple_omp_for_kind (ctx->stmt) == GF_OMP_FOR_KIND_FOR_SIMD))
+{
+ error_at (gimple_location (stmt),
+ "OpenMP constructs may not be nested inside simd region");
+ return false;
+}
switch (gimple_code (stmt))
{
case GIMPLE_OMP_FOR:
+ if (gimple_omp_for_kind (stmt) == GF_OMP_FOR_KIND_SIMD)
+ return true;
+ /* FALLTHRU */
case GIMPLE_OMP_SECTIONS:
case GIMPLE_OMP_SINGLE:
case GIMPLE_CALL:
@@ -1874,8 +1886,12 @@ check_omp_nesting_restrictions (gimple s
case GIMPLE_OMP_ORDERED:
case GIMPLE_OMP_MASTER:
case GIMPLE_OMP_TASK:
+ case GIMPLE_OMP_CRITICAL:
if (is_gimple_call (stmt))
{
+ if (DECL_FUNCTION_CODE (gimple_call_fndecl (stmt))
+ != BUILT_IN_GOMP_BARRIER)
+ return true;
error_at (gimple_location (stmt),
"barrier region may not be closely nested inside "
"of work-sharing, critical, ordered, master or "
@@ -1932,7 +1948,10 @@ check_omp_nesting_restrictions (gimple s
}
return true;
case GIMPLE_OMP_PARALLEL:
- return true;
+ error_at (gimple_location (stmt),
+ "ordered region must be closely nested inside "
+ "a loop region with an ordered clause");
+ return false;
default:
break;
}
@@ -2029,9 +2048,20 @@ scan_omp_1_stmt (gimple_stmt_iterator *g
else if (is_gimple_call (stmt))
{
tree fndecl = gimple_call_fndecl (stmt);
- if (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL
- && DECL_FUNCTION_CODE (fndecl) == BUILT_IN_GOMP_BARRIER)
- remove = !check_omp_nesting_restrictions (stmt, ctx);
+ if (fndecl
+ && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
+ switch (DECL_FUNCTION_CODE (fndecl))
+ {
+ case BUILT_IN_GOMP_BARRIER:
+ case BUILT_IN_GOMP_CANCEL:
+ case BUILT_IN_GOMP_CANCELLATION_POINT:
+ case BUILT_IN_GOMP_TASKYIELD:
+ case BUILT_IN_GOMP_TASKWAIT:
+ remove = !check_omp_nesting_restrictions (stmt, ctx);
+ break;
+ default:
+ break;
+ }
}
if (remove)
{
--- gcc/testsuite/gfortran.dg/gomp/appendix-a/a.35.5.f90.jj 2013-03-20
10:05:25.462181487 +0100
+++ gcc/testsuite/gfortran.dg/gomp/appendix-a/a.35.5.f902013-04-30
17:24:27.805425874 +0200
@@ -6,7 +6,7 @@
!$OMP CRITICAL
CALL WORK(N,1)
! incorrect nesting of barrier region in a critical region
-!$OMP BARRIER
+!$OMP BARRIER ! { dg-error "region may not be closely nested inside of" }
CALL WORK(N,2)
!$OMP END CRITICAL
!$OMP END PARALLEL
Jakub
[gomp4] Tiny c-family addition
Hi!
Just one tiny omission (but neither of the parsers can parse the accelerator
stuff yet).
2013-04-30 Jakub Jelinek
* c-pragma.c (omp_pragmas): Add PRAGMA_OMP_DISTRIBUTE.
--- gcc/c-family/c-pragma.c.jj 2013-03-27 13:01:09.0 +0100
+++ gcc/c-family/c-pragma.c 2013-04-30 15:18:35.473478963 +0200
@@ -1166,6 +1166,7 @@ static const struct omp_pragma_def omp_p
{ "cancellation", PRAGMA_OMP_CANCELLATION_POINT },
{ "critical", PRAGMA_OMP_CRITICAL },
{ "declare", PRAGMA_OMP_DECLARE_REDUCTION },
+ { "distribute", PRAGMA_OMP_DISTRIBUTE },
{ "end", PRAGMA_OMP_END_DECLARE_TARGET },
{ "flush", PRAGMA_OMP_FLUSH },
{ "for", PRAGMA_OMP_FOR },
Jakub
[gomp4] Handle seq_cst clause on OpenMP atomics
Hi!
Something I've missed in the latest draft, there can be seq_cst
clause to request sequentially atomic operation as opposed to relaxed.
Handled thusly:
2013-04-30 Jakub Jelinek
* gimple-pretty-print.c (dump_gimple_omp_atomic_load,
dump_gimple_omp_atomic_store): Handle gimple_omp_atomic_seq_cst_p.
* gimple.h (enum gf_mask): Add GF_OMP_ATOMIC_SEQ_CST.
(gimple_omp_atomic_set_seq_cst, gimple_omp_atomic_seq_cst_p): New
inline functions.
* omp-low.c (expand_omp_atomic_load, expand_omp_atomic_store,
expand_omp_atomic_fetch_op): If gimple_omp_atomic_seq_cst_p,
pass MEMMODEL_SEQ_CST instead of MEMMODEL_RELAXED to the builtin.
* gimplify.c (gimplify_omp_atomic): Handle OMP_ATOMIC_SEQ_CST.
* tree-pretty-print.c (dump_generic_node): Handle OMP_ATOMIC_SEQ_CST.
* tree.def (OMP_ATOMIC): Add comment that OMP_ATOMIC* must stay
consecutive.
* tree.h (OMP_ATOMIC_SEQ_CST): Define.
c/
* c-parser.c (c_parser_omp_atomic): Parse seq_cst clause, pass
true if it is present to c_finish_omp_atomic.
cp/
* pt.c (tsubst_expr): Pass OMP_ATOMIC_SEQ_CST to finish_omp_atomic.
* semantics.c (finish_omp_atomic): Add seq_cst argument, pass
it through to c_finish_omp_atomic or store into OMP_ATOMIC_SEQ_CST.
* cp-tree.h (finish_omp_atomic): Adjust prototype.
* parser.c (cp_parser_omp_atomic): Parse seq_cst clause, pass
true if it is present to finish_omp_atomic.
c-family/
* c-omp.c (c_finish_omp_atomic): Add seq_cst argument, store it
into OMP_ATOMIC_SEQ_CST bit.
* c-common.h (c_finish_omp_atomic): Adjust prototype.
testsuite/
* testsuite/libgomp.c/atomic-17.c: New test.
* testsuite/libgomp.c++/atomic-14.C: New test.
* testsuite/libgomp.c++/atomic-15.C: New test.
--- gcc/gimple-pretty-print.c.jj2013-03-27 13:01:09.0 +0100
+++ gcc/gimple-pretty-print.c 2013-04-30 17:34:10.663125084 +0200
@@ -1805,6 +1805,8 @@ dump_gimple_omp_atomic_load (pretty_prin
else
{
pp_string (buffer, "#pragma omp atomic_load");
+ if (gimple_omp_atomic_seq_cst_p (gs))
+ pp_string (buffer, " seq_cst");
if (gimple_omp_atomic_need_value_p (gs))
pp_string (buffer, " [needed]");
newline_and_indent (buffer, spc + 2);
@@ -1835,6 +1837,8 @@ dump_gimple_omp_atomic_store (pretty_pri
else
{
pp_string (buffer, "#pragma omp atomic_store ");
+ if (gimple_omp_atomic_seq_cst_p (gs))
+ pp_string (buffer, "seq_cst ");
if (gimple_omp_atomic_need_value_p (gs))
pp_string (buffer, "[needed] ");
pp_character (buffer, '(');
--- gcc/c/c-parser.c.jj 2013-04-24 18:22:37.0 +0200
+++ gcc/c/c-parser.c2013-04-30 16:32:45.967276133 +0200
@@ -10218,10 +10218,23 @@ c_parser_omp_atomic (location_t loc, c_p
location_t eloc;
bool structured_block = false;
bool swapped = false;
+ bool seq_cst = false;
if (c_parser_next_token_is (parser, CPP_NAME))
{
const char *p = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value);
+ if (!strcmp (p, "seq_cst"))
+ {
+ seq_cst = true;
+ c_parser_consume_token (parser);
+ if (c_parser_next_token_is (parser, CPP_COMMA)
+ && c_parser_peek_2nd_token (parser)->type == CPP_NAME)
+ c_parser_consume_token (parser);
+ }
+}
+ if (c_parser_next_token_is (parser, CPP_NAME))
+{
+ const char *p = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value);
if (!strcmp (p, "read"))
code = OMP_ATOMIC_READ;
@@ -10236,6 +10249,23 @@ c_parser_omp_atomic (location_t loc, c_p
if (p)
c_parser_consume_token (parser);
}
+ if (!seq_cst)
+{
+ if (c_parser_next_token_is (parser, CPP_COMMA)
+ && c_parser_peek_2nd_token (parser)->type == CPP_NAME)
+ c_parser_consume_token (parser);
+
+ if (c_parser_next_token_is (parser, CPP_NAME))
+ {
+ const char *p
+ = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value);
+ if (!strcmp (p, "seq_cst"))
+ {
+ seq_cst = true;
+ c_parser_consume_token (parser);
+ }
+ }
+}
c_parser_skip_to_pragma_eol (parser);
switch (code)
@@ -10526,7 +10556,7 @@ done:
}
else
stmt = c_finish_omp_atomic (loc, code, opcode, lhs, rhs, v, lhs1, rhs1,
- swapped);
+ swapped, seq_cst);
if (stmt != error_mark_node)
add_stmt (stmt);
--- gcc/gimple.h.jj 2013-03-27 13:01:09.0 +0100
+++ gcc/gimple.h2013-04-30 16:02:24.164400181 +0200
@@ -114,6 +114,7 @@ enum gf_mask {
GF_OMP_SECTION_LAST= 1 << 0,
GF_OMP_ATOMIC_NEED_VALUE = 1 << 0,
+GF_OMP_ATOMIC_SEQ_CST = 1 << 1,
GF_PREDICT_TAKEN = 1 << 15
};
@@ -1727,6 +1728,29 @@ gimple_omp_atomic_
Re: [PATCH, wwwdocs] Fix PR 50642
On Tue, 30 Apr 2013, Shakthi Kannan wrote: > Hi, > > - Original Message - > | From: "Joseph S. Myers" > | > | onlinedocs copies of manuals are generated by > | maintainer-scripts/update_web_docs_svn, which doesn't use any makefiles. > \-- > > Could you please list the pre-requisite steps needed to run the above? The script is only designed to be run from the gccadmin account on gcc.gnu.org. -- Joseph S. Myers jos...@codesourcery.com
[Patch, ARM][11/n] Split patterns that output multiple assembly instructions - thumb2.md
This patch continues to clean up patterns that output multiple assembly instructions. It handles most of the patterns in thumb2.md. The following patterns are not split: thumb2_movcond, thumb2_cond_move - complex, maybe later. tls_load_dot_plus_four - won't split: uses asm_out in output statement. thumb2_cbz - won't split: uses pc in length attribute and length in output statement. thumb2_cbnz - likewise. No regression on qemu for arm-none-eabi. Bootstrap successful on Cortex-A15. Ok for trunk? Thanks, Greta 2013-04-24 Greta Yorsh * config/arm/thumb2.md (thumb2_smaxsi3,thumb2_sminsi3): Convert define_insn to define_insn_and_split. (thumb32_umaxsi3,thumb2_uminsi3): Likewise. (thumb2_negdi2,thumb2_abssi2,thumb2_neg_abssi2): Likewise. (thumb2_mov_scc,thumb2_mov_negscc,thumb2_mov_notscc): Likewise. (thumb2_movsicc_insn,thumb2_and_scc,thumb2_ior_scc): Likewise. (thumb2_negscc): Likewise.diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 697350c..92ae8f4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -64,81 +38,167 @@ (set_attr "type" "alu_shift")] ) -(define_insn "*thumb2_smaxsi3" +(define_insn_and_split "*thumb2_smaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand""rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" - "@ - cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 - cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1 - cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2" + "#" + ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2 + ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1 + ; cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2 + "TARGET_THUMB2" + [(set (reg:CC CC_REGNUM) +(compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) +(if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "10,10,14")] ) -(define_insn "*thumb2_sminsi3" +(define_insn_and_split "*thumb2_sminsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" - "@ - cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 - cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1 - cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2" + "#" + ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2 + ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1 + ; cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2" + "TARGET_THUMB2" + [(set (reg:CC CC_REGNUM) +(compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) +(if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "10,10,14")] ) -(define_insn "*thumb32_umaxsi3" +(define_insn_and_split "*thumb32_umaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" - "@ - cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 - cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1 - cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2" + "#" + ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2 + ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1 + ; cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2" + "TARGET_THUMB2" + [(set (reg:CC CC_REGNUM) +(compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) +(if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "10,10,14")] ) -(define_insn "*thumb2_uminsi3" +(define_insn_and_split "*thumb2_uminsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_THUMB2" - "@ - cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 - cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1 - cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2" + "#" + ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2 + ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1 + ; cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2" + "TARGET_THUMB2" + [(set (reg:CC CC_REGNUM) +(compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) +(if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) +
Re: [PATCH, fixincludes] Fix NULL on AIX
On Tue, Apr 30, 2013 at 11:28 AM, Bruce Korb wrote: > Hi David, > > Looks good to me, but for a small nit: > Unless there is some reason you want to emphasize tabs with the "\t" escapes. > I think the "here string" is easier to read. I coped c_fix_arg from openbsd_null_definition fix. I don't know if two different formats for similar fixes would be confusing, but I do not have a problem using the EOF version. Do you have any comment about the change to void_null fix? Thanks, David
Re: [C++ Patch/RFC] PR 57092
... sorry about the latter confabulations ;) I went almost crazy trying
to avoid the copy_node, but in this case it seems really necessary. The
below appears to regtest fine (already beyond g++.dg/dg.exp).
Thanks,
Paolo.
///
Index: cp/pt.c
===
--- cp/pt.c (revision 198461)
+++ cp/pt.c (working copy)
@@ -11781,14 +11781,23 @@ tsubst (tree t, tree args, tsubst_flags_t complain
case DECLTYPE_TYPE:
{
tree type;
+ tree expr = DECLTYPE_TYPE_EXPR (t);
+ bool id = DECLTYPE_TYPE_ID_EXPR_OR_MEMBER_ACCESS_P (t);
++cp_unevaluated_operand;
++c_inhibit_evaluation_warnings;
- type = tsubst_copy_and_build (DECLTYPE_TYPE_EXPR (t), args,
- complain|tf_decltype, in_decl,
- /*function_p*/false,
- /*integral_constant_expression*/false);
+ if (id && TREE_CODE (expr) == TEMPLATE_PARM_INDEX)
+ {
+ type = copy_node (expr);
+ TREE_TYPE (type) = tsubst (TREE_TYPE (expr), args,
+ complain|tf_decltype, in_decl);
+ }
+ else
+ type = tsubst_copy_and_build (expr, args,
+ complain|tf_decltype, in_decl,
+ /*function_p*/false,
+ /*integral_constant_expression*/false);
--cp_unevaluated_operand;
--c_inhibit_evaluation_warnings;
@@ -11800,8 +11809,7 @@ tsubst (tree t, tree args, tsubst_flags_t complain
type = lambda_proxy_type (type);
else
{
- bool id = DECLTYPE_TYPE_ID_EXPR_OR_MEMBER_ACCESS_P (t);
- if (id && TREE_CODE (DECLTYPE_TYPE_EXPR (t)) == BIT_NOT_EXPR
+ if (id && TREE_CODE (expr) == BIT_NOT_EXPR
&& EXPR_P (type))
/* In a template ~id could be either a complement expression
or an unqualified-id naming a destructor; if instantiating
Index: testsuite/g++.dg/cpp0x/decltype53.C
===
--- testsuite/g++.dg/cpp0x/decltype53.C (revision 0)
+++ testsuite/g++.dg/cpp0x/decltype53.C (working copy)
@@ -0,0 +1,11 @@
+// PR c++/57092
+// { dg-do compile { target c++11 } }
+
+template
+class B {
+ decltype(F) v;
+};
+
+void foo(int) {}
+
+B o;
RE: [PATCH][ARM] Fix PR 56809
> -Original Message- > From: Ramana Radhakrishnan > Sent: 03 April 2013 16:16 > To: Kyrylo Tkachov > Cc: GCC Patches > Subject: Re: [PATCH][ARM] Fix PR 56809 > > On 04/03/13 16:07, Kyrylo Tkachov wrote: > > Hi all, > > > > This patch fixes an ICE that we encounter when building gcc on arm > targets. > > The jump table reorganisation exposed a bug in the backend. > > This fixes it > > by using next_active_insn instead of next_real_insn when looking for > the > > diff vector in the jump table handling code. (Thanks to Steven > Bosscher for > > the tip). > > > > A separate aarch64 patch is coming soon separately. > > > > Tested arm-none-eabi on qemu and confirmed that the build for > > arm-none-linux-gnueabi is fixed. > > Since the PR affects both arm and aarch64 I put a testcase into > gcc.dg. > > > > Ok for trunk? > > Ok for trunk. Given that this fixes a latent bug, is it ok to backport to 4.8 and 4.7? Tested the patch on those branches with no regressions on arm-none-eabi. Thanks, Kyrill > > regards > Ramana
[Patch,ARM,Committed] Remove trailing whitespaces in thumb2.md
Remove trailing whitespaces in thumb2.md. Committed as obvious (trunk r198464). Thanks, Greta 2013-04-30 Greta Yorsh * config/arm/thumb2.md: Remove trailing whitespaces.diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 697350c..3aa7247 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -50,7 +50,7 @@ (set_attr "length" "6,10")] ) -;; Thumb-2 only allows shift by constant on data processing instructions +;; Thumb-2 only allows shift by constant on data processing instructions (define_insn "*thumb_andsi_not_shiftsi_si" [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (not:SI (match_operator:SI 4 "shift_operator" @@ -330,7 +330,7 @@ [(set_attr "conds" "clob")] ) ;; Don't define thumb2_load_indirect_jump because we can't guarantee label -;; addresses will have the thumb bit set correctly. +;; addresses will have the thumb bit set correctly. (define_insn "*thumb2_and_scc" @@ -401,7 +401,7 @@ (define_insn "*thumb2_cond_arith" [(set (match_operand:SI 0 "s_register_operand" "=r,r") -(match_operator:SI 5 "shiftable_operator" +(match_operator:SI 5 "shiftable_operator" [(match_operator:SI 4 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) @@ -864,7 +864,7 @@ else return \"cmp\\t%0, #0\;beq\\t%l1\"; " - [(set (attr "length") + [(set (attr "length") (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int 2)) (le (minus (match_dup 1) (pc)) (const_int 128)) @@ -887,7 +887,7 @@ else return \"cmp\\t%0, #0\;bne\\t%l1\"; " - [(set (attr "length") + [(set (attr "length") (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int 2)) (le (minus (match_dup 1) (pc)) (const_int 128))
[Patch, Fortran] Avoid segfault in conformable_arrays
The issue was found by Reinhold Bader when testing the Fortran-Dev
branch (thanks!), but it also affects GCC 4.6 and later.
The patch is rather obvious: The segfault occured as tail->u.ar.start[i]
== NULL. An alternative is to could use "continue" instead of "break".
Build and regtested on x86-64-gnu-linux.
OK for the trunk?
Tobias
PS: The test case is invalid Fortran 2003 but valid Fortran 2008. As
gfortran lacks that feature, it unconditionally rejects the test case.
Work around is to add a "(1)" to the alloc-expr.
2013-04-30 Tobias Burnus
* resolve.c (conformable_arrays): Avoid segfault
when ar.start[i] == NULL.
2013-04-30 Tobias Burnus
* gfortran.dg/allocate_with_source_3.f90: New.
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index 6e1f56f..0f2fce0 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -6498,24 +6498,27 @@ conformable_arrays (gfc_expr *e1, gfc_expr *e2)
return false;
}
if (e1->shape)
{
int i;
mpz_t s;
mpz_init (s);
for (i = 0; i < e1->rank; i++)
{
+ if (tail->u.ar.start[i] == NULL)
+ break;
+
if (tail->u.ar.end[i])
{
mpz_set (s, tail->u.ar.end[i]->value.integer);
mpz_sub (s, s, tail->u.ar.start[i]->value.integer);
mpz_add_ui (s, s, 1);
}
else
{
mpz_set (s, tail->u.ar.start[i]->value.integer);
}
if (mpz_cmp (e1->shape[i], s) != 0)
--- /dev/null 2013-04-30 09:21:48.687062896 +0200
+++ gcc/gcc/testsuite/gfortran.dg/allocate_with_source_3.f90 2013-04-30 18:13:52.884740171 +0200
@@ -0,0 +1,28 @@
+! { dg-do compile }
+!
+! Contributed by Reinhold Bader
+!
+program assumed_shape_01
+ use, intrinsic :: iso_c_binding
+ implicit none
+ type, bind(c) :: cstruct
+ integer(c_int) :: i
+ real(c_float) :: r(2)
+ end type cstruct
+ interface
+ subroutine psub(this, that) bind(c, name='Psub')
+ import :: c_float, cstruct
+ real(c_float) :: this(:,:)
+ type(cstruct) :: that(:)
+ end subroutine psub
+ end interface
+
+ real(c_float) :: t(3,7)
+ type(cstruct), pointer :: u(:)
+
+! The following is VALID Fortran 2008 but NOT YET supported
+ allocate(u, source=[cstruct( 4, [1.1,2.2] ) ]) ! { dg-error "Array specification required in ALLOCATE statement" }
+ call psub(t, u)
+ deallocate (u)
+
+end program assumed_shape_01
Re: [PATCH, fixincludes] Fix NULL on AIX
Hi,
On Tue, Apr 30, 2013 at 9:42 AM, David Edelsohn wrote:
> I coped c_fix_arg from openbsd_null_definition fix. I don't know if
> two different formats for similar fixes would be confusing, but I do
> not have a problem using the EOF version.
I haven't reviewed all patches and I don't always raise nits.
> Do you have any comment about the change to void_null fix?
By analogy, I'd prefer the EOF version there, too. But ultimately,
it works and is not exactly illegible, so I have no serious objection
to the fix. It would be nice if it were combinable, but doing so is
tricky. I'm guessing that the fix on AIX is separated because the
headers contain "__cplusplus" and that is used as an exclusion test
for the "void_null" fix? Otherwise this:
select= "^#[ \t]*define[ \t]+NULL[ \t]+("
"\\(\\(void[ \t]*\\*\\)0\\)" "|" "\\(*0L*\\)*" ")";
would allow void_null to work for you -- perhaps by using %1 somewhere
in the replacement "c-fix-arg".
Cheers - Bruce
[PATCH,ARM] Internal memcpy using LDRD/STRD
This patch for gcc's internal memcpy emits LDRD/STRD whenever
possible, if prefer_ldrd_strd field is set in tune_params.
It uses DImode moves in both ARM and Thumb modes.
The generic move_by_pieces implementation cannot be used as is
to generate the same instruction sequence.
To handle cases in which either source or destination is not word-aligned,
this patch introduces new patterns for UNSPEC_UNALIGNED double-word access.
After reload, the pattern is split into two unaligned single-word accesses.
It prevents lower_subreg from splitting an aligned double-word access
that depends on the unaligned access.
This may become unnecessary when the cost model is fixed.
This patch also adjusts existing tests to accept LDRD/STRD or LDM/STM
depending on effective target arm_prefer_ldrd_strd.
An early version of this patch was posted here:
http://gcc.gnu.org/ml/gcc-patches/2011-11/msg00921.html
The new version is simpler because it generates
(a) the same RTL for both Thumb and ARM modes, and
(b) load and store blocks are matched, i.e., no need for store_partial_word
subroutine any more.
The previous version did not use DImode moves in Thumb mode.
Instead, it relied on LDRD/STRD patterns introduced by patches for
Thumb prolog/epilog using LDRD/STRD. These patterns were not approved,
because of a potential problem with reload, see here:
http://gcc.gnu.org/ml/gcc-patches/2012-10/msg01807.html
A slightly modified version of these patterns, approved and committed,
matches only
after reload, whereas the RTL insns for internal memcpy are generated
early on, during expand. There might be missed optimization
opportunities in Thumb mode.
No regression on qemu for arm-none-eabi with cpu cortex-a15 arm/thumb.
Bootstrap successful on Cortex-A15.
Ok for trunk?
Thanks,
Greta
ChangeLog
gcc/
2013-04-30 Greta Yorsh
* config/arm/arm-protos.h (gen_movmem_ldrd_strd): New declaration.
* config/arm/arm.c (next_consecutive_mem): New function.
(gen_movmem_ldrd_strd): Likewise.
* config/arm/arm.md (movmemqi): Update condition and code.
(unaligned_loaddi, unaligned_storedi): New patterns.
gcc/testsuite
2013-04-30 Greta Yorsh
* gcc.target/arm/unaligned-memcpy-2.c: Adjust expected output.
* gcc.target/arm/unaligned-memcpy-3.c: Likewise.
* gcc.target/arm/unaligned-memcpy-4.c: Likewise.diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 4274c0d..9e43419 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -119,6 +119,7 @@ extern rtx arm_gen_store_multiple (int *, int, rtx, int,
rtx, HOST_WIDE_INT *);
extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
extern int arm_gen_movmemqi (rtx *);
+extern bool gen_movmem_ldrd_strd (rtx *);
extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
HOST_WIDE_INT);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 231a27f..a3b9787 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -11836,6 +11836,134 @@ arm_gen_movmemqi (rtx *operands)
return 1;
}
+/* Helper for gen_movmem_ldrd_strd. Increase the address of memory rtx
+by mode size. */
+inline static rtx
+next_consecutive_mem (rtx mem)
+{
+ enum machine_mode mode = GET_MODE (mem);
+ HOST_WIDE_INT offset = GET_MODE_SIZE (mode);
+ rtx addr = plus_constant (Pmode, XEXP (mem, 0), offset);
+
+ return adjust_automodify_address (mem, mode, addr, offset);
+}
+
+/* Copy using LDRD/STRD instructions whenever possible.
+ Returns true upon success. */
+bool
+gen_movmem_ldrd_strd (rtx *operands)
+{
+ unsigned HOST_WIDE_INT len;
+ HOST_WIDE_INT align;
+ rtx src, dst, base;
+ rtx reg0;
+ bool src_aligned, dst_aligned;
+ bool src_volatile, dst_volatile;
+
+ gcc_assert (CONST_INT_P (operands[2]));
+ gcc_assert (CONST_INT_P (operands[3]));
+
+ len = UINTVAL (operands[2]);
+ if (len > 64)
+return false;
+
+ /* Maximum alignment we can assume for both src and dst buffers. */
+ align = INTVAL (operands[3]);
+
+ if ((!unaligned_access) && (len >= 4) && ((align & 3) != 0))
+return false;
+
+ /* Place src and dst addresses in registers
+ and update the corresponding mem rtx. */
+ dst = operands[0];
+ dst_volatile = MEM_VOLATILE_P (dst);
+ dst_aligned = MEM_ALIGN (dst) >= BITS_PER_WORD;
+ base = copy_to_mode_reg (SImode, XEXP (dst, 0));
+ dst = adjust_automodify_address (dst, VOIDmode, base, 0);
+
+ src = operands[1];
+ src_volatile = MEM_VOLATILE_P (src);
+ src_aligned = MEM_ALIGN (src) >= BITS_PER_WORD;
+ base = copy_to_mode_reg (SImode, XEXP (src, 0));
+ src = adjust_automodify_address (src, VOIDmode, base, 0);
+
+ if (!unaligned_access && !(src_aligned && dst_aligned))
+return false;
+
+ if (src_volatile || dst_volatile)
+return false;
+
+ /* If
Re: [AArch64] Improve description of CM instructions in RTL
OK /Marcus On 30 April 2013 15:55, James Greenhalgh wrote: > > Comparison operators can be described in RTL in a more accurate > manner than simply using UNSPECs. Do this. > > We need the split cases for DI mode to give reload a sensible > alternative. Without these, reload would churn out some truly > ugly code along the lines of: > >> fmov d0, x0 >> cmp d0, d0, #0 >> fmov x0, d0 > > Regression tested on aarch64-none-elf and aarch64-none-linux-gnu > with no regressions. > > OK? > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... > (cmgeu): ...This. > (cmhi): Rename to... > (cmgtu): ...This. > * config/aarch64/aarch64-simd.md > (simd_mode): Add SF. > (aarch64_vcond_internal): Use new names for unsigned comparison insns. > (aarch64_cm): Rewrite to not use UNSPECs. > * config/aarch64/aarch64.md (*cstore_neg): Rename to... > (cstore_neg): ...This. > * config/aarch64/iterators.md > (VALLF): new. > (unspec): Remove UNSPEC_CM. > (COMPARISONS): New. > (UCOMPARISONS): Likewise. > (optab): Add missing comparisons. > (n_optab): New. > (cmp_1): Likewise. > (cmp_2): Likewise. > (CMP): Likewise. > (cmp): Remove. > (VCMP_S): Likewise. > (VCMP_U): Likewise. > (V_cmp_result): Add DF, SF modes. > (v_cmp_result): Likewise. > (v): Likewise. > (vmtype): Likewise. > * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.
Re: [AArch64] Remap neon vcmp functions to C/TREE
OK /Marcus On 30 April 2013 15:58, James Greenhalgh wrote: > > Where possible, describe these Neon intrinsics in C. Where not > possible, remap them to a builtin which will fold to an equivalent > C function. > > Add the support code to allow folding of these instructions. > > As GE_EXPR, GT_EXPR, EQ_EXPR are GIMPLE and GENERIC codes, use > TARGET_FOLD_BUILTIN. > > Regression tested on aarch64-none-elf with only bogus regressions > (corrected in a separate patch). > > OK? > > Thanks, > James > > --- > gcc/ > > 2013-04-29 James Greenhalgh > > * config/aarch64/aarch64-builtins.c (BUILTIN_VALLDI): Define. > (aarch64_fold_builtin): Add folding for cm. > * config/aarch64/aarch64-simd-builtins.def > (cmeq): Update to BUILTIN_VALLDI. > (cmgt): Likewise. > (cmge): Likewise. > (cmle): Likewise. > (cmlt): Likewise. > * config/aarch64/arm_neon.h > (vc_<8,16,32,64>): Remap > to builtins or C as appropriate.
Re: [AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.
OK
/Marcus
On 30 April 2013 16:06, James Greenhalgh wrote:
>
> If the end goal of a VEC_COND_EXPR is to pick between
> {-1, -1, -1, -1} and {0, 0, 0, 0}
> then we do not need to do a bit select, this is just
> a move of the generated mask to the result operand.
>
> This patch checks for this case, and emits the
> appropriate instructions. This can save us loading the
> two constant masks and performing a bsl.
>
> The midend turns GE_EXPR style tree codes in to VEC_COND_EXPRS,
> so fixing this folding up earlier in the compiler is not helpful.
>
> Regression tested for aarch64-none-elf with no regressions.
>
> OK?
>
> Thanks,
> James
>
> ---
> gcc/
>
> 2013-04-30 James Greenhalgh
>
> * config/aarch64/aarch64-simd.md
> (vcond_internal): Handle special cases for constant masks.
> (vcond): Allow nonmemory_operands for outcome vectors.
> (vcondu): Likewise.
> (vcond): New.
Re: [AArch64 Testsuite] Fix fallout from FCM changes.
OK /Marcus On 30 April 2013 16:08, James Greenhalgh wrote: > > Hi, > > gcc.target/aarch64/scalar_intrinsics.c uses the vcled_s64 style > intrinsics. As these now just map to a C operation, we need to first > ensure that the arguments to these functions make their way to the > SIMD register set. > > For the >= 0 and < 0 opertaions idiom recognition will convert > them to shifts, so we also need to mop up the expectations on numbers > of shifts and generation of cmge d0, d0, #0. > > Tested to ensure test still passes. > > Thanks, > James > > --- > gcc/testsuite/ > > 2013-04-30 James Greenhalgh > > * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. > (test_vceqd_s64): Force arguments to SIMD registers. > (test_vceqzd_s64): Likewise. > (test_vcged_s64): Likewise. > (test_vcled_s64): Likewise. > (test_vcgezd_s64): Likewise. > (test_vcged_u64): Likewise. > (test_vcgtd_s64): Likewise. > (test_vcltd_s64): Likewise. > (test_vcgtzd_s64): Likewise. > (test_vcgtd_u64): Likewise. > (test_vclezd_s64): Likewise. > (test_vcltzd_s64): Likewise. > (test_vtst_s64): Likewise. > (test_vtst_u64): Likewise.
Re: [AArch64] Add combiner patterns for FAC instructions
OK /Marcus On 30 April 2013 16:11, James Greenhalgh wrote: > > Hi, > > This patch adds patterns to allow the combiner to generate > FAC instructions. > > Regression tested on aarch64-none-elf with no regressions. > > OK? > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/aarch64-simd.md (*aarch64_fac): New. > * config/aarch64/iterators.md (FAC_COMPARISONS): New.
Re: [AArch64] Rewrite vca Neon patterns in C.
OK /Marcus On 30 April 2013 16:13, James Greenhalgh wrote: > > Hi, > > This patch renames the vac neon intrinsics to vca > as required by the newest version of the neon intrinsics spec. > > While we are there, we also update all the vca* intrinsics to > a C implimentation. > > Regression tested on aarch64-none-elf with no regressions. > > OK? > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/arm_neon.h > (vac_f<32, 64>): Rename to... > (vca_f<32, 64>): ...this, reimpliment in C. > (vca_f<32, 64>): Reimpliment in C.
Re: [AArch64] Add testcases for FAC, FCM changes.
OK /Marcus On 30 April 2013 16:15, James Greenhalgh wrote: > > Hi, > > This patch adds two testcases for the scalar and vector versions > of the vca* intrinsics. > > New tests pass on aarch64-none-elf. > > OK? > > Thanks, > James > > --- > gcc/testsuite/ > > 2013-04-30 James Greenhalgh > > * gcc.target/aarch64/scalar-vca.c: New. > * gcc.target/aarch64/vect-vca.c: Likewise.
Re: [AArch64] Refactor vector max and min RTL and builtins.
OK /Marcus On 30 April 2013 16:19, James Greenhalgh wrote: > > Hi, > > This patch moves around the max/min infrastructure such that > we can more uniformly access the backend RTL patterns and such > that it uses the standard pattern names. > > We also fixup the bugs this introduces in arm_neon.h which expected > the older names. > > Regression tested on aarch64-none-elf with no issues. > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/aarch64-simd-builtins.def > (reduc_smax_): New. > (reduc_smin_): Likewise. > (reduc_umax_): Likewise. > (reduc_umin_): Likewise. > (reduc_smax_nan_): Likewise. > (reduc_smin_nan_): Likewise. > (fmax): Remove. > (fmin): Likewise. > (smax): Update for V2SF, V4SF and V2DF modes. > (smin): Likewise. > (smax_nan): New. > (smin_nan): Likewise. > * config/aarch64/aarch64-simd.md (3): Rename to... > (3): ...This, refactor. > (s3): New. > (3): Likewise. > (reduc__): Refactor. > (reduc__v4sf): Likewise. > (reduc__v2si): Likewise. > (aarch64_: Remove. > * config/aarch64/arm_neon.h (vmax_f<32,64>): Rewrite to use > new builtin names. > (vmin_f<32,64>): Likewise. > * config/iterators.md (unspec): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. > (FMAXMIN): New. > (su): Add mappings for smax, smin, umax, umin. > (maxmin): New. > (FMAXMINV): Add UNSPEC_FMAXNMV, UNSPEC_FMINNMV. > (FMAXMIN): Rename as... > (FMAXMIN_UNS): ...This. > (maxminv): Remove. > (fmaxminv): Likewise. > (fmaxmin): Likewise. > (maxmin_uns): New. > (maxmin_uns_op): Likewise.
Re: [AArch64] Fold max and min reduction builtins to tree.
OK /Marcus On 30 April 2013 16:21, James Greenhalgh wrote: > > Hi, > > This patch folds the signed versions of min and max reduction > builtins to tree form. We can't safely fold the unsigned > versions as they do not currently have the correct type. > > We must use TARGET_GIMPLE_FOLD_BUILTIN as REDUC_MIN_EXPR > is not a valid GENERIC code. > > Regression tested on aarch64-none-elf with no regressions. > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/aarch64-builtins > (aarch64_gimple_fold_builtin): Fold reduc__ builtins.
Re: [AArch64] Refactor reduc_plus patterns.
OK /Marcus On 30 April 2013 16:42, James Greenhalgh wrote: > > Hi, > > This patch refactors the reduc_plus RTL patterns in the > AArch64 back-end. We do this to provide a more uniform > interface for arm_neon.h builtins. Because of this we can rewrite > the intrinsics in arm_neon.h to use these standard pattern names, > and allow the signed varients to fold to tree where appropriate. > > Patch regression tested on aarch64-none-elf with no regressions. > > Thanks, > James > > --- > gcc/ > > 2013-04-30 James Greenhalgh > > * config/aarch64/aarch64-builtins.c > (aarch64_gimple_fold_builtin.c): Fold more modes for reduc_splus_. > * config/aarch64/aarch64-simd-builtins.def > (reduc_splus_): Add new modes. > (reduc_uplus_): New. > * config/aarch64/aarch64-simd.md (aarch64_addvv4sf): Remove. > (reduc_uplus_v4sf): Likewise. > (reduc_splus_v4sf): Likewise. > (aarch64_addv): Likewise. > (reduc_uplus_): Likewise. > (reduc_splus_): Likewise. > (aarch64_addvv2di): Likewise. > (reduc_uplus_v2di): Likewise. > (reduc_splus_v2di): Likewise. > (aarch64_addvv2si): Likewise. > (reduc_uplus_v2si): Likewise. > (reduc_splus_v2si): Likewise. > (reduc_plus_): New. > (reduc_plus_v2di): Likewise. > (reduc_plus_v2si): Likewise. > (reduc_plus_v4sf): Likewise. > (aarch64_addpv4sf): Likewise. > * config/aarch64/arm_neon.h > (vaddv_<8, 16, 32, 64): Rewrite using builtins. > * config/aarch64/iterators.md (unspec): Remove UNSPEC_ADDV, > add UNSPEC_SADDV, UNSPEC_UADDV. > (SUADDV): New. > (sur): Add UNSPEC_SADDV, UNSPEC_UADDV. > > gcc/testsuite/ > > 2013-04-30 James Greenhalgh > > * gcc.target/aarch64/vect-vaddv.c: New.
Re: [PATCH, fixincludes] Fix NULL on AIX
On Tue, Apr 30, 2013 at 1:09 PM, Bruce Korb wrote:
> By analogy, I'd prefer the EOF version there, too. But ultimately,
> it works and is not exactly illegible, so I have no serious objection
> to the fix. It would be nice if it were combinable, but doing so is
> tricky. I'm guessing that the fix on AIX is separated because the
> headers contain "__cplusplus" and that is used as an exclusion test
> for the "void_null" fix? Otherwise this:
>
> select= "^#[ \t]*define[ \t]+NULL[ \t]+("
> "\\(\\(void[ \t]*\\*\\)0\\)" "|" "\\(*0L*\\)*" ")";
>
> would allow void_null to work for you -- perhaps by using %1 somewhere
> in the replacement "c-fix-arg".
Yes, I created a separate fix because the void_null fix has additional
selection details that I did not want to change and possibly break
other platforms.
Thanks, David
[patch] Update email, status in MAINTAINERS
I have a new email address (and accompanying new job), and I hope to be working with GCC in the new job at least a bit, so it's time to update my email address in the MAINTAINERS file. Also, it has been some years since I have touched the Fortran front end, so I have demoted myself from Fortran reviewer to the "Write After Approval" section. Committed. Index: ChangeLog === --- ChangeLog (revision 198467) +++ ChangeLog (working copy) @@ -1,3 +1,8 @@ +2013-04-30 Brooks Moses + + * MAINTAINERS: Update my email; move myself from Fortran + reviewer to Write After Approval. + 2013-04-16 Andreas Schwab * configure.ac (aarch64-*-*): Don't disable java. Index: MAINTAINERS === --- MAINTAINERS (revision 198434) +++ MAINTAINERS (working copy) @@ -274,7 +274,6 @@ FortranDaniel Kraftd...@domob.eu FortranToon Moene t...@moene.org FortranMikael Morinmikael.mo...@sfr.fr -FortranBrooks Moses brooks.mo...@codesourcery.com FortranTobias Schlüter tobias.schlue...@physik.uni-muenchen.de FortranPaul Thomas pa...@gcc.gnu.org FortranJanus Weil ja...@gcc.gnu.org @@ -467,6 +466,7 @@ Alexander Monakov amona...@ispras.ru Catherine Moorec...@codesourcery.com James A. Morrison phyt...@gcc.gnu.org +Brooks Moses bmo...@google.com Dirk Mueller dmuel...@suse.de Phil Muldoon pmuld...@redhat.com Quentin Neill quentin.neill@gmail.com
Re: [C++ Patch/RFC] PR 57092
On 04/30/2013 11:59 AM, Paolo Carlini wrote: Currently, in some cases (see, eg, template/canon-type-9.C) we have that id is true and DECLTYPE_TYPE_EXPR (t) is a TEMPLATE_PARM_INDEX but the tsubst_copy_and_build call returns a TEMPLATE_PARM_INDEX again, not an ADDR_EXPR, not an expression Good point, this can happen for partial instantiations, when processing_template_decl is still true. We want to keep the DECLTYPE_TYPE around until the expression instantiates to something non-instantiation-dependent. Hmm. Maybe the right answer is to just add a default: case to finish_decltype_type and trust that it will be right. Jason
Re: [DWARF] Fix multiple register spanning location.
2013-04-26 Christian Bruel
* dwarf2out.c (multiple_reg_loc_descriptor): Use DBX_REGISTER_NUMBER
for spaning registers.
s/spaning/spanning/
Index: dwarf2out.c
===
--- dwarf2out.c (revision 198287)
+++ dwarf2out.c (working copy)
@@ -10656,7 +10656,8 @@ multiple_reg_loc_descriptor (rtx rtl, rtx regs,
{
dw_loc_descr_ref t;
- t = one_reg_loc_descriptor (REGNO (XVECEXP (regs, 0, i)),
+ reg = REGNO (XVECEXP (regs, 0, i));
+ t = one_reg_loc_descriptor (DBX_REGISTER_NUMBER (reg),
VAR_INIT_STATUS_INITIALIZED);
add_loc_descr (&loc_result, t);
size = GET_MODE_SIZE (GET_MODE (XVECEXP (regs, 0, 0)));
How about using dbx_reg_number (XVECEXP (regs, 0, i)) instead? The
bare use of DBX_REGISTER_NUMBER earlier in that function is protected
by a gcc_assert, but this one isn't.
-cary
Re: [C++ Patch/RFC] PR 57092
Hi,
On 04/30/2013 08:57 PM, Jason Merrill wrote:
On 04/30/2013 11:59 AM, Paolo Carlini wrote:
Currently, in some cases (see, eg, template/canon-type-9.C) we have that
id is true and DECLTYPE_TYPE_EXPR (t) is a TEMPLATE_PARM_INDEX but the
tsubst_copy_and_build call returns a TEMPLATE_PARM_INDEX again, not an
ADDR_EXPR, not an expression
Good point, this can happen for partial instantiations, when
processing_template_decl is still true. We want to keep the
DECLTYPE_TYPE around until the expression instantiates to something
non-instantiation-dependent.
I see...
Hmm. Maybe the right answer is to just add a default: case to
finish_decltype_type and trust that it will be right.
Ok. Then shall we do something like the below?
Thanks,
Paolo.
//
Index: cp/semantics.c
===
--- cp/semantics.c (revision 198469)
+++ cp/semantics.c (working copy)
@@ -5416,8 +5416,8 @@ finish_decltype_type (tree expr, bool id_expressio
break;
default:
- gcc_unreachable ();
- return error_mark_node;
+ type = TREE_TYPE (expr);
+ break;
}
}
else
Index: testsuite/g++.dg/cpp0x/decltype53.C
===
--- testsuite/g++.dg/cpp0x/decltype53.C (revision 0)
+++ testsuite/g++.dg/cpp0x/decltype53.C (working copy)
@@ -0,0 +1,11 @@
+// PR c++/57092
+// { dg-do compile { target c++11 } }
+
+template
+class B {
+ decltype(F) v;
+};
+
+void foo(int) {}
+
+B o;
[google] Add function name to function_patch_* sections (issue9025045)
Adding function name to the function_patch_* sections when -ffunction-sections
is provided. Helps in garbage collecting dead functions with the help of linker.
Tested:
Tested using 'make -k check-gcc RUNTESTFLAGS="i386.exp=patch*
--target_board=unix\{-m32,,-m64\}"'.
2013-04-30 Harshit Chopra
* gcc/config/i386/i386.c (ix86_output_function_nops_prologue_epilogue):
(ix86_elf_asm_named_section):
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index aa6ec82..7cb832b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11285,6 +11285,8 @@ ix86_output_function_nops_prologue_epilogue (FILE *file,
unsigned int section_flags = SECTION_RELRO;
char *section_name_comdat = NULL;
const char *decl_section_name = NULL;
+ const char *func_name = NULL;
+ char *section_name_function_sections = NULL;
size_t len;
gcc_assert (num_remaining_nops >= 0);
@@ -11336,12 +11338,24 @@ ix86_output_function_nops_prologue_epilogue (FILE
*file,
{
decl_section_name =
TREE_STRING_POINTER (DECL_SECTION_NAME (current_function_decl));
- len = strlen (decl_section_name) + strlen (section_name) + 1;
+ len = strlen (decl_section_name) + strlen (section_name) + 2;
section_name_comdat = (char *) alloca (len);
sprintf (section_name_comdat, "%s.%s", section_name, decl_section_name);
section_name = section_name_comdat;
section_flags |= SECTION_LINKONCE;
}
+ else if (flag_function_sections)
+{
+ func_name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+ if (func_name)
+{
+ len = strlen (func_name) + strlen (section_name) + 2;
+ section_name_function_sections = (char *) alloca (len);
+ sprintf (section_name_function_sections, "%s.%s", section_name,
+ func_name);
+ section_name = section_name_function_sections;
+}
+}
section = get_section (section_name, section_flags, current_function_decl);
switch_to_section (section);
/* Align the section to 8-byte boundary. */
@@ -11369,7 +11383,7 @@ ix86_elf_asm_named_section (const char *name, unsigned
int flags,
tree decl)
{
const char *section_name = name;
- if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
+ if (!flag_function_sections && HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
{
const int prologue_section_name_length =
sizeof(FUNCTION_PATCH_PROLOGUE_SECTION) - 1;
--
This patch is available for review at http://codereview.appspot.com/9025045
Re: [AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.
On Tue, 30 Apr 2013, James Greenhalgh wrote:
If the end goal of a VEC_COND_EXPR is to pick between
{-1, -1, -1, -1} and {0, 0, 0, 0}
then we do not need to do a bit select, this is just
a move of the generated mask to the result operand.
This patch checks for this case, and emits the
appropriate instructions. This can save us loading the
two constant masks and performing a bsl.
Some other targets (x86) optimize:
(a cmp b) ? x : 0
to
(a cmp b) & x
and then I think they rely on the generic simplify-rtx to optimize AND
with -1.
(it is also possible to replace (a cmp b) ? -1 : x with (a cmp b) | x)
Since several targets are in the same situation, it might make sense to
have those optimizations in the generic code with a way for targets to
advertise that their comparisons return 0/-1 the same size as the
arguments (using VECTOR_STORE_FLAG_VALUE?).
(to be clear: I am not at all arguing against this patch)
--
Marc Glisse
RE: [patch] cilkplus: Array notation for C patch
On 30 April 2013 00:55:16 "Joseph S. Myers" wrote:
> + if (flag_enable_cilkplus && contains_array_notation_expr (cond))
> +{
> + error_at (start_locus, "array notation expression cannot be used
in a "
> + "loop%'s condition");
> + return;
> +}
> + if (flag_enable_cilkplus && contains_array_notation_expr (incr) && 0)
> +{
> + error_at (start_locus, "array notation expression cannot be used
in a "
> + "loop's increment expression");
> + return;
> +}
Use %' in the second error here, as you did in the first.
Or just delete this second error, it is dead code ATM (&&0).
Sent with AquaMail for Android
http://www.aqua-mail.com
[patch, fortran, committed] Change 1**k to 1
Hello world,
the attached patch was committed after Tobias Burnus' OK
in PR 57073 and regression-testing.
Thomas
2013-04-30 Thomas Koenig
PR fortran/57071
* frontend-passes.c (optimize_power): Simplify
1**k to 1.
2013-04-30 Thomas Koenig
PR fortran/57071
* gfortran.dg/power_5.f90: New test.
Index: frontend-passes.c
===
--- frontend-passes.c (Revision 198369)
+++ frontend-passes.c (Arbeitskopie)
@@ -1148,6 +1148,24 @@ optimize_power (gfc_expr *e)
*e = *ishft;
return true;
}
+
+ else if (mpz_cmp_si (op1->value.integer, 1L) == 0)
+{
+ op2 = e->value.op.op2;
+ if (op2 == NULL)
+ return false;
+
+ gfc_free_expr (op1);
+ gfc_free_expr (op2);
+
+ e->expr_type = EXPR_CONSTANT;
+ e->value.op.op1 = NULL;
+ e->value.op.op2 = NULL;
+ mpz_init_set_si (e->value.integer, 1);
+ /* Typespec cand location are still OK. */
+ return true;
+}
+
return false;
}
! { dg-do run }
! { dg-options "-ffrontend-optimize -fdump-tree-original" }
! PR 57071 - Check that 1**k is transformed into 1
program main
implicit none
integer, parameter :: n = 3
integer(kind=8), dimension(-n:n) :: a
integer, dimension(-n:n) :: c, d
integer :: m
integer :: i, v
integer (kind=2) :: i2
v = 1
m = n
! Test in scalar expressions
do i=-n,n
if (v /= 1**i) call abort
end do
! Test in array constructors
a(-m:m) = [ (1**i, i= -m, m) ]
if (any(a .ne. v)) call abort
! Test in array expressions
c = [ ( i, i = -n , n ) ]
d = 1**c
if (any(d .ne. v)) call abort
! Test in different kind expressions
do i2=-n,n
if (v /= 1**i2) call abort
end do
end program main
! { dg-final { scan-tree-dump-times "_gfortran_pow_i4_i4" 0 "original" } }
! { dg-final { cleanup-tree-dump "original" } }
Re: [patch, fortran, committed] Change 1**k to 1
On Tue, Apr 30, 2013 at 11:47:46PM +0200, Thomas Koenig wrote: > + e->value.op.op1 = NULL; > + e->value.op.op2 = NULL; > + mpz_init_set_si (e->value.integer, 1); > + /* Typespec cand location are still OK. */ s/cand/and -- steve
[GOOGLE] Change function naming to use context function assembler name to replace function id
This patch changes to use context function name to replace function
id, which is not available in AutoFDO builds.
Bootstrapped and passed regression tests.
OK for google branches?
Thanks,
Dehao
Index: gcc/l-ipo.c
===
--- gcc/l-ipo.c (revision 198469)
+++ gcc/l-ipo.c (working copy)
@@ -1714,9 +1714,10 @@ create_unique_name (tree decl, unsigned module_id)
{
tree id, assemb_id;
char *assembler_name;
+ const char *context = NULL;
const char *name;
- struct function *context = NULL;
int seq = 0;
+ int len;
if (TREE_CODE (decl) == FUNCTION_DECL)
{
@@ -1740,7 +1741,8 @@ create_unique_name (tree decl, unsigned module_id)
else if (TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL)
{
id = DECL_NAME (decl);
- context = DECL_STRUCT_FUNCTION (DECL_CONTEXT (decl));
+ context = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (
+ DECL_CONTEXT (decl)));
}
else
/* file scope context */
@@ -1748,17 +1750,12 @@ create_unique_name (tree decl, unsigned module_id)
}
name = IDENTIFIER_POINTER (id);
+ len = strlen (name) + context ? strlen (context) : 0;
+ assembler_name = (char*) alloca (len + 30);
if (context)
-{
- char *n;
- unsigned fno = FUNC_DECL_FUNC_ID (context);
- n = (char *)alloca (strlen (name) + 15);
- sprintf (n, "%s.%u", name, fno);
- name = n;
-}
-
- assembler_name = (char*) alloca (strlen (name) + 30);
- sprintf (assembler_name, "%s.cmo.%u", name, module_id);
+sprintf (assembler_name, "%s.%s.cmo.%u", context, name, module_id);
+ else
+sprintf (assembler_name, "%s.cmo.%u", name, module_id);
seq = get_name_seq_num (assembler_name);
if (seq)
sprintf (assembler_name, "%s.%d", assembler_name, seq);
[Google 4.8 Dwarf] Backport .debug_str in .o files with -gsplit-dwarf from trunk (issue9052046)
The enclosed patch puts strings in the .debug_str section in the .o
file with -gsplit-dwarf. It is backported from from trunk (which, in turn,
was ported from google_4.7).
http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01355.html
The patch itself is no different from the one finally applied to trunk,
except several hunks have moved a few lines.
OK for gcc/google/gcc-4_8?
Sterling
Index: gcc/dwarf2out.c
===
--- gcc/dwarf2out.c (revision 198475)
+++ gcc/dwarf2out.c (working copy)
@@ -158,6 +158,7 @@ static GTY(()) section *debug_loc_section;
static GTY(()) section *debug_pubnames_section;
static GTY(()) section *debug_pubtypes_section;
static GTY(()) section *debug_str_section;
+static GTY(()) section *debug_str_dwo_section;
static GTY(()) section *debug_str_offsets_section;
static GTY(()) section *debug_ranges_section;
static GTY(()) section *debug_frame_section;
@@ -207,6 +208,28 @@ struct GTY(()) indirect_string_node {
static GTY ((param_is (struct indirect_string_node))) htab_t debug_str_hash;
+/* With split_debug_info, both the comp_dir and dwo_name go in the
+ main object file, rather than the dwo, similar to the force_direct
+ parameter elsewhere but with additional complications:
+
+ 1) The string is needed in both the main object file and the dwo.
+ That is, the comp_dir and dwo_name will appear in both places.
+
+ 2) Strings can use three forms: DW_FORM_string, DW_FORM_strp or
+ DW_FORM_GNU_str_index.
+
+ 3) GCC chooses the form to use late, depending on the size and
+ reference count.
+
+ Rather than forcing the all debug string handling functions and
+ callers to deal with these complications, simply use a separate,
+ special-cased string table for any attribute that should go in the
+ main object file. This limits the complexity to just the places
+ that need it. */
+
+static GTY ((param_is (struct indirect_string_node)))
+ htab_t skeleton_debug_str_hash;
+
static GTY(()) int dw2_string_counter;
/* True if the compilation unit places functions in more than one section. */
@@ -3198,6 +3221,8 @@ static bool generic_type_p (tree);
static void schedule_generic_params_dies_gen (tree t);
static void gen_scheduled_generic_parms_dies (void);
+static const char *comp_dir_string (void);
+
/* enum for tracking thread-local variables whose address is really an offset
relative to the TLS pointer, which will need link-time relocation, but will
not need relocation by the DWARF consumer. */
@@ -3311,11 +3336,11 @@ new_addr_loc_descr (rtx addr, enum dtprel_bool dtp
(!dwarf_split_debug_info \
? (DEBUG_NORM_STR_OFFSETS_SECTION) : (DEBUG_DWO_STR_OFFSETS_SECTION))
#endif
-#define DEBUG_DWO_STR_SECTION ".debug_str.dwo"
-#define DEBUG_NORM_STR_SECTION ".debug_str"
+#ifndef DEBUG_STR_DWO_SECTION
+#define DEBUG_STR_DWO_SECTION ".debug_str.dwo"
+#endif
#ifndef DEBUG_STR_SECTION
-#define DEBUG_STR_SECTION \
- (!dwarf_split_debug_info ? (DEBUG_NORM_STR_SECTION) :
(DEBUG_DWO_STR_SECTION))
+#define DEBUG_STR_SECTION ".debug_str"
#endif
#ifndef DEBUG_RANGES_SECTION
#define DEBUG_RANGES_SECTION ".debug_ranges"
@@ -3327,17 +3352,18 @@ new_addr_loc_descr (rtx addr, enum dtprel_bool dtp
#endif
/* Section flags for .debug_macinfo/.debug_macro section. */
-#define DEBUG_MACRO_SECTION_FLAGS \
+#define DEBUG_MACRO_SECTION_FLAGS \
(dwarf_split_debug_info ? SECTION_DEBUG | SECTION_EXCLUDE : SECTION_DEBUG)
/* Section flags for .debug_str section. */
-#define DEBUG_STR_SECTION_FLAGS \
- (dwarf_split_debug_info \
- ? SECTION_DEBUG | SECTION_EXCLUDE \
- : (HAVE_GAS_SHF_MERGE && flag_merge_debug_strings \
- ? SECTION_DEBUG | SECTION_MERGE | SECTION_STRINGS | 1\
- : SECTION_DEBUG))
+#define DEBUG_STR_SECTION_FLAGS \
+ (HAVE_GAS_SHF_MERGE && flag_merge_debug_strings \
+ ? SECTION_DEBUG | SECTION_MERGE | SECTION_STRINGS | 1\
+ : SECTION_DEBUG)
+/* Section flags for .debug_str.dwo section. */
+#define DEBUG_STR_DWO_SECTION_FLAGS (SECTION_DEBUG | SECTION_EXCLUDE)
+
/* Labels we insert at beginning sections we can reference instead of
the section names themselves. */
@@ -3820,19 +3846,15 @@ debug_str_eq (const void *x1, const void *x2)
(const char *)x2) == 0;
}
-/* Add STR to the indirect string hash table. */
+/* Add STR to the given string hash table. */
static struct indirect_string_node *
-find_AT_string (const char *str)
+find_AT_string_in_table (const char *str, htab_t table)
{
struct indirect_string_node *node;
void **slot;
- if (! debug_str_hash)
-debug_str_hash = htab_create_ggc (10, debug_str_do_hash,
- debug_str_eq, NULL);
-
- slot = htab_find_slot_with_hash (debug_str_hash, str,
+ slot = hta
Re: [google] Add function name to function_patch_* sections (issue9025045)
ok.
David
On Tue, Apr 30, 2013 at 1:34 PM, Harshit Chopra wrote:
> Adding function name to the function_patch_* sections when
> -ffunction-sections is provided. Helps in garbage collecting dead functions
> with the help of linker.
>
> Tested:
> Tested using 'make -k check-gcc RUNTESTFLAGS="i386.exp=patch*
> --target_board=unix\{-m32,,-m64\}"'.
>
> 2013-04-30 Harshit Chopra
>
> * gcc/config/i386/i386.c
> (ix86_output_function_nops_prologue_epilogue):
> (ix86_elf_asm_named_section):
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index aa6ec82..7cb832b 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -11285,6 +11285,8 @@ ix86_output_function_nops_prologue_epilogue (FILE
> *file,
>unsigned int section_flags = SECTION_RELRO;
>char *section_name_comdat = NULL;
>const char *decl_section_name = NULL;
> + const char *func_name = NULL;
> + char *section_name_function_sections = NULL;
>size_t len;
>
>gcc_assert (num_remaining_nops >= 0);
> @@ -11336,12 +11338,24 @@ ix86_output_function_nops_prologue_epilogue (FILE
> *file,
> {
>decl_section_name =
>TREE_STRING_POINTER (DECL_SECTION_NAME (current_function_decl));
> - len = strlen (decl_section_name) + strlen (section_name) + 1;
> + len = strlen (decl_section_name) + strlen (section_name) + 2;
>section_name_comdat = (char *) alloca (len);
>sprintf (section_name_comdat, "%s.%s", section_name,
> decl_section_name);
>section_name = section_name_comdat;
>section_flags |= SECTION_LINKONCE;
> }
> + else if (flag_function_sections)
> +{
> + func_name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
> + if (func_name)
> +{
> + len = strlen (func_name) + strlen (section_name) + 2;
> + section_name_function_sections = (char *) alloca (len);
> + sprintf (section_name_function_sections, "%s.%s", section_name,
> + func_name);
> + section_name = section_name_function_sections;
> +}
> +}
>section = get_section (section_name, section_flags, current_function_decl);
>switch_to_section (section);
>/* Align the section to 8-byte boundary. */
> @@ -11369,7 +11383,7 @@ ix86_elf_asm_named_section (const char *name,
> unsigned int flags,
> tree decl)
> {
>const char *section_name = name;
> - if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE)
> + if (!flag_function_sections && HAVE_COMDAT_GROUP && flags &
> SECTION_LINKONCE)
> {
>const int prologue_section_name_length =
>sizeof(FUNCTION_PATCH_PROLOGUE_SECTION) - 1;
>
> --
> This patch is available for review at http://codereview.appspot.com/9025045
Re: [Google 4.8 Dwarf] Backport .debug_str in .o files with -gsplit-dwarf from trunk (issue9052046)
> The enclosed patch puts strings in the .debug_str section in the .o > file with -gsplit-dwarf. It is backported from from trunk (which, in turn, > was ported from google_4.7). > > http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01355.html > > The patch itself is no different from the one finally applied to trunk, > except several hunks have moved a few lines. > > OK for gcc/google/gcc-4_8? OK. -cary
Re: [Google 4.8 Dwarf] Backport .debug_str in .o files with -gsplit-dwarf from trunk (issue9052046)
On Tue, Apr 30, 2013 at 4:47 PM, Cary Coutant wrote: >> The enclosed patch puts strings in the .debug_str section in the .o >> file with -gsplit-dwarf. It is backported from from trunk (which, in turn, >> was ported from google_4.7). >> >> http://gcc.gnu.org/ml/gcc-patches/2013-04/msg01355.html >> >> The patch itself is no different from the one finally applied to trunk, >> except several hunks have moved a few lines. >> >> OK for gcc/google/gcc-4_8? > > OK. > > -cary Thanks. Committed as posted.
Re: [C++ Patch/RFC] PR 57092
On 04/30/2013 04:49 PM, Paolo Carlini wrote: Ok. Then shall we do something like the below? Yeah, just add a comment explaining that it's there to handle instantiated template non-type arguments. Jason
RFC: PATCH to avoid linking multiple front ends at once with parallel make
Since GNU Make doesn't support anything like the .MUTEX directive (http://savannah.gnu.org/bugs/?func=detailitem&item_id=17873), and accidentally doing "make -j8 -l4" makes my laptop useless for several minutes while it tries to link all the front ends at once, I decided to kludge a workaround. This hack uses mkdir as a locking mechanism, as it fails if the directory already exists. Each front-end rule first tries to get the lock, and spins if the lock isn't available. Currently I'm enabling the locking by default on build hosts with less than 8GB of memory. Releasing the lock is not reliable; if the user interrupts the link with ^C, the lock will remain. So I adjusted 'make all' to remove the lock early on, though that only works for the typical case, and users that do something like 'make cc1plus' could still run into trouble. Thoughts? Is this too horrible a hack, or does it seem like something we might want? Maybe I should fix Make instead. Jason commit 47980ab5ea7f1037b8b7cce9b8abfe1c0a75c032 Author: Jason Merrill Date: Thu Apr 25 17:54:17 2013 -0400 * Makefile.in (link-mutex, remove-link-mutex): New targets. (native, mostlyclean): Remove link mutex. * configure.ac: Handle --enable-link-mutex. * */Make-lang.in: Use link mutex. diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 903125e..3934e16 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -1737,8 +1737,8 @@ start.encap: native xgcc$(exeext) cpp$(exeext) specs \ rest.encap: lang.rest.encap # This is what is made with the host's compiler # whether making a cross compiler or not. -native: config.status auto-host.h build-@POSUB@ $(LANGUAGES) \ - $(EXTRA_PROGRAMS) $(COLLECT2) lto-wrapper$(exeext) \ +native: remove-link-mutex config.status auto-host.h build-@POSUB@ \ + $(LANGUAGES) $(EXTRA_PROGRAMS) $(COLLECT2) lto-wrapper$(exeext) \ gcc-ar$(exeext) gcc-nm$(exeext) gcc-ranlib$(exeext) ifeq ($(enable_plugin),yes) @@ -4529,6 +4529,8 @@ mostlyclean: lang.mostlyclean -rm -f gtype.state # Delete genchecksum outputs -rm -f *-checksum.c +# Delete front-end linking mutex directory + -rm -rf link-mutex # Delete all files made by compilation # that don't exist in the distribution. @@ -5335,3 +5337,14 @@ po/gcc.pot: force $(MAKE) srcextra AWK=$(AWK) $(SHELL) $(srcdir)/po/exgettext \ $(XGETTEXT) gcc $(srcdir) + +do_link_mutex = @DO_LINK_MUTEX@ +.PHONY: link-mutex +link-mutex: +ifeq ($(do_link_mutex),true) + while ! mkdir link-mutex 2>/dev/null; do sleep 1; done +endif + +.PHONY: remove-link-mutex +remove-link-mutex: + -rm -rf link-mutex diff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-interface/Make-lang.in index ef12b4b..7d88961 100644 --- a/gcc/ada/gcc-interface/Make-lang.in +++ b/gcc/ada/gcc-interface/Make-lang.in @@ -562,7 +562,10 @@ TARGET_ADA_SRCS = # Since the RTL should be built with the latest compiler, remove the # stamp target in the parent directory whenever gnat1 is rebuilt gnat1$(exeext): $(TARGET_ADA_SRCS) $(GNAT1_OBJS) $(ADA_BACKEND) libcommon-target.a $(LIBDEPS) - +$(GCC_LINK) -o $@ $(GNAT1_OBJS) $(ADA_BACKEND) libcommon-target.a $(LIBS) $(SYSLIBS) $(BACKENDLIBS) $(CFLAGS) + $(MAKE) link-mutex + +$(GCC_LINK) -o $@ $(GNAT1_OBJS) $(ADA_BACKEND) \ + libcommon-target.a $(LIBS) $(SYSLIBS) $(BACKENDLIBS) $(CFLAGS); \ + $(MAKE) remove-link-mutex $(RM) stamp-gnatlib2-rts stamp-tools gnatbind$(exeext): ada/b_gnatb.o $(CONFIG_H) $(GNATBIND_OBJS) ggc-none.o libcommon-target.a $(LIBDEPS) diff --git a/gcc/c/Make-lang.in b/gcc/c/Make-lang.in index 8310e0a..cf61d74 100644 --- a/gcc/c/Make-lang.in +++ b/gcc/c/Make-lang.in @@ -75,8 +75,10 @@ cc1-checksum.c : build/genchecksum$(build_exeext) checksum-options \ cc1-checksum.o : cc1-checksum.c $(CONFIG_H) $(SYSTEM_H) cc1$(exeext): $(C_OBJS) cc1-checksum.o $(BACKEND) $(LIBDEPS) + $(MAKE) link-mutex +$(LINKER) $(ALL_LINKERFLAGS) $(LDFLAGS) -o $@ $(C_OBJS) \ - cc1-checksum.o $(BACKEND) $(LIBS) $(BACKENDLIBS) + cc1-checksum.o $(BACKEND) $(LIBS) $(BACKENDLIBS); \ + $(MAKE) remove-link-mutex # # Build hooks: diff --git a/gcc/configure b/gcc/configure index fd4a0eb..ab56d21 100755 --- a/gcc/configure +++ b/gcc/configure @@ -670,6 +670,7 @@ subdirs dollar gcc_tooldir enable_lto +DO_LINK_MUTEX MAINT zlibinc zlibdir @@ -916,6 +917,7 @@ with_long_double_128 with_gc with_system_zlib enable_maintainer_mode +enable_link_mutex enable_version_specific_runtime_libs enable_plugin enable_libquadmath_support @@ -1627,6 +1629,8 @@ Optional Features: --enable-maintainer-mode enable make rules and dependencies not useful (and sometimes confusing) to the casual installer + --enable-link-mutex avoid linking multiple front-ends at once to avoid + thrashing on the build machine --enable-version-specific-runtime-libs specify that runtime libraries should be installed in a
