OK /Marcus
On 30 April 2013 16:08, James Greenhalgh <james.greenha...@arm.com> wrote: > > Hi, > > gcc.target/aarch64/scalar_intrinsics.c uses the vcled_s64 style > intrinsics. As these now just map to a C operation, we need to first > ensure that the arguments to these functions make their way to the > SIMD register set. > > For the >= 0 and < 0 opertaions idiom recognition will convert > them to shifts, so we also need to mop up the expectations on numbers > of shifts and generation of cmge d0, d0, #0. > > Tested to ensure test still passes. > > Thanks, > James > > --- > gcc/testsuite/ > > 2013-04-30 James Greenhalgh <james.greenha...@arm.com> > > * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. > (test_vceqd_s64): Force arguments to SIMD registers. > (test_vceqzd_s64): Likewise. > (test_vcged_s64): Likewise. > (test_vcled_s64): Likewise. > (test_vcgezd_s64): Likewise. > (test_vcged_u64): Likewise. > (test_vcgtd_s64): Likewise. > (test_vcltd_s64): Likewise. > (test_vcgtzd_s64): Likewise. > (test_vcgtd_u64): Likewise. > (test_vclezd_s64): Likewise. > (test_vcltzd_s64): Likewise. > (test_vtst_s64): Likewise. > (test_vtst_u64): Likewise.
