Hi,
This patch adds patterns to allow the combiner to generate
FAC instructions.
Regression tested on aarch64-none-elf with no regressions.
OK?
Thanks,
James
---
gcc/
2013-04-30 James Greenhalgh <james.greenha...@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_fac<optab><mode>): New.
* config/aarch64/iterators.md (FAC_COMPARISONS): New.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index dfe4acb..21c2a68 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3400,6 +3400,23 @@
(set_attr "simd_mode" "<MODE>")]
)
+;; fac(ge|gt)
+;; Note we can also handle what would be fac(le|lt) by
+;; generating fac(ge|gt).
+
+(define_insn "*aarch64_fac<optab><mode>"
+ [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
+ (neg:<V_cmp_result>
+ (FAC_COMPARISONS:<V_cmp_result>
+ (abs:VALLF (match_operand:VALLF 1 "register_operand" "w"))
+ (abs:VALLF (match_operand:VALLF 2 "register_operand" "w"))
+ )))]
+ "TARGET_SIMD"
+ "fac<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
+ [(set_attr "simd_type" "simd_fcmp")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
;; addp
(define_insn "aarch64_addp<mode>"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 0b9f9e8..00e315d 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -553,6 +553,9 @@
;; Unsigned comparison operators.
(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
+;; Unsigned comparison operators.
+(define_code_iterator FAC_COMPARISONS [lt le ge gt])
+
;; -------------------------------------------------------------------
;; Code Attributes
;; -------------------------------------------------------------------
