from:"Zakk Chen via Phabricator via cfe\-commits"

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

2022-09-06 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D71387#3755056 , @lewis-revill 
wrote:

> I believe this patch is still relevant/necessary when using LTO for RISCV, so 
> can I ask if @khchen is able to update it to rebase/address the feedback? If 
> not, are there are any objections to me commandeering this revision to get it 
> landed?

Yes, you could command this revision to enable LTO, thank you!!


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[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

2022-09-06 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

> Possible solution/results:
>
> 1. All functions in `a.o` and `b.o` using same target features during the 
> first build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and 
> `-march` option given in LTO CodeGen stage is ignored, it only used for ELF 
> attribute use (this revision).
> 2. All functions in `a.o` and `b.o` using same target features during the 
> first build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and 
> deduced arch info from those `.o` for ELF attribute use (D106347 
> ), `-march`
> 3. All functions in `a.o` and `b.o` re-compile with `-march=rv64gc_zba` and 
> ELF attribute use `rv64gc_zba`.
>
> Option 1: Require user use right `-march` option during LTO stage, and might 
> fill wrong/unexpected ELF attribute if give wrong `-march` or not even not 
> given in LTO stage.
> Option 2: Should be more ideal, but D106347 
>  seems no progress for a while.
> Option 3: This option will break IFUNC usage.

This patch (Option 1) is look good to me, but maybe we need to report a warning 
in linking stage if possible.
I think users may not easy to specific the right -march string when they're 
using external libraries.
We had discussed that before in here  
and here , it's why I proposed Option 
2  which encodes a module scope arch features 
in IR. IIRC, it's similar to what gcc did.


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-06-30 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM. Other than that last comments.




Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:77
+  // Create compressed hsignature table from SemaRecords.
+  void init(const std::vector &SemaRecords);
+

please use ArrayRef



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:110
+  void createRVVIntrinsics(std::vector> &Out,
+   std::vector *SemaRecords);
+  /// Create all intrinsics record and SemaSignatureTable from SemaRecords.

maybe SemaRecords could have default argument as nullptr.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:114
+SemaSignatureTable &SST,
+const std::vector &SemaRecords);
+

please use ArrayRef



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:254
+  if (Signature.empty())
+return 0;
+

Does it mean empty Signature always at 0?
If yes,  maybe we could check the table from Index = 1 in below loop?


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-06-30 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

@craig.topper @rogfer01 - do you have other comments?


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-05 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");

I feel this logic is not clear for reader, maybe you should add comment to say 
why the return type -1 are load intrinsics?


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[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

2022-03-24 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: s, VincentWu, luke957, StephenFan, vkmr, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

This reverts commit 10fd2822b77e12215b4ea82fc6d0a052961eb9d9 
.

I have a better implementation for those operations without the
additional policy operand.
masked compare and vmsbf/vmsif/vmsof are always tail agnostic so we could
assume undef maskedoff is mask agnostic.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

2022-03-29 Thread Zakk Chen via Phabricator via cfe-commits

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10b2760da0fd: Revert "[RISCV] Add policy operand for 
masked compare and vmsbf/vmsif/vmsof IR" (authored by khchen).
Herald added a subscriber: sunshaoce.

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

2022-07-26 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbc4eef509b21: [RISCV][Clang] Refactor and rename rvv 
intrinsic related stuff. (NFC) (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126740?vs=433256&id=447630#toc

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -479,12 +479,12 @@
 bool HasMasked = R->getValueAsBit("HasMasked");
 bool HasMaskedOffOperand = R->getValueAsBit("HasMaskedOffOperand");
 bool HasVL = R->getValueAsBit("HasVL");
-Record *MaskedPolicyRecord = R->getValueAsDef("MaskedPolicy");
-PolicyScheme MaskedPolicy =
-static_cast(MaskedPolicyRecord->getValueAsInt("Value"));
-Record *UnMaskedPolicyRecord = R->getValueAsDef("UnMaskedPolicy");
-PolicyScheme UnMaskedPolicy =
-static_cast(UnMaskedPolicyRecord->getValueAsInt("Value"));
+Record *MPSRecord = R->getValueAsDef("MaskedPolicyScheme");
+auto MaskedPolicyScheme =
+static_cast(MPSRecord->getValueAsInt("Value"));
+Record *UMPSRecord = R->getValueAsDef("UnMaskedPolicyScheme");
+auto UnMaskedPolicyScheme =
+static_cast(UMPSRecord->getValueAsInt("Value"));
 bool HasUnMaskedOverloaded = R->getValueAsBit("HasUnMaskedOverloaded");
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
 bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
@@ -500,50 +500,19 @@
 
 // Parse prototype and create a list of primitive type with transformers
 // (operand) in Prototype. Prototype[0] is output operand.
-SmallVector Prototype = parsePrototypes(Prototypes);
+SmallVector BasicPrototype =
+parsePrototypes(Prototypes);
 
 SmallVector SuffixDesc = parsePrototypes(SuffixProto);
 SmallVector OverloadedSuffixDesc =
 parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-SmallVector MaskedPrototype = Prototype;
-if (HasMasked) {
-  // If HasMaskedOffOperand, insert result type as first input operand.
-  if (HasMaskedOffOperand) {
-if (NF == 1) {
-  MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
-} else {
-  // Convert
-  // (void, op0 address, op1 address, ...)
-  // to
-  // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-  PrototypeDescriptor MaskoffType = Prototype[1];
-  MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
-  for (unsigned I = 0; I < NF; ++I)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   MaskoffType);
-}
-  }
-  if (HasMaskedOffOperand && NF > 1) {
-// Convert
-// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-// to
-// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
-// ...)
-MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
-   PrototypeDescriptor::Mask);
-  } else {
-// If HasMasked, insert PrototypeDescriptor:Mask as first input operand.
-MaskedPrototype.insert(MaskedPrototype.begin() + 1,
-   PrototypeDescriptor::Mask);
-  }
-}
-// If HasVL, append PrototypeDescriptor:VL to last operand
-if (HasVL) {
-  Prototype.push_back(PrototypeDescriptor::VL);
-  MaskedPrototype.push_back(PrototypeDescriptor::VL);
-}
+auto Prototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/false, /*HasMaskedOffOperand=*/false,
+HasVL, NF);
+auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
+BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF);
 
 // Create Intrinsics for each type and LMUL.
 for (char I : TypeRange) {
@@ -562,7 +531,7 @@
 Out.push_back(std::make_unique(
 Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
 /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
-UnMaskedPolicy, HasUnMaskedOverloaded, HasBuiltinAlias,
+UnMaskedPolicyScheme, HasUnMaskedOverloaded, HasBuiltinAlias,
 ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF));
 if (HasMasked) {
   // Create a masked intrinsic
@@ -571,7 +540,7 @@
   Out.push_back(std::make_unique(
   Name, SuffixStr, OverloadedName, Overloade

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

2022-07-26 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG93f8657c743b: [RISCV][Clang] Refactor RISCVVEmitter. (NFC) 
(authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126741?vs=433257&id=447634#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D126741

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -50,9 +50,6 @@
   // Prototype for this intrinsic.
   SmallVector Prototype;
 
-  // Prototype for masked intrinsic.
-  SmallVector MaskedPrototype;
-
   // Suffix of intrinsic name.
   SmallVector Suffix;
 
@@ -61,6 +58,10 @@
 
   // Number of field, large than 1 if it's segment load/store.
   unsigned NF;
+
+  bool HasMasked :1;
+  bool HasVL :1;
+  bool HasMaskedOffOperand :1;
 };
 
 // Compressed function signature table.
@@ -241,7 +242,6 @@
 
   llvm::for_each(SemaRecords, [&](const SemaRecord &SR) {
 InsertToSignatureSet(SR.Prototype);
-InsertToSignatureSet(SR.MaskedPrototype);
 InsertToSignatureSet(SR.Suffix);
 InsertToSignatureSet(SR.OverloadedSuffix);
   });
@@ -583,12 +583,10 @@
 }
 
 SR.NF = NF;
-
-SR.Prototype = std::move(Prototype);
-
-if (HasMasked)
-  SR.MaskedPrototype = std::move(MaskedPrototype);
-
+SR.HasMasked = HasMasked;
+SR.HasVL = HasVL;
+SR.HasMaskedOffOperand = HasMaskedOffOperand;
+SR.Prototype = std::move(BasicPrototype);
 SR.Suffix = parsePrototypes(SuffixProto);
 SR.OverloadedSuffix = parsePrototypes(OverloadedSuffixProto);
 
@@ -616,22 +614,21 @@
 R.Name = SR.Name.c_str();
 R.OverloadedName = SR.OverloadedName.c_str();
 R.PrototypeIndex = SST.getIndex(SR.Prototype);
-R.MaskedPrototypeIndex = SST.getIndex(SR.MaskedPrototype);
 R.SuffixIndex = SST.getIndex(SR.Suffix);
 R.OverloadedSuffixIndex = SST.getIndex(SR.OverloadedSuffix);
 R.PrototypeLength = SR.Prototype.size();
-R.MaskedPrototypeLength = SR.MaskedPrototype.size();
 R.SuffixLength = SR.Suffix.size();
 R.OverloadedSuffixSize = SR.OverloadedSuffix.size();
 R.RequiredExtensions = SR.RequiredExtensions;
 R.TypeRangeMask = SR.TypeRangeMask;
 R.Log2LMULMask = SR.Log2LMULMask;
 R.NF = SR.NF;
+R.HasMasked = SR.HasMasked;
+R.HasVL = SR.HasVL;
+R.HasMaskedOffOperand = SR.HasMaskedOffOperand;
 
 assert(R.PrototypeIndex !=
static_cast(SemaSignatureTable::INVALID_INDEX));
-assert(R.MaskedPrototypeIndex !=
-   static_cast(SemaSignatureTable::INVALID_INDEX));
 assert(R.SuffixIndex !=
static_cast(SemaSignatureTable::INVALID_INDEX));
 assert(R.OverloadedSuffixIndex !=
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -981,17 +981,18 @@
   else
 OS << "\"" << Record.OverloadedName << "\",";
   OS << Record.PrototypeIndex << ",";
-  OS << Record.MaskedPrototypeIndex << ",";
   OS << Record.SuffixIndex << ",";
   OS << Record.OverloadedSuffixIndex << ",";
   OS << (int)Record.PrototypeLength << ",";
-  OS << (int)Record.MaskedPrototypeLength << ",";
   OS << (int)Record.SuffixLength << ",";
   OS << (int)Record.OverloadedSuffixSize << ",";
   OS << (int)Record.RequiredExtensions << ",";
   OS << (int)Record.TypeRangeMask << ",";
   OS << (int)Record.Log2LMULMask << ",";
   OS << (int)Record.NF << ",";
+  OS << (int)Record.HasMasked << ",";
+  OS << (int)Record.HasVL << ",";
+  OS << (int)Record.HasMaskedOffOperand << ",";
   OS << "},\n";
   return OS;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -178,14 +178,23 @@
   for (auto &Record : RVVIntrinsicRecords) {
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
-ArrayRef ProtoSeq =
+ArrayRef BasicProtoSeq =
 ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength);
-ArrayRef ProtoMaskSeq = ProtoSeq2ArrayRef(
-Record.MaskedPrototypeIndex, Record.MaskedPrototypeLength);
 ArrayRef SuffixProto =
 ProtoSeq2ArrayRef(Record.SuffixIndex, Record.SuffixLength);
 ArrayRef OverloadedSuffixProto = ProtoSeq2ArrayRef(
 Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);
+
+llvm::SmallVector ProtoSeq =
+RVVIntrinsic::computeBuiltinTypes(BasicProtoS

[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8e51917b39cd: [RISCV][Clang] Add tests for all supported 
policy functions. (NFC) (authored by khchen).

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Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intri

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D126745#3678776 , @nlopes wrote:

> While at it, could you switch those UndefValue with PoisonValue if possible?  
> Thank you!

I'm not sure UndefValue will work because the backend would only check 
isUndef() to generate correct code...


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D126745#3691544 , @craig.topper 
wrote:

> In D126745#3691528 , @khchen wrote:
>
>> In D126745#3678776 , @nlopes wrote:
>>
>>> While at it, could you switch those UndefValue with PoisonValue if 
>>> possible?  Thank you!
>>
>> I'm not sure UndefValue will work because the backend would only check 
>> isUndef() to generate correct code...
>
> PoisonValue and UndefValue are both turned into undef in SelectionDAG today.

thanks @craig.topper, I will switch UndefValue with PoisonValue.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-01 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

oops.. all tests need to updated and include all intrinsic IR tests...
Is there any benefit to switch UndefValue to PoisonValue?
maybe those changed should be in other follow-up patches?


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

@nlopes we will update all undef to poison in follow up patches.


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7eddeb9e99f3: [RISCV][Clang] Support policy functions for 
vmerge, vfmerge and (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126745?vs=433263&id=449336#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126745/new/

https://reviews.llvm.org/D126745

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -981,7 +981,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1f16.nxv1f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vmerge_vvm_f16mf4 (vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
+vfloat16mf4_t test_vmerge_vvm_f16mf4(vbool64_t mask, vfloat16mf4_t op1, vfloat16mf4_t op2, size_t vl) {
   return vmerge_vvm_f16mf4(mask, op1, op2, vl);
 }
 
@@ -990,7 +990,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv2f16.nxv2f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vmerge_vvm_f16mf2 (vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
+vfloat16mf2_t test_vmerge_vvm_f16mf2(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
   return vmerge_vvm_f16mf2(mask, op1, op2, vl);
 }
 
@@ -999,7 +999,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv4f16.nxv4f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vmerge_vvm_f16m1 (vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+vfloat16m1_t test_vmerge_vvm_f16m1(vbool16_t mask, vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
   return vmerge_vvm_f16m1(mask, op1, op2, vl);
 }
 
@@ -1008,7 +1008,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv8f16.nxv8f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vmerge_vvm_f16m2 (vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
+vfloat16m2_t test_vmerge_vvm_f16m2(vbool8_t mask, vfloat16m2_t op1, vfloat16m2_t op2, size_t vl) {
   return vmerge_vvm_f16m2(mask, op1, op2, vl);
 }
 
@@ -1017,7 +1017,7 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv16f16.nxv16f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vmerge_vvm_f16m4 (vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
+vfloat16m4_t test_vmerge_vvm_f16m4(vbool4_t mask, vfloat16m4_t op1, vfloat16m4_t op2, size_t vl) {
   return vmerge_vvm_f16m4(mask, op1, op2, vl);
 }
 
@@ -1026,6 +1026,96 @@
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv32f16.nxv32f16.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vmerge_vvm_f16m8 (vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
+vfloat16m8_t test_vmerge_vvm_f16m8(vbool2_t mask, vfloat16m8_t op1, vfloat16m8_t op2, size_t vl) {
   return vmerge_vvm_f16m8(mask, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmerge_vvm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vvm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmerge_vvm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge_vxm_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmerge.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint32mf2_t test_vmerge_vxm_i32mf2_tu(vbool64_t mask, vint32mf2_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmerge_vxm_i32mf2_tu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmerge

[PATCH] D126746: [RISCV][Clang] Support policy functions for Vector Comparison Instructions.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9caf2cc05c02: [RISCV][Clang] Support policy functions for 
Vector Comparison (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126746/new/

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
@@ -1699,3 +1699,75 @@
   vuint64m8_t op1, uint64_t op2, size_t vl) {
   return vmsne_vx_u64m8_b8_m(mask, maskedoff, op1, op2, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_i32mf2_b64_ma (vbool64_t mask, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmsne_vx_i32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( undef,  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
+  return vmsne_vv_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_u32mf2_b64_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( undef,  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_u32mf2_b64_ma (vbool64_t mask, vuint32mf2_t op1, uint32_t op2, size_t vl) {
+  return vmsne_vx_u32mf2_b64_ma(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.nxv1i32.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vv_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
+  return vmsne_vv_i32mf2_b64_mu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vx_i32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsne.mask.nxv1i32.i32.i64( [[MERGE:%.*]],  [[OP1:%.*]], i32 [[OP2:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool64_t test_vmsne_vx_i32mf2_b64_mu (vbool64_t mask, vbool64_t merge, vint32mf2_t op1, int32_t op2, size_t vl) {
+  return vmsne_vx_i32mf2_b64_mu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsne_vv_u32mf2_b64_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdffdca85ec2d: [RISCV][Clang] Support policy functions for 
Vector Reduction (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126748?vs=433267&id=449338#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126748/new/

https://reviews.llvm.org/D126748

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -194,6 +194,10 @@
   if (RVVI->hasMaskedOffOperand() &&
   RVVI->getDefaultPolicy() == Policy::TAMA)
 OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
+  // Masked reduction cases.
+  if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
+  RVVI->getDefaultPolicy() == Policy::TAMA)
+OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
 } else {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
 }
@@ -201,7 +205,8 @@
 if (RVVI->hasPolicyOperand())
   OS << "  Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
 "DefaultPolicy));\n";
-else if (RVVI->hasPassthruOperand() && RVVI->getDefaultPolicy() == Policy::TA)
+else if (RVVI->hasPassthruOperand() &&
+ RVVI->getDefaultPolicy() == Policy::TA)
   OS << "  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
   }
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
@@ -759,3 +759,75 @@
 vuint64m1_t scalar, size_t vl) {
   return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64( [[MERGE:%.*]],  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tu(vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
+  return vwredsumu_vs_u32mf2_u64m1_tu(merge, vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64( undef,  [[VECTOR:%.*]],  [[SCALAR:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vint64m1_t test_vwredsum_vs_i32mf2_i64m1_ta(vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
+  return vwredsum_vs_i32mf2_i64m1_ta(vector, scalar, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vwredsumu.nxv1i64.nxv

[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbb99d4b11d84: [RISCV][Clang] Support policy functions for 
Vector Mask Instructions. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126749/new/

https://reviews.llvm.org/D126749

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsof_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsif_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -204,7 +204,7 @@
 
 // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t test_viota_m_u8mf8_m

[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

2022-08-04 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG010f329803c8: [RISCV][Clang] Support policy function for all 
vector segment load. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D126750?vs=433270&id=450064#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126750/new/

https://reviews.llvm.org/D126750

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
@@ -6923,3 +6923,28 @@
   return vluxseg8ei64_v_f32mf2(v0, v1, v2, v3, v4, v5, v6, v7, base, bindex, vl);
 }
 
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_tu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t merge0, vint32mf2_t merge1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_tu(v0, v1, merge0, merge1, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv1i32.nxv1i32.i64( undef,  undef, i32* [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_ta(vint32mf2_t *v0, vint32mf2_t *v1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_ta(v0, v1, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
@@ -9051,3 +9051,54 @@
   return vluxseg2ei8_v_i8mf8_m(v0, v1, mask, maskedoff0, maskedoff1, base, bindex, vl);
 }
 
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vluxseg2ei32_v_i32mf2_tuma(vint32mf2_t *v0, vint32mf2_t *v1, vbool64_t mask, vint32mf2_t merge0, vint32mf2_t merge1, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+  return vluxseg2ei32_v_i32mf2_tuma(v0, v1, mask, merge0, merge1, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxseg2ei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv1i32.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], i32* [[BASE:%.*]],  [[BINDEX:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], * [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], * [[V1

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-15 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10
 /// This file describes the RISC-V instructions from the standard 'V' Vector
 /// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been

Do we need to update 0.10 to 1.0-rc?
If the answer is yes, I think maybe we also need to update the clang part (ex. 
arch parsing, predefine macro) in follow-up patches.




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

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[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-15 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.

Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10
 /// This file describes the RISC-V instructions from the standard 'V' Vector
 /// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been

jacquesguan wrote:
> khchen wrote:
> > Do we need to update 0.10 to 1.0-rc?
> > If the answer is yes, I think maybe we also need to update the clang part 
> > (ex. arch parsing, predefine macro) in follow-up patches.
> > 
> > 
> Maybe update it after finishing all changes in 1.0-rc?
> Maybe update it after finishing all changes in 1.0-rc?
Yes.

The other questions like how do you encode `rc1` in `march` or predefined 
architecture extension macro.
or maybe we could just use 1.0 directly because v is still an experiential 
extension.

@luismarques  @frasercrmck @craig.topper @HsiangKai What do you think?

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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

2021-07-18 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

This all looks good to me except some tidy warning.
wait for others comments.




Comment at: llvm/lib/Support/RISCVISAInfo.cpp:460
+
+addExtension("e");
+  }

nit: add `break;` to avoid the implicit-fallthrough warning.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:57
+}
+
 namespace {

nit: please fix this tidy warning


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[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-18 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 359670.
khchen added a comment.

rebase on D105168 .


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-metadata.c
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -331,5 +331,18 @@
   return true;
 }
 
+StringRef computeABIByArch(bool HasD, bool HasE, bool Is64Bit) {
+  if (!Is64Bit) {
+if (HasD)
+  return "ilp32d";
+if (HasE)
+  return "ilp32e";
+return "ilp32";
+  }
+  if (HasD)
+return "lp64d";
+  return "lp64";
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -174,6 +174,7 @@
 void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features);
 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
+StringRef computeABIByArch(bool HasD, bool HasE, bool IsRV64);
 
 } // namespace RISCV
 
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,14 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
 // RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
 // RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
 
+// Test expected behavior when giving -target-cpu
+// This cc1 test is similar to clang with -march=rv32ifd -mcpu=sifive-e31, default abi is ilp32d
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-cpu sifive-e31 -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
+// This cc1 test is similar to clang with -march=rv64i -mcpu=sifive-u74, default abi is lp64
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
+
+// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 // ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
 // ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
 // ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 
+// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
 // LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
 // LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
 // LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -197,22 +197,10 @@
 // Ignore parsing error, just go 3rd step.
 consumeError(std::move(E));
   } else {
-bool HasD = ISAInfo.hasExtension("d");
 unsigned XLen = ISAInfo.getXLen();
-if (XLen == 32) {
-  bool HasE = ISAInfo.hasExtension("e");
-  if (HasD)
-return "ilp32d";
-  else if (HasE)
-return "ilp32e";
-  else
-return "ilp32";
-} else if (XLen == 64) {
-  if (HasD)
-return "lp64d";
-  else
-return "lp64";
-}
+bool HasD = ISAInfo.hasExtension("d");
+bool HasE = ISAInfo.hasExtension("e");
+return llvm::RISCV::computeABIByArch(HasD, HasE, /*IsRV64=*/XLen == 64);
   }
 
   // 3. Choose a default based on

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

2021-07-20 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: jrtc27, MaskRay, kito-cheng.
Herald added subscribers: vkmr, frasercrmck, dexonsmith, evandro, luismarques, 
apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

1. Support a new link behavoir 'OR' for module flag metadata, use for 
riscv-isa-bits.

(This feature could be in separated patch if PoC patch is workable.)

2. riscv-isa-bits records the march information for a module.

RISCVAsmPrinter reads the riscv-isa-bits to generate corrent arch attribute
if -mattr is missing.

Currently RISC-V encodes arch information per function attribute, 
'target-features'.
so there are two issues we want to fix.

1. In IFUNC case (ex. https://godbolt.org/z/a1oTbacn9), the final arch

attribute information is ambiguous because one compilation unit have
different target-feature value in function attribute.
We could not just union of all target-features, because in IFUNC case,
the base arch string is excepted elf arch attribute.

2. During the LTO, clang driver will not pass -march option to LTO code

generator, because users maybe specify the incorrect -march value if
some linked external libraries have been compiled with different arch
extensions.

The probably way is adding a new module flag metadata, riscv-isa-bits, to
records -march info for one compilation unit, and each riscv-isa-bits
get combined (OR) when linking.

In this PoC patch, I think the potential issue is illegal arch combination
will report an error in code generation stage, not in linking stage.
(For example, zfinx is conflict with f/d/q, and Zceb and Zcec are conflict with 
d)
I'm not sure having a target dependence behaivor in bitcode linking does make
sense or not.

Thanks for @jrtc27, @MaskRay to address this issue in D102926 
 and D102925 
,
and @kito-cheng's reminder of exclusive extensions issue.


Repository:
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https://reviews.llvm.org/D106347

Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypeCache.h
  clang/test/CodeGen/RISCV/riscv-metadata-isa-bits-empty-target-feature.cpp
  clang/test/CodeGen/RISCV/riscv-metadata-isa-bits-ifunc.c
  clang/test/CodeGen/RISCV/riscv-metadata-isa-bits.c
  llvm/include/llvm/IR/Module.h
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Linker/IRMover.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-isa-bits.ll
  llvm/test/Linker/Inputs/module-flags-or-1.ll
  llvm/test/Linker/module-flags-or-1.ll

Index: llvm/test/Linker/module-flags-or-1.ll
===
--- /dev/null
+++ llvm/test/Linker/module-flags-or-1.ll
@@ -0,0 +1,18 @@
+; RUN: llvm-link %s %p/Inputs/module-flags-or-1.ll -S -o - | FileCheck %s
+
+; Test OR functionality of module flags.
+
+!0 = !{i32 8, !"or two small values", i32 8}
+; or 7FFF and 8000
+!1 = !{i32 8, !"or two big values-1", i256 9223372036854775807}
+; or 10011001 and 1010101010101010
+!2 = !{i32 8, !"or two big values-2", i256 1152921509170249729}
+!3 = !{i32 8, !"or small and big value", i32 8}
+!4 = !{i32 8, !"foo", i66 8}
+!llvm.module.flags = !{!0, !1, !2, !3, !4}
+
+;CHECK: !0 = !{i32 8, !"or two small values", i32 24}
+;CHECK: !1 = !{i32 8, !"or two big values-1", i256 -1}
+;CHECK: !2 = !{i32 8, !"or two big values-2", i256 1157442769704194065}
+;CHECK: !3 = !{i32 8, !"or small and big value", i256 24}
+;CHECK: !4 = !{i32 8, !"foo", i128 24}
Index: llvm/test/Linker/Inputs/module-flags-or-1.ll
===
--- /dev/null
+++ llvm/test/Linker/Inputs/module-flags-or-1.ll
@@ -0,0 +1,6 @@
+!0 = !{i32 8, !"or two small values", i32 16}
+!1 = !{i32 8, !"or two big values-1", i256 -9223372036854775808}
+!2 = !{i32 8, !"or two big values-2", i256 1157442765409226768}
+!3 = !{i32 8, !"or small and big value", i256 16}
+!4 = !{i32 8, !"foo", i44 16}
+!llvm.module.flags = !{!0, !1, !2, !3, !4}
Index: llvm/test/CodeGen/RISCV/riscv-isa-bits.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-isa-bits.ll
@@ -0,0 +1,36 @@
+; RUN: llc -o - < %s | FileCheck %s
+; -mattr option would overwrite target-feature and module flag riscv-isa-bits
+; RUN: llc -o - -mattr=+f,+d < %s | FileCheck %s -check-prefix=ISA-F-D
+; RUN: llc --filetype=obj -o - < %s | llvm-readelf -A - \
+; RUN:   | FileCheck %s -check-prefix=OBJFILE
+
+; CHECK: .attr

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

2021-07-20 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D106347#2890123 , @jrtc27 wrote:

> Why can't we just save target-features itself as a module flag instead of 
> inventing yet another equivalent encoding? Especially since a long bitfield 
> is brittle, you can't reorder or remove elements without breaking bitcode 
> compatibility.

I think the benefit of using bitfield is making link behavior simpler. I will 
try to investigate another link behavior to handle two different 
target-features strings especially have `+` or `-`.


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[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

2021-07-22 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 360723.
khchen added a comment.

store target-features string as module flag.


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Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/RISCV/riscv-metadata-isa-features-empty-target-feature.cpp
  clang/test/CodeGen/RISCV/riscv-metadata-isa-features-ifunc.c
  clang/test/CodeGen/RISCV/riscv-metadata-isa-features.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/test/CodeGen/RISCV/riscv-isa-features.ll

Index: llvm/test/CodeGen/RISCV/riscv-isa-features.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/riscv-isa-features.ll
@@ -0,0 +1,35 @@
+; RUN: llc -o - < %s | FileCheck %s
+; -mattr option would overwrite target-feature and module flag riscv-isa-features
+; RUN: llc -o - -mattr=+f,+d < %s | FileCheck %s -check-prefix=ISA-F-D
+; RUN: llc --filetype=obj -o - < %s | llvm-readelf -A - \
+; RUN:   | FileCheck %s -check-prefix=OBJFILE
+
+; CHECK:   .attribute  5, "rv64i2p0_m2p0_a2p0_c2p0"
+; ISA-F-D: .attribute  5, "rv64i2p0_f2p0_d2p0"
+
+; OBJFILE: TagName: arch
+; OBJFILE: Value: rv64i2p0_m2p0_a2p0_c2p0
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define float @foo0(i32 %a) nounwind #0 {
+; CHECK:   call__floatsisf@plt
+; ISA-F-D: fcvt.s.wft0, a0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+define float @foo1(i32 %a) nounwind #1 {
+; CHECK:   fcvt.s.wft0, a0
+; ISA-F-D: fcvt.s.wft0, a0
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+attributes #0 = { "target-features"="+64bit,+a,+c,+m"}
+attributes #1 = { "target-features"="+64bit,+a,+c,+d,+f,+m"}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 6, !"riscv-isa-features", !1}
+!1 = !{!"+a", !"+c", !"+m"}
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -27,6 +27,7 @@
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
@@ -178,10 +179,27 @@
 }
 
 void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
-  if (TM.getTargetTriple().isOSBinFormatELF())
-emitAttributes();
+  if (TM.getTargetTriple().isOSBinFormatELF()) {
+RISCVTargetStreamer &RTS =
+static_cast(*OutStreamer->getTargetStreamer());
+const auto *ISAFeatureNodes =
+dyn_cast_or_null(M.getModuleFlag("riscv-isa-features"));
+if (STI->getFeatureString().empty() && ISAFeatureNodes) {
+  std::vector Features;
+  for (const MDOperand &Feature : ISAFeatureNodes->operands()) {
+auto MAttr = cast(Feature.get())->getString();
+Features.push_back(MAttr.str());
+  }
+  unsigned XLEN =
+  TM.getTargetTriple().getArch() == llvm::Triple::riscv32 ? 32 : 64;
+  RISCVISAInfo ISAInfo;
+  ISAInfo.parse(XLEN, Features);
+  RTS.emitTargetAttributes(ISAInfo);
+} else {
+  RTS.emitTargetAttributes(*STI);
+}
+  }
 }
-
 void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
   RISCVTargetStreamer &RTS =
   static_cast(*OutStreamer->getTargetStreamer());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -11,6 +11,7 @@
 
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
@@ -36,6 +37,7 @@
 StringRef StringValue);
 
   void emitTargetAttributes(const MCSubtargetInfo &STI);
+  void emitTargetAttributes(const RISCVISAInfo &ISAInfo);
 };
 
 // This part is for ascii assembly output
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -49,9 +49,15 @@
   unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
   std::vector FeatureVector;
   RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
   ISAInfo.parse(XLen, FeatureVector);
+  emitTargetAttributes(ISAInfo);
+}
 
+void RISCVTargetStreamer::emitTargetAttributes(const RISCVISAInfo &ISAInfo) {
+  if (ISAInfo.hasExtension("e"))
+emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
+  el

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 361216.
khchen added a comment.

address arichardson's comment, thanks!


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D10/new/

https://reviews.llvm.org/D10

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-metadata.c
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -331,5 +331,20 @@
   return true;
 }
 
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo,
+bool Is64Bit) {
+  bool HasD = ISAInfo.hasExtension("d");
+  if (!Is64Bit) {
+if (HasD)
+  return "ilp32d";
+if (ISAInfo.hasExtension("e"))
+  return "ilp32e";
+return "ilp32";
+  }
+  if (HasD)
+return "lp64d";
+  return "lp64";
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -17,8 +17,9 @@
 // FIXME: vector is used because that's what clang uses for subtarget feature
 // lists, but SmallVector would probably be better
 #include "llvm/ADT/Triple.h"
-#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/AArch64TargetParser.h"
+#include "llvm/Support/ARMTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include 
 
 namespace llvm {
@@ -174,6 +175,8 @@
 void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features);
 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo,
+bool IsRV64);
 
 } // namespace RISCV
 
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,14 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
 // RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
 // RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
 
+// Test expected behavior when giving -target-cpu
+// This cc1 test is similar to clang with -march=rv32ifd -mcpu=sifive-e31, default abi is ilp32d
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-cpu sifive-e31 -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
+// This cc1 test is similar to clang with -march=rv64i -mcpu=sifive-u74, default abi is lp64
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
+
+// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 // ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
 // ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
 // ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 
+// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
 // LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
 // LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
 // LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -197,22 +197,9 @@
 // Ignore parsing error, just go 3rd step.
 consumeError(std::move(E));
   } else {
-bool HasD = ISAInfo.hasExtension("d");
 unsign

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen marked an inline comment as done.
khchen added a comment.




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[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-features'.

2021-07-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/lib/CodeGen/CodeGenModule.cpp:835
+llvm::RISCVISAInfo::filterISAStrings(Features);
+std::vector Ops;
+if (Features.empty()) {

jrtc27 wrote:
> Why is this building a list? Just use a string so it's in the same format as 
> the function attributes? We already have parsers for that. Yes, it means you 
> do a small amount of redundant work but having a single format in the IR for 
> representing the same thing in every place is better than having multiple 
> different ways of representing the same thing.
Because I think maybe the merge behavior `AppendUnique` is the best way to 
merge two module with different value of metadata flag, and it requires a 
metadata node with operands list.
Personally, I did not like to to have a new merge behavior to merge two 
target-features string, but maybe there is another better merging behavior I 
never thought,

In addition, some target features are not related to extension information, for 
example, +relax, +save-restore. Should we really need to record those 
unnecessary information in module?

What do you think?







Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:187
+dyn_cast_or_null(M.getModuleFlag("riscv-isa-features"));
+if (STI->getFeatureString().empty() && ISAFeatureNodes) {
+  std::vector Features;

jrtc27 wrote:
> This doesn't make sense. The module flag should have been parsed and applied 
> to the subtarget long ago. And an empty feature string means no features, not 
> that they're missing. The fact that you need to change this code here is a 
> sign that code elsewhere is wrong.
What's excepted elf attribute if llc with -mattr=+f,+d but the 
riscv-isa-features module flag is +a,+c+m?
I think it will be +f, +d, so we need to make sure -mattr is empty before use 
the module flag.  Does it make sense?

> The module flag should have been parsed and applied to the subtarget long 
> ago. 
Sorry, I didn't understand it. The module flag `riscv-isa-features` is not 
applied to subtarget, I only use it to generate the correct extension 
.attribute. 

Maybe I misunderstood something?




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[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 361264.
khchen added a comment.

address @jrtc27's comment, thanks! I forget RISCVISAInfo include XLen..


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-metadata.c
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -331,5 +331,18 @@
   return true;
 }
 
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo) {
+  if (ISAInfo.getXLen() == 32) {
+if (ISAInfo.hasExtension("d"))
+  return "ilp32d";
+if (ISAInfo.hasExtension("e"))
+  return "ilp32e";
+return "ilp32";
+  }
+  if (ISAInfo.hasExtension("d"))
+return "lp64d";
+  return "lp64";
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -17,8 +17,9 @@
 // FIXME: vector is used because that's what clang uses for subtarget feature
 // lists, but SmallVector would probably be better
 #include "llvm/ADT/Triple.h"
-#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/AArch64TargetParser.h"
+#include "llvm/Support/ARMTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include 
 
 namespace llvm {
@@ -174,6 +175,7 @@
 void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features);
 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo);
 
 } // namespace RISCV
 
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,14 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
 // RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
 // RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
 
+// Test expected behavior when giving -target-cpu
+// This cc1 test is similar to clang with -march=rv32ifd -mcpu=sifive-e31, default abi is ilp32d
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-cpu sifive-e31 -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
+// This cc1 test is similar to clang with -march=rv64i -mcpu=sifive-u74, default abi is lp64
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
+
+// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 // ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
 // ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
 // ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 
+// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
 // LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
 // LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
 // LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -197,22 +197,7 @@
 // Ignore parsing error, just go 3rd step.
 consumeError(std::move(E));
   } else {
-bool HasD = ISAInfo.hasExtension("d");
-unsigned XLen = ISAInfo.getXLen();
-if (XLen == 32) {
-

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-25 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 361568.
khchen marked 6 inline comments as done.
khchen added a comment.

address @jrtc27's comment, thanks again!


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-metadata.c
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -331,5 +331,20 @@
   return true;
 }
 
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo) {
+  if (ISAInfo.getXLen() == 32) {
+if (ISAInfo.hasExtension("d"))
+  return "ilp32d";
+if (ISAInfo.hasExtension("e"))
+  return "ilp32e";
+return "ilp32";
+  } else if (ISAInfo.getXLen() == 64) {
+if (ISAInfo.hasExtension("d"))
+  return "lp64d";
+return "lp64";
+  }
+  llvm_unreachable("Invalid XLEN");
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -17,8 +17,9 @@
 // FIXME: vector is used because that's what clang uses for subtarget feature
 // lists, but SmallVector would probably be better
 #include "llvm/ADT/Triple.h"
-#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/AArch64TargetParser.h"
+#include "llvm/Support/ARMTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include 
 
 namespace llvm {
@@ -174,6 +175,7 @@
 void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features);
 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
+StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo);
 
 } // namespace RISCV
 
Index: clang/test/CodeGen/RISCV/riscv-metadata.c
===
--- clang/test/CodeGen/RISCV/riscv-metadata.c
+++ clang/test/CodeGen/RISCV/riscv-metadata.c
@@ -1,14 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-ILP32 %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
 // RUN: %clang_cc1 -triple riscv32 -target-abi ilp32 -emit-llvm -o - %s | FileCheck -check-prefix=ILP32 %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -o - %s | FileCheck -check-prefix=ILP32F %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d -emit-llvm -o - %s | FileCheck -check-prefix=ILP32D %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -emit-llvm -o - %s | FileCheck -check-prefix=EMPTY-LP64D %s
 // RUN: %clang_cc1 -triple riscv64 -target-abi lp64 -emit-llvm -o - %s | FileCheck -check-prefix=LP64 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -o - %s | FileCheck -check-prefix=LP64F %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-abi lp64d -emit-llvm -o - %s | FileCheck -check-prefix=LP64D %s
 
+// Test expected behavior when giving -target-cpu
+// This cc1 test is similar to clang with -march=rv32ifd -mcpu=sifive-e31, default abi is ilp32d
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -target-feature +f -target-feature +d -target-cpu sifive-e31 -o - %s | FileCheck -check-prefix=EMPTY-ILP32D %s
+// This cc1 test is similar to clang with -march=rv64i -mcpu=sifive-u74, default abi is lp64
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu sifive-u74 %s | FileCheck -check-prefix=EMPTY-LP64 %s
+
+// EMPTY-ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
+// EMPTY-ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 // ILP32: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32"}
 // ILP32F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32f"}
 // ILP32D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"ilp32d"}
 
+// EMPTY-LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
+// EMPTY-LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
 // LP64: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64"}
 // LP64F: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64f"}
 // LP64D: !{{[0-9]+}} = !{i32 1, !"target-abi", !"lp64d"}
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -197,22 +197,7 @@
 // Ignore parsing error, just go 3rd step.
 consumeError(std::move(E));
   } else {
-bool HasD

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

2021-07-27 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

This patch depends on D105168 , 
Please help to review it if you have time.
Thanks!


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[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

2022-03-14 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, kito-cheng.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

Improve test converage.


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https://reviews.llvm.org/D121578

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD-INVAL %s
 // RV32-STD-INVAL: error: invalid arch name 'rv32imw',
@@ -376,6 +401,18 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

2022-03-14 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

LGTM. wait @kito-cheng  to approve it.


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[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

2022-03-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 416057.
khchen added a comment.
Herald added subscribers: s, arichardson.

rebase on main.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

2022-03-18 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.
Herald added a subscriber: s.

In D70401#3384758 , @pcwang-thead 
wrote:

> In D70401#3250049 , @khchen wrote:
>
>> 1. please add a check here 
>> 
>>  and a clang cc1 test for it.
>> 2. Have you try to run llvm-test-suite with rv32e config on qemu?
>
>
>
> 1. Thanks, I may do it later. And here is a question: the comment 
> 
>  says `It is illegal to specify 'e' extensions with 'f' and 'd'`.
>
> While ilp32e 
> 
>  says:
>
>> The ILP32E calling convention is not compatible with ISAs that have 
>> registers that require load and store alignments of more than 32 bits. In 
>> particular, this calling convention must not be used with the D ISA 
>> extension.
>
> And, the RV32E 
>  chapter 
> in RISCV ISA manual says:
>
>> RV32E can be combined with all current standard extensions.
>
> If I understand correctly, E can't be combined with D in current 
> specification since E must use ILP32E calling convention.

IMO, at least clang need to follows the gcc's implementation.
I guess gcc implementation follow riscv-elf-psabi-doc, @kito-cheng could you 
please confirm that?

> 2. I have run llvm-test-suite with rv32e on qemu, and found no major fault 
> for current implementation. Some tests are disabled because they can't run on 
> bare mental (sees Disabled llvm-test-suite cases 
> ).
>
> There are some failed tests due to floating-point precision, but I saw the 
> same result when run with  rv32imc on bare mental. I haven't taken the time 
> to find out the reason, but I guess it may be soft-float issues.

Thanks for testing!! I also tested your patch locally, 
Could you please make sure all gcc and clang results are the same in your 
failed tests?

I found 
https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c
 result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
Did you have same issue?

my build option:

  $/path/to/rv32e-gcc/bin/riscv32-unknown-elf-gcc -march=rv32e -mabi=ilp32e 
2003-05-26-Shorts.c
  $./bin/clang --target=riscv32 -march=rv32e -mabi=ilp32e 
--gcc-toolchain=/path/to/rv32e-gcc/ 2003-05-26-Shorts.c 

clang output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = 0 (0xafafafaf)

  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = -2060025877491592863 
(0xe3695161)   


  i = -976897885 (0xc5c5b8a3) L-i = 0 (0xafafafb0)  

   i* i = -1912031287 (0x8e08b7c9)L/ i = 6996953267980741613 
(0x611a2bed0001)   


  us= 47267 (0xb8a3)  UL-us = -4195947477825748992 
(0xc5c5afafafaf) 
  us*us = 2234169289 (0x852ab7c9)   UL/us = 1452874783539635691 
(0x1429a5ebf397)


   s= -18269 (0xb8a3) L-s = -4195666002849038335 
(0xc5c6afafafaf)   
   s* s = 333756361 (0x13e4b7c9)  L/ s = -7718140893307295808 
(0x94e3a7c1201b)  


  ub= 163 (0xa3)  UL-ub = -4195745167686238208 
(0xc5c5b800afafafaf) 
  ub*ub = 26569 (0x67c9)  UL/ub = 2350833624863004346 
(0x209fd6ba0113eca9)  


   b= -93 (0xffa3)L-b = -4195744068174610431 
(0xc5c5b900afafafaf)   
   b* b = 8649 (0x21c9)   L/b = -1938405340110362979 
(0xe519669d00dd1421)   

gcc output:

 ui = 3318069411 (0xc5c5b8a3) UL-ui = -5787213829993660416 
(0xafafafaf)
  ui*ui = 2382936009 (0x8e08b7c9)   UL/ui = 3815330145 (0xe3695161)
  
  i = -976897885 (0xc5c5b8a3) L-i = -5787213825698693120 
(0xafafafb0)
   i* i = -1912031287 (0x8e08b7c9)L/ i = 5924072429 (0x1611a2bed)
  
  us= 47267 (0xb8a3)  UL-us = -5787213826675638272 
(0xafafafafc5c5)
  us*us = 2234169289 (0x852ab7c9)   UL/us = 267830203885035 (0xf3971429a5eb)
  
   s= -18269 (0xb8a3) L-s = -5787213826675572736 
(0xafafafafc5c6)
   s* s = 333756361 (0x13e4b7c9)  L/ s = 316777810864064 (0x1201b94e3a7c0)
  
  ub= 163 (0xa3)  UL-ub = -5787213826675591168 
(0xafaf

[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

2022-03-18 Thread Zakk Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf5fea45d09e5: [RISCV][NFC] Add tests to address invalid arch 
dependencies. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STD-INVAL %s
 // RV32-STD-INVAL: error: invalid arch name 'rv32imw',
@@ -376,6 +401,18 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
 // RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfh -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFH %s
+// RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin01p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzfhmin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
+// RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izbb -### %s \


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -224,6 +224,31 @@
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv64e -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
+// RV64-EER: error: invalid arch name 'rv64e',
+// RV64-EER: standard user-level extension 'e' requires 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-DER %s
+// RV32-DER: error: invalid arch name 'rv32id',
+// RV32-DER: d requires f extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izve32f -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
+// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
+// RV32-ZVE32F-ER: zve32f requires f or zfinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ifzve64d -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
+// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
+// RV32-ZVE64D-ER: zve64d requires d or zdinx extension to also be specified
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl64b -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
+// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
+// RV32-ZVL64B-ER: zvl*b requires v or zve* extension to also be specified
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32imw -

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

2022-03-21 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

2022-03-22 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9ab18cc53537: [RISCV] Add policy operand for masked vid and 
viota IR intrinsics. (authored by khchen).
Herald added subscribers: s, StephenFan, arichardson.
Herald added a project: All.

Changed prior to commit:
  https://reviews.llvm.org/D120227?vs=410209&id=417223#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/riscv_vector.td
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll

Index: llvm/test/CodeGen/RISCV/rvv/viota.ll
===
--- llvm/test/CodeGen/RISCV/rvv/viota.ll
+++ llvm/test/CodeGen/RISCV/rvv/viota.ll
@@ -27,7 +27,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i8_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
@@ -40,7 +40,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -69,7 +69,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i8_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
@@ -82,7 +82,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -111,7 +111,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i8_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
@@ -124,7 +124,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -153,7 +153,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i8_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
@@ -166,7 +166,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -195,7 +195,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i8_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
@@ -208,7 +208,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -237,7 +237,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv32i8_nxv32i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
@@ -250,7 +250,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -279,7 +279,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv64i8_nxv64i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
@@ -292,7 +292,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -321,7 +321,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv1i16_nxv1i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
@@ -334,7 +334,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -363,7 +363,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv2i16_nxv2i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
@@ -376,7 +376,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -405,7 +405,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv4i16_nxv4i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
@@ -418,7 +418,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -447,7 +447,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv8i16_nxv8i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
@@ -460,7 +460,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -489,7 +489,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv16i16_nxv16i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
@@ -502,7 +502,7 @@
  %0,
  %1,
  %1,
-iXLen %2)
+iXLen %2, iXLen 0)
 
   ret  %a
 }
@@ -531,7 +531,7 @@
   ,
   ,
   ,
-  iXLen);
+  iXLen, iXLen);
 
 define  @intrinsic_viota_mask_m_nxv32i16_nxv32i1( %0,  %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

2022-03-22 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG10fd2822b77e: [RISCV] Add policy operand for masked compare 
and vmsbf/vmsif/vmsof IR (authored by khchen).
Herald added a subscriber: StephenFan.

Changed prior to commit:
  https://reviews.llvm.org/D120228?vs=416057&id=417297#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120228/new/

https://reviews.llvm.org/D120228

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof.ll

___
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cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

2022-03-22 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23d60ce164db: [RISCV][NFC] Refine and refactor RISCVVEmitter 
and riscv_vector.td. (authored by khchen).
Herald added subscribers: s, StephenFan, arichardson.

Changed prior to commit:
  https://reviews.llvm.org/D120870?vs=412606&id=417330#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120870/new/

https://reviews.llvm.org/D120870

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td

Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -220,7 +220,7 @@
   }
   // For unit stride load with mask
   // Input: (maskedoff, pointer, mask, vl, policy)
-  class RISCVUSLoadMask
+  class RISCVUSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -235,7 +235,7 @@
   // Output: (data, vl)
   // NOTE: We model this with default memory properties since we model writing
   // VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
-  class RISCVUSLoadFFMask
+  class RISCVUSLoadFFMasked
 : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
 [LLVMMatchType<0>,
  LLVMPointerType>,
@@ -256,7 +256,7 @@
   }
   // For strided load with mask
   // Input: (maskedoff, pointer, stride, mask, vl, policy)
-  class RISCVSLoadMask
+  class RISCVSLoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyint_ty,
@@ -278,7 +278,7 @@
   }
   // For indexed load with mask
   // Input: (maskedoff, pointer, index, mask, vl, policy)
-  class RISCVILoadMask
+  class RISCVILoadMasked
 : Intrinsic<[llvm_anyvector_ty ],
 [LLVMMatchType<0>,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -300,7 +300,7 @@
   }
   // For unit stride store with mask
   // Input: (vector_in, pointer, mask, vl)
-  class RISCVUSStoreMask
+  class RISCVUSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>,
@@ -321,7 +321,7 @@
   }
   // For stride store with mask
   // Input: (vector_in, pointer, stirde, mask, vl)
-  class RISCVSStoreMask
+  class RISCVSStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyint_ty,
@@ -341,7 +341,7 @@
   }
   // For indexed store with mask
   // Input: (vector_in, pointer, index, mask, vl)
-  class RISCVIStoreMask
+  class RISCVIStoreMasked
 : Intrinsic<[],
 [llvm_anyvector_ty,
  LLVMPointerType>, llvm_anyvector_ty,
@@ -351,7 +351,7 @@
   }
   // For destination vector type is the same as source vector.
   // Input: (passthru, vector_in, vl)
-  class RISCVUnaryAANoMask
+  class RISCVUnaryAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -359,7 +359,7 @@
   }
   // For destination vector type is the same as first source vector (with mask).
   // Input: (vector_in, vector_in, mask, vl, policy)
-  class RISCVUnaryAAMask
+  class RISCVUnaryAAMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -377,7 +377,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
-  class RISCVBinaryAAANoMask
+  class RISCVBinaryAAAUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
 [IntrNoMem]>, RISCVVIntrinsic {
@@ -385,7 +385,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (passthru, vector_in, int_vector_in, vl)
-  class RISCVRGatherVVNoMask
+  class RISCVRGatherVVUnMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>,
  LLVMVectorOfBitcastsToInt<0>, llvm_anyint_ty],
@@ -394,7 +394,7 @@
   }
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, int_vector_in, vl, policy)
-  class RISCVRGatherVVMask
+  class RISCVRGatherVVMasked
 : Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>,
  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -403,7 +403,7 @@
 let V

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

2022-04-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Re-run the update_cc_test_checks.py to update expected result.
I'm not sure why those tests are passed before.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124062

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
@@ -160,7 +160,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t test_vid_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
@@ -170,7 +170,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf4_t test_vid_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
@@ -180,7 +180,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf2_t test_vid_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
@@ -190,7 +190,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m1_t test_vid_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {
@@ -199,7 +199,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m2_t test_vid_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {
@@ -208,7 +208,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m4_t test_vid_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {
@@ -217,7 +217,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m8_t test_vid_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {
@@ -226,7 +226,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf4_t test_vid_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
@@ -236,7 +236,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf2_m(
 // CHECK-RV6

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

2022-04-20 Thread Zakk Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbd0d126302a8: [RISCV][Clang][NFC] Update vid intrinsic 
tests. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124062/new/

https://reviews.llvm.org/D124062

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
@@ -160,7 +160,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t test_vid_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff,
@@ -170,7 +170,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf4_t test_vid_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff,
@@ -180,7 +180,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf2_t test_vid_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff,
@@ -190,7 +190,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m1_t test_vid_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) {
@@ -199,7 +199,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m2_t test_vid_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) {
@@ -208,7 +208,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m4_t test_vid_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) {
@@ -217,7 +217,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8m8_t test_vid_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) {
@@ -226,7 +226,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf4_t test_vid_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff,
@@ -236,7 +236,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16mf2_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vid.mask.nxv2i16.i64( [[MASKEDOFF:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint16mf2_t test_vid_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff,
@@ -246,7 +246,7 @@
 
 // CHECK-RV64-LABEL: @test_vid_v_u16m1_m(

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

2022-04-20 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D124062#3461069 , @frasercrmck 
wrote:

> Were they perhaps passing because `i64 [[VL:%.*]]` was matching the `, i64 0` 
> too? Seems like a flaw in the checks generated by the script, but I can see 
> how the majority of the time the brevity is nice.

Yes, agree.

Thanks for reviewing.


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[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

2022-02-08 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

clang will calculate the default target-abi if -mabi is empty and encode the it 
in LLVM IR module flag.
then if llc has no target-abi option (`Options.MCOptions.ABIName` is empty), in 
getSubtargetImpl it uses different way to compute the default target-abi, then 
the default result is not same.
Currently it works well because getSubtargetImpl only check the ABI when 
`Options.MCOptions.ABIName` is not empty.


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[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

2022-02-08 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: asb, kito-cheng, craig.topper, jrtc27.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar, 
hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in

RISCVISAInfo.

2. Add parseFeatureBits which may used in D118333 
.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119250

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -45,11 +45,8 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+  auto ParseResult = RISCVFeatures::parseFeatureBits(
+  STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
 /* Assume any error about features should handled earlier.  */
 consumeError(ParseResult.takeError());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -18,6 +18,7 @@
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
@@ -344,9 +345,8 @@
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 
-// Convert FeatureBitset to FeatureVector.
-void toFeatureVector(std::vector &FeatureVector,
- const FeatureBitset &FeatureBits);
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
 
 } // namespace RISCVFeatures
 
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
@@ -106,13 +107,17 @@
 report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
-void toFeatureVector(std::vector &FeatureVector,
- const FeatureBitset &FeatureBits) {
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
+  unsigned XLen = IsRV64 ? 64 : 32;
+  std::vector FeatureVector;
+  // Convert FeatureBitset to FeatureVector.
   for (auto Feature : RISCVFeatureKV) {
 if (FeatureBits[Feature.Value] &&
 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
   FeatureVector.push_back(std::string("+") + Feature.Key);
   }
+  return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
 }
 
 } // namespace RISCVFeatures
Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -329,21 +329,6 @@
   return true;
 }
 
-StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo) {
-  if (ISAInfo.getXLen() == 32) {
-if (ISAInfo.hasExtension("d"))
-  return "ilp32d";
-if (ISAInfo.hasExtension("e"))
-  return "ilp32e";
-return "ilp32";
-  } else if (ISAInfo.getXLen() == 64) {
-if (ISAInfo.hasExtension("d"))
-  return "lp64d";
-return "lp64";
-  }
-  llvm_unreachable("Invalid XLEN");
-}
-
 } // namespace RISCV
 } // namespace llvm
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

2022-02-08 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 406842.
khchen added a comment.

rebase on D119250  to make changes clear.

Thanks for kito's suggestion!


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Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/frm-dependency.ll
  llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
  llvm/test/MC/RISCV/mattr-invalid-combination.s

Index: llvm/test/MC/RISCV/mattr-invalid-combination.s
===
--- llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
 # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
 # RUN:   | FileCheck %s -check-prefix=RV64E
 
-# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
+# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
===
--- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 \
 ; RUN:   -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32IBT
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IBT
 
 ; Selects of wide values are split into two selects, which can easily cause
Index: llvm/test/CodeGen/RISCV/select-const.ll
===
--- llvm/test/CodeGen/RISCV/select-const.ll
+++ llvm/test/CodeGen/RISCV/select-const.ll
@@ -1,19 +1,19 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

2022-02-08 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcfe7f690367b: [RISCV][NFC] Refactor RISCVISAInfo. (authored 
by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119250/new/

https://reviews.llvm.org/D119250

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -45,11 +45,8 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
-  std::vector FeatureVector;
-  RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
-
-  auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
+  auto ParseResult = RISCVFeatures::parseFeatureBits(
+  STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
 /* Assume any error about features should handled earlier.  */
 consumeError(ParseResult.takeError());
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -18,6 +18,7 @@
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 namespace llvm {
 
@@ -344,9 +345,8 @@
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 
-// Convert FeatureBitset to FeatureVector.
-void toFeatureVector(std::vector &FeatureVector,
- const FeatureBitset &FeatureBits);
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
 
 } // namespace RISCVFeatures
 
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
@@ -106,13 +107,17 @@
 report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
-void toFeatureVector(std::vector &FeatureVector,
- const FeatureBitset &FeatureBits) {
+llvm::Expected>
+parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
+  unsigned XLen = IsRV64 ? 64 : 32;
+  std::vector FeatureVector;
+  // Convert FeatureBitset to FeatureVector.
   for (auto Feature : RISCVFeatureKV) {
 if (FeatureBits[Feature.Value] &&
 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
   FeatureVector.push_back(std::string("+") + Feature.Key);
   }
+  return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
 }
 
 } // namespace RISCVFeatures
Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -329,21 +329,6 @@
   return true;
 }
 
-StringRef computeDefaultABIFromArch(const llvm::RISCVISAInfo &ISAInfo) {
-  if (ISAInfo.getXLen() == 32) {
-if (ISAInfo.hasExtension("d"))
-  return "ilp32d";
-if (ISAInfo.hasExtension("e"))
-  return "ilp32e";
-return "ilp32";
-  } else if (ISAInfo.getXLen() == 64) {
-if (ISAInfo.hasExtension("d"))
-  return "lp64d";
-return "lp64";
-  }
-  llvm_unreachable("Invalid XLEN");
-}
-
 } // namespace RISCV
 } // namespace llvm
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -914,3 +914,18 @@
 return std::move(Result);
   return std::move(ISAInfo);
 }
+
+StringRef RISCVISAInfo::computeDefaultABI() const {
+  if (XLen == 32) {
+if (hasExtension("d"))
+  return "ilp32d";
+if (hasExtension("e"))
+  return "ilp32e";
+return "ilp32";
+  } else if (XLen == 64) {
+if (hasExtension("d"))
+  return "lp64d";
+return "lp64";
+  }
+  llvm_unreachable("Invalid XLEN");
+}
Index: llvm/include/llvm/Support/

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

2022-02-10 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

Gentle ping.


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[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

2022-02-10 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

Gentle ping.


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[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

2022-02-11 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd224be3b999a: [RISCV] Add the policy operand for some masked 
RVV ternary IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D117681?vs=403117&id=407849#toc

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D119686: [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.

2022-02-13 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

2022-02-14 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, 
jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.

The nomask vector Multiply-Add need a policy operand because merge value could 
not be undef.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119727

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

2022-02-15 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 408840.
khchen added a comment.

Rebase and refine code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119727/new/

https://reviews.llvm.org/D119727

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

2022-02-15 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb7847199044e: [RISCV] Add the passthru operand for RVV 
nomask binary intrinsics. (authored by khchen).
Herald added a subscriber: qcolombet.

Changed prior to commit:
  https://reviews.llvm.org/D117989?vs=408696&id=409119#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117989/new/

https://reviews.llvm.org/D117989

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul-eew64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
  clang/test/Co

[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

2022-02-15 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV 
nomask unary and nullary… (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D118253?vs=403269&id=409155#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118253/new/

https://reviews.llvm.org/D118253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfclass.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
  llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
  llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vid.ll
  llvm/test/CodeGen/RISCV/rvv/viota.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

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[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

2022-02-15 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 409156.
khchen added a comment.

rebase and add more one test.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

2022-02-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D70401#3325419 , @zixuan-wu wrote:

> It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there 
> are no workable environment such as runtime and kernel for ilp32e in GNU 
> series tools.
> And we can not run llvm-test-suite in baremental environment(NOT linux but 
> elf triple). So I have a question about how to test llvm in elf triple and 
> environment? Is there any test case llvm community normally uses and accepts?

I believe you can try QEMU, I tried it before.
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/JE0aG-Mr0u4/m/tfFoITv7AgAJ
For llvm-test-suite, you could disable some non-baremental tests manually.
I found some issues in my local rv32e implementation by running llvm-test-suite 
before, it's why I think it's good to have a test.

Maybe the other reviewers have different opinions about this.
@luismarques @jrtc27 @asb @kito-cheng What do you think?

Repository:
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[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

2022-02-17 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG093ecccdab47: [RISCV] Add the passthru operand for 
vadc/vsbc/vmerge/vfmerge IR intrinsics. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119686/new/

https://reviews.llvm.org/D119686

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

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[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

2022-02-17 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGca783124073f: [RISCV] Add the policy operand for nomask 
vector Multiply-Add IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D119727?vs=408840&id=409687#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/memory-args.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

2022-04-21 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D124186#3465136 , @craig.topper 
wrote:

> The intrinsic interface doesn't care about 0 give user control of vstart. Nearly every instruction is undisturbed for 
> 0
> But having said that it probably makes sense to keep the vslideup/down 
> interface the same.



In D124186#3465136 , @craig.topper 
wrote:

> The intrinsic interface doesn't care about 0 give user control of vstart. Nearly every instruction is undisturbed for 
> 0
> But having said that it probably makes sense to keep the vslideup/down 
> interface the same.

Yes I know, but I didn't clarify that in comment, thanks for your advice.


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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

2022-04-22 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 424517.
khchen edited the summary of this revision.
khchen added a comment.

update clang tests.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

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[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

2022-04-25 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGffe03ff75c26: [RISCV] Fix incorrect policy implement for 
unmasked vslidedown and vslideup. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D124186?vs=424517&id=424934#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124186/new/

https://reviews.llvm.org/D124186

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

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[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

2022-04-27 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

It's seem like all targets need to return `false` in 
`useFP16ConversionIntrinsics` for correctness of `int16` -> `__fp16` conversion?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D124509/new/

https://reviews.llvm.org/D124509

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[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

2022-04-28 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, asb, luismarques.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

Test experimental arch, Zfh, Zfmin and Zve arch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124611

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,28 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE-BADVERS %s
+// RV32-ZVE-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE-GOODVERS %s
+// RV32-ZVE-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMEN

[PATCH] D124510: [RISCV] Precommit test for D124509

2022-04-29 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

2022-05-03 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 426587.
khchen added a comment.

Add zve64* tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124611/new/

https://reviews.llvm.org/D124611

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,48 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-BADVERS %s
+// RV32-ZVE32X-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE32X-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-GOODVERS %s
+// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64X %s
+// RV32-ZVE64X: "-target-feature" "+zve64x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
+// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
+// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
+// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', zve64d 
requires d or zdinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
+// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN:

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

2022-05-04 Thread Zakk Chen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6c10014f1de6: [RISCV][Clang] add more tests for clang 
driver. (NFC) (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124611/new/

https://reviews.llvm.org/D124611

Files:
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -412,6 +412,26 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
 // RV32-ZFHMIN: "-target-feature" "+zfhmin"
 
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG 
%s
+// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS 
%s
+// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izbt'
+// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version 
number
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p1 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS 
%s
+// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izbt0p1'
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental 
extension
+// RV32-EXPERIMENTAL-BADVERS: 'zbt'(this compiler supports 0.93)
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbt0p93 
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 
-check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
+// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zbt"
+
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb -### %s \
@@ -494,3 +514,48 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izk1p0 -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZK %s
 // RV32-ZK: "-target-feature" "+zk"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfh1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFH %s
+// CHECK-RV32-ZFH: "-target-feature" "+zfh"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfhmin1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CHECK-RV32-ZFHMIN %s
+// CHECK-RV32-ZFHMIN: "-target-feature" "+zfhmin"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x0p1 -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-BADVERS %s
+// RV32-ZVE32X-BADVERS: error: invalid arch name 'rv32izve32x0p1'
+// RV32-ZVE32X-BADVERS: unsupported version number 0.1 for extension 'zve32x'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32X-GOODVERS %s
+// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
+// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
+// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64x -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64X %s
+// RV32-ZVE64X: "-target-feature" "+zve64x"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 
| \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
+// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', zve32f 
requires f or zfinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
+// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
+// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', zve64d 
requires d or zdinx extension to also be specified
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 
2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
+// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"


Index: clang/test/Driver/riscv-arch.c
===
---

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

2022-05-10 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, 
arcbbb, monkchiang, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, 
arichardson, qcolombet, MatzeB.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.


Repository:
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https://reviews.llvm.org/D125323

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-11 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.
Herald added a subscriber: shiva0217.

Thanks for refactoring!




Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55
+// basic vector type, used to compute type info of arguments.
+enum class PrimitiveType : uint8_t {
+  Invalid,

I think vector is not a primitive type in common sense, is it?
why Widening2XVector, Widening4XVector, Widening8XVector and MaskVector is not 
part of VectorTypeModifier?

Sorry, I'm confused and maybe forget something.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:85
+// TypeProfile is used to compute type info of arguments or return value.
+struct TypeProfile {
+  constexpr TypeProfile() = default;

I think we need to update the comment in riscv_vector.td to sync the word 
"TypeProfile", I feel the new word `TypeProfile` is similar to `modifier` or 
`prototype`, is it?

```
The C/C++ prototype of the builtin is defined by the Prototype attribute.
Prototype is a non-empty sequence of type transformers, the first of which
is the return type of the builtin and the rest are the parameters of the
builtin, in order. For instance if Prototype is "wvv" and TypeRange is "si"
a first builtin will have type
```

we call it  `modifier` or `prototype` is because those words are coming from 
clang intrinsic definition and other target.

https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.def#L52
https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/arm_sve.td#L58

personally I think consistent naming maybe better than creating a new word, 
what do you think?


BTW, I think having this new class is really good idea for refactoring!



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:90
+  : PT(static_cast(PT)), TM(static_cast(TM)) {}
+  constexpr TypeProfile(uint8_t PT, uint8_t VTM, uint8_t TM)
+  : PT(PT), VTM(VTM), TM(TM) {}

If we allow parameter could `uint8_t`, why other constructors not follow the 
same rule?



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:97
+
+  std::string IndexStr() const {
+return std::to_string(PT) + "_" + std::to_string(VTM) + "_" +

What's purpose of this function, translate TypeProfile to the Proto string?



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:249
+  /// and LMUL with type transformers). It also record result of type in legal
+  /// or illegal set to avoid compute the  same config again. The result maybe
+  /// have illegal RVVType.

additional space



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:767
+
+void RVVType::applyFixedLog2LMUL(int Log2LMUL, bool LargerThan) {
+  if (LargerThan) {

In riscv_vector.td is said smaller or larger, I feel little confusing here when 
it call LagerThan. maybe have more comment like `The result of modified type 
should be smaller than giving type` ?


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

2022-05-11 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 428674.
khchen added a comment.

address Craig's comments, thanks!!


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

2022-05-13 Thread Zakk Chen via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7dfc56c10746: [RISCV] Add the passthru operand for RVV 
unmasked segment load IR intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D125323?vs=428674&id=429171#toc

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-13 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

Thanks Kito. This all LGTM except some warnings need to fix.




Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:384
+return PD;
   // Handle primitive type transformer
+  auto PType = PrototypeDescriptorStr.back();

so we also need to update this comment as base type transformer?



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:718
+  default:
+llvm_unreachable("Illegal vector type modifier!");
+  }

Don’t use default labels in fully covered switches over enumerations
please remove default in `RISCVVIntrinsicUtils.cpp:624`, 
`RISCVVIntrinsicUtils.cpp:717` and `RISCVVIntrinsicUtils.cpp:793`.



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:962
+  }
+  return std::move(PrototypeDescriptors);
+}

```
clang/lib/Support/RISCVVIntrinsicUtils.cpp:962:10: warning: moving a local 
object in a return statement prevents copy elision [-Wpessimizing-move]
  return std::move(PrototypeDescriptors);
 ^
clang/lib/Support/RISCVVIntrinsicUtils.cpp:962:10: note: remove std::move call 
here
  return std::move(PrototypeDescriptors);
```


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

2022-05-13 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

Do we need to have some tests in `clang/test/PCH/` for new #pragma?




Comment at: clang/lib/Sema/SemaLookup.cpp:932
+  if (DeclareRVVBuiltins) {
+if (GetRVVBuiltinInfo(*this, R, II, PP)) {
+  return true;

Don’t Use Braces on Simple Single-Statement Bodies.



Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:884
 RVVIntrinsic::getSuffixStr(BasicType Type, int Log2LMUL,
-   const llvm::SmallVector &TypeProfiles) 
{
+   const llvm::ArrayRef &TypeProfiles) {
   SmallVector SuffixStrs;

maybe this changed should be in another NFC patch.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:372
 StringRef Name = R->getValueAsString("Name");
-StringRef SuffixProto = R->getValueAsString("Suffix");
+StringRef Suffix = R->getValueAsString("Suffix");
 StringRef MangledName = R->getValueAsString("MangledName");

maybe all renaming stuffs should be in another NFC patch.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:480
+// They are handled by riscv_vector.h
+if (Name == "vsetvli" || Name == "vsetvlimax")
+  continue;

I feel little tricky to checking the name here. what do you mean they are 
handled by riscv_vector.h?
do you mean they have `vsetvl_macro:RVVHeader`?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:611
+  for (const auto &SR : SemaRecords) {
+// Output *MUST* sync with RVVIntrinsicRecord in SemaRVVLookup.cpp.
+OS << "{"

I'm thinking is it possible to have an unittest or test to make sure we won't 
screw up in the future implementation?
Is it possible to have unittest to test implement really have `sync` correctly?
Is it easy to debug the mismatch problem during implementation without any new 
test added?
We will add a new implementation (really cool speed up and meaningful 
improvement), but unfortunately we don't have any tests, that make me a little 
hesitating...

What do you think?


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[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

2022-05-18 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

2022-05-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

I think we have no consensus in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161,
 and most people disagree the current naming,
maybe we need to have more followup discussion before landing this patch.

For example, maybe `_Float16` should be supported when enable zvh, not zvfh?


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

2022-05-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

please move those tests to `test/CodeGen/RISCV/rvv-intrinsics` and rename them 
without `rvv-` prefix.




Comment at: clang/include/clang/Basic/riscv_vector.td:1511
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {

pcwang-thead wrote:
> craig.topper wrote:
> > Do we need __gnu_inline__ and __artificial__? The only intrinsics headers 
> > that have them in clang are in ppc_wrappers. X86 uses 
> > `__attribute__((__always_inline__, __nodebug__`
> I just made it the same as GCC.
Why do you think making it same as GCC is better than same as other targets in 
clang?




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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

2022-05-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D125765#3526835 , @pcwang-thead 
wrote:

> In D125765#3524456 , @khchen wrote:
>
>> I think we have no consensus in 
>> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161,
>>  and most people disagree the current naming,
>> maybe we need to have more followup discussion before landing this patch.
>
> Thanks for your reminding of previous discussion!
> Should we put this in next sync-up discussion agenda and settle it down? 
> There are already some large code bases based GCC implementation, we should 
> make it stable before it becomes too hard to change.

I think so. But I think maybe we need to raise an issue somewhere (maybe 
riscv-c-api-doc) to gather opinions from community first. (see below)

>> For example, maybe `_Float16` should be supported when enable zvh, not zvfh?
>
> You mean `zfh`? `float16_t` is only used in RVV intrinsics, so I think it is 
> OK to me. And it is the same as generated type aliases in riscv_vector.h(at 
> about line 130):

Yes, sorry for my typo.

I think maybe we need to have more comprehensive consideration about define 
floating type aliases in RISC-V world.
For example, before RISC-V support half floating type, we had posted 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/172 to update the 
spec for half floating-point type.

or like https://github.com/riscv-non-isa/riscv-c-api-doc/pull/25, it's trying 
to define a unified naming rules for all intrinsics.
so I think maybe we also need to have RFC in riscv-c-api-doc to define the 
convention for floating type aliases.

>   #if defined(__riscv_zvfh)
>   typedef __rvv_float16mf4_t vfloat16mf4_t;
>   typedef __rvv_float16mf2_t vfloat16mf2_t;
>   typedef __rvv_float16m1_t vfloat16m1_t;
>   typedef __rvv_float16m2_t vfloat16m2_t;
>   typedef __rvv_float16m4_t vfloat16m4_t;
>   typedef __rvv_float16m8_t vfloat16m8_t;
>   #endif

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[PATCH] D126042: [RISCV][NFC] Remove `*=` operator for LMULType

2022-05-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks.


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2020-12-19 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:194
   HasV = true;
-else if (Feature == "+experimental-zfh")
+  HasRISCVVTypes = true;
+} else if (Feature == "+experimental-zfh")

HasRISCVVTypes is an undefined variable?


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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

2021-05-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 345712.
khchen added a comment.
Herald added a subscriber: vkmr.

Pass -target-abi option into LTO codegenerator base on D102582 
 patch.

please see D102582  for more detal.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.h
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/BareMetal.h
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.h
  clang/test/Driver/lto.c

Index: clang/test/Driver/lto.c
===
--- clang/test/Driver/lto.c
+++ clang/test/Driver/lto.c
@@ -77,3 +77,14 @@
 //
 // CHECK-TUNING-LLDB:   "-plugin-opt=-debugger-tune=lldb"
 // CHECK-NO-TUNING-NOT: "-plugin-opt=-debugger-tune
+
+// Need to pass -target-abi in RISC-V target.
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=lld -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-linux-gnu %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-linux-gnu %s -fuse-ld=lld -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RISCV: "-plugin-opt=target-abi=lp64f"
Index: clang/lib/Driver/ToolChains/RISCVToolchain.h
===
--- clang/lib/Driver/ToolChains/RISCVToolchain.h
+++ clang/lib/Driver/ToolChains/RISCVToolchain.h
@@ -29,6 +29,7 @@
   RuntimeLibType GetDefaultRuntimeLibType() const override;
   UnwindLibType
   GetUnwindLibType(const llvm::opt::ArgList &Args) const override;
+  bool HasNativeLLVMSupport() const override { return true; }
   void
   AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
 llvm::opt::ArgStringList &CC1Args) const override;
Index: clang/lib/Driver/ToolChains/RISCVToolchain.cpp
===
--- clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -7,6 +7,7 @@
 //===--===//
 
 #include "RISCVToolchain.h"
+#include "Arch/RISCV.h"
 #include "CommonArgs.h"
 #include "InputInfo.h"
 #include "clang/Driver/Compilation.h"
@@ -158,6 +159,12 @@
 CmdArgs.push_back("elf32lriscv");
   }
 
+  if (D.isUsingLTO()) {
+assert(!Inputs.empty() && "Must have at least one input.");
+addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0],
+  D.getLTOMode() == LTOK_Thin);
+  }
+
   std::string Linker = getToolChain().GetLinkerPath();
 
   bool WantCRTs =
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -12,6 +12,7 @@
 #include "Arch/M68k.h"
 #include "Arch/Mips.h"
 #include "Arch/PPC.h"
+#include "Arch/RISCV.h"
 #include "Arch/SystemZ.h"
 #include "Arch/VE.h"
 #include "Arch/X86.h"
@@ -629,6 +630,17 @@
 
   addX86AlignBranchArgs(D, Args, CmdArgs, /*IsLTO=*/true);
 
+  // pass more options in specific target
+  switch (ToolChain.getArch()) {
+  default:
+break;
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+riscv::addRISCVTargetABIArgs(ToolChain, Args, CmdArgs);
+break;
+  }
+  }
+
   // Handle remark diagnostics on screen options: '-Rpass-*'.
   renderRpassOptions(Args, CmdArgs);
 
Index: clang/lib/Driver/ToolChains/BareMetal.h
===
--- clang/lib/Driver/ToolChains/BareMetal.h
+++ clang/lib/Driver/ToolChains/BareMetal.h
@@ -40,6 +40,7 @@
 
 public:
   bool useIntegratedAs() const override { return true; }
+  bool HasNativeLLVMSupport() const override { return true; }
   bool isCrossCompiling() const override { return true; }
   bool isPICDefault() const override { return false; }
   bool isPIEDefault() const override { return false; }
Index: clang/lib/Driver/ToolChains/BareMetal.cpp
===
--- clang/lib/Driver/ToolChains/BareMetal.cpp
+++ clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -319,6 +319,13 @@
   CmdArgs.push_back("-o");
   CmdArgs.push_back(Output.getFilename());
 
+  const Driver &D = TC.getDriver();
+  if (D.isUsingLTO()) {
+assert(!Inputs.empty() && "Must have at least one input.");
+addLTOOptions(TC, Args, CmdArgs, Output, Inputs[0],
+

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

2021-05-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D71387#1820995 , @efriedma wrote:

> Okay.  Please let me know if you want me to review anything.

Hi all,
We had encoded the target-abi into module now, but I feel it does not make 
sense to 
support overwrite ABI option and datalayout in TargetMahcine/IR by target-abi 
module flag in IR.

So I think maybe passing the target-abi option by clang driver can make 
anything more simple, the only one limitation is users need to specific `-mabi` 
in below cases at the last command.

  clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o a.o
  clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o b.o
  clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo




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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

2021-05-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen added a comment.

In D71387#2762120 , @jrtc27 wrote:

> In D71387#2762115 , @khchen wrote:
>
>> In D71387#1820995 , @efriedma wrote:
>>
>>> Okay.  Please let me know if you want me to review anything.
>>
>> Hi all,
>> We had encoded the target-abi into module now, but I feel it does not make 
>> sense to 
>> support overwrite ABI option and datalayout in TargetMahcine/IR by 
>> target-abi module flag in IR.
>>
>> So I think maybe passing the target-abi option by clang driver can make 
>> anything more simple, the only one limitation is users need to specific 
>> `-mabi` in below cases at the last command.
>>
>>   clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o 
>> a.o
>>   clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o 
>> b.o
>>   clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo
>
> We should treat a missing `-mabi=` as an implicit 
> `-mabi=whatever-the-default-is` for consistency with non-LTO. So yes, if the 
> default ABI differs from what you've compiled the .o's with, you should have 
> to provide it. This is needed already _anyway_ for multilib toolchains to 
> determine the right library search path, though there are cases currently 
> when you can get away without providing it, at least with Clang.

Hi @jrtc27, do you mean in clang, we need encode an explicitly -target-abi 
string (compute by RISCVABI::computeTargetABI) rather than an empty string in 
IR module?


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[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

2021-05-31 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 348870.
khchen added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Revert to previous revision Diff 347356 and add empty module flag could be 
empty in test.


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Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/module-target-abi-tests.ll
  llvm/test/CodeGen/RISCV/module-target-abi.ll
  llvm/test/CodeGen/RISCV/module-target-abi2.ll

Index: llvm/test/CodeGen/RISCV/module-target-abi2.ll
===
--- llvm/test/CodeGen/RISCV/module-target-abi2.ll
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: llc -mtriple=riscv32 < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=DEFAULT %s
-; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=RV32IF-ILP32 %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=RV32IF-ILP32F %s
-; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s
-
-; RV32IF-ILP32: -target-abi option != target-abi module flag
-
-; FLAGS: Flags: 0x0
-; // this should be "Flags :0x2, single-float ABI", it will be fixed later.
-
-define float @foo(i32 %a) nounwind #0 {
-; DEFAULT: # %bb.0:
-; DEFAULT-NEXT: fcvt.s.w fa0, a0
-; DEFAULT-NEXT: ret
-; RV32IF-ILP32F: # %bb.0:
-; RV32IF-ILP32F: fcvt.s.w fa0, a0
-; RV32IF-ILP32F: ret
-  %conv = sitofp i32 %a to float
-  ret float %conv
-}
-
-attributes #0 = { "target-features"="+f"}
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"target-abi", !"ilp32f"}
Index: llvm/test/CodeGen/RISCV/module-target-abi.ll
===
--- llvm/test/CodeGen/RISCV/module-target-abi.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc -mtriple=riscv32 < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=DEFAULT %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=RV32IF-ILP32 %s
-; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=RV32IF-ILP32F %s
-; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s
-
-; RV32IF-ILP32F: -target-abi option != target-abi module flag
-
-; FLAGS: Flags: 0x0
-
-define float @foo(i32 %a) nounwind #0 {
-; DEFAULT: # %bb.0:
-; DEFAULT: fmv.x.w a0, ft0
-; RV32IF-ILP32: # %bb.0:
-; RV32IF-ILP32: fmv.x.w a0, ft0
-  %conv = sitofp i32 %a to float
-  ret float %conv
-}
-
-attributes #0 = { "target-features"="+f"}
-!llvm.module.flags = !{!0}
-!0 = !{i32 1, !"target-abi", !"ilp32"}
Index: llvm/test/CodeGen/RISCV/module-target-abi-tests.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/module-target-abi-tests.ll
@@ -0,0 +1,35 @@
+; This test is designed to run with different target-abi module flags.
+;
+; Default RV32 ABI is ilp32 for empty target-abi option and module flag, so the result is correct.
+; RUN: cat %s > %t.emptyabi
+; RUN: echo '!0 = !{i32 1, !"target-abi", !""}' >> %t.emptyabi
+; RUN: llc -mtriple=riscv32 < %t.emptyabi -o /dev/null
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %t.emptyabi -o /dev/null
+; RUN: not llc -mtriple=riscv32 -target-abi ilp32f < %t.emptyabi -o /dev/null 2>&1 \
+; RUN:   | FileCheck -check-prefix=DEFAULT-RV32-ILP32F %t.emptyabi
+;
+; Default RV32 ABI is ilp32 which equals target-abi module flag, so the result is correct.
+; RUN: cat %s > %t.ilp32abi
+; RUN: echo '!0 = !{i32 1, !"target-abi", !"ilp32"}' >> %t.ilp32abi
+; RUN: llc -mtriple=riscv32 < %t.ilp32abi -o /dev/null
+; RUN: not llc -mtriple=riscv32 -target-abi ilp32f < %t.ilp32abi -o /dev/null 2>&1 \
+; RUN:   | FileCheck -check-prefix=DEFAULT-RV32-ILP32F %t.ilp32abi
+
+; DEFAULT-RV32-ILP32F: error: Mismatched ABIs. Current ABI is 'ilp32f', but IR target-abi module flag is 'ilp32'.
+
+; Default RV32 ABI is ilp32 which mismatch with target-abi module flag ilp32f.
+; RUN: cat %s > %t.ilp32fabi
+; RUN: echo '!0 = !{i32 1, !"target-abi", !"ilp32f"}' >> %t.ilp32fabi
+; RUN: not llc -mtriple=riscv32 < %t.ilp32fabi -o /dev/null
+; RUN: not llc -mtriple=riscv32 -target-abi ilp32 < %t.ilp32fabi -o /dev/null 2>&1 \
+; RUN:   | FileCheck -check-prefix=RV32-ILP32F %t.ilp32fabi
+
+; RV32-ILP32F: Mismatched ABIs. Current ABI is 'ilp32', but IR target-abi module flag is 'ilp32f'.
+
+define float @foo(i32 %a) nounwind #0 {
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+attributes #0 = { "target-features"="+f"}
+!llvm.module.flags = !{!0}
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-22 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 318423.
khchen added a comment.

1. address @craig.topper's comment.
2. rewrite script as python.

I'm still have no idea to make generating tests mechanism be more elegant...


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-riscv-v-tests.sh
  clang/utils/TestUtils/gen-rvv-tests.py
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-22 Thread Zakk Chen via Phabricator via cfe-commits

khchen marked 7 inline comments as done.
khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:191
+defvar suffix = s_p[1];
+defvar prototype = s_p[2];
+

Paul-C-Anagnostopoulos wrote:
> Well now, thanks for highlighting an inconsistency I did not know about. The 
> documentation says that x[0] produces a list of the 0th element of x, which 
> is why I suggested using !head. But that is true only in certain contexts, 
> such as when x is a defvar. Otherwise it produces the single element. Ouch.
I also thanks for your suggestion. When I was trying to use `!head(s_p[1])` but 
it didn't work, and then I found giving the index is clearer.



Comment at: clang/include/clang/Basic/riscv_vector.td:204
+// op_list in gen-riscv-v-tests.sh.
+#ifdef ALL
+#define VADD

jrtc27 wrote:
> Probably nicer to have a notion of a builtin group and allow the records to 
> be filtered (with the default being to process all of them). Depending on 
> what's still to come you could even use NAME automatically as the group for 
> RVVBinBuiltinSet's RVV(Bin)Builtins given that's always the lowercase version 
> of the macro guarding the definitions at the moment.
@jrtc27 Sorry, I still have no idea to do that, could you please elaborate it 
more?
In our downstream implementation, some builtins inherit `RVVBuiltin` class 
directly. Does your solution still work in this situation?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-22 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 318447.
khchen marked 2 inline comments as done.
khchen added a comment.

1. do not need to manually define new op in gen-rvv-tests.py.
2. do not need to manually add new op define in ALL marco.


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  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  clang/utils/TestUtils/gen-rvv-tests.py
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-25 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 319000.
khchen marked 7 inline comments as done.
khchen added a comment.

1. address @HsiangKai's comments
2. remove test generator to make td simpler.
3. remove MangledSuffix, it should be MangledName


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/riscv-rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-25 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list ELMUL = [0, 1, 2, 3, -1, -2, -3];
+

HsiangKai wrote:
> EMUL according to specification.
Here ELMUL means  exponental LMUL


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-27 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 319488.
khchen marked 21 inline comments as done.
khchen added a comment.

1. address @jrtc27's comments. I really appreciate your help very much.
2. use downstream test generator and move all tests to rvv-intrinsics-generic 
and rvv-intrinsics.


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  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-01-27 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:10
+
+// ASM-NOT: warning
+#include 

jrtc27 wrote:
> Asm checks are discouraged in Clang. If you want to check for Clang warnings, 
> use -verify, and in this case you want `// expected-no-diagnostics`.
RVV is the scalable vector type similar to SVE, so I added this check.
please see https://reviews.llvm.org/D82943.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:48-55
+  bool Float, Bool, Signed;
+  // Constant indices are "int", but have the constant expression.
+  bool Immediate;
+  bool Void;
+  // const qualifier.
+  bool Constant;
+  bool Pointer;

jrtc27 wrote:
> These are poor names; many of them don't sound like bools, and are some of 
> them not mutually exclusive? If so, an enum would be better.
Those variables are used to descript the property of RVVType, I think maybe 
rename as IsXXX could become more clear.
ps. I implement RVVType similar to SveType [[ 
https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/SveEmitter.cpp#L68-L70
 | did ]].
Do you mean only mutually exclusive property should be represented in an enum?



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:308
+return false;
+  if (Float && ElementBitwidth == 8)
+return false;

jrtc27 wrote:
> or 1? Clearer to move this into the switch below IMO.
This checks illegal type float8_t .


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[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

2021-09-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:162
   // For unit stride load with mask
   // Input: (maskedoff, pointer, mask, vl)
   class RISCVUSLoadMask

maybe we could have another NFC patch to update those `argument info` comments.


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[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

2021-09-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.
Herald added a subscriber: achieveartificialintelligence.



Comment at: clang/include/clang/Basic/riscv_vector.td:181
+  // no need to specify the tail policy.
+  bit HasPolicy = true;
+

Add more comment like:
If `HasPolicy`, masked operation have tail policy argument in the last 
position, and append `t` in function name. 
and update the HasVL comment too.

personally, I prefer the naming like `HasTailPolicy`, `HasTail` or 
`HasTailOperand`.



Comment at: clang/include/clang/Basic/riscv_vector.td:2186
+}] in
+def policy : RVVHeader;

It seems like we can rewrite `vsetvli/vsetvl` and ` vsetvlmax` instructions by 
using the `RVVHeader` mechanism?
We only need to have one mechanism to dump header code.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c:14
 //
-vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+vint8mf8_t test_vadd_vv_i8mf8 (vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
   return vadd_vv_i8mf8(op1, op2, vl);

Nit: we don't need to add a space here.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1180
 }
 // If HasVL, append 'z' to last operand
 if (HasVL) {

Nit: update this comment


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[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

2021-09-23 Thread Zakk Chen via Phabricator via cfe-commits

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

LGTM.




Comment at: clang/include/clang/Basic/riscv_vector.td:2186
+}] in
+def policy : RVVHeader;

HsiangKai wrote:
> khchen wrote:
> > It seems like we can rewrite `vsetvli/vsetvl` and ` vsetvlmax` instructions 
> > by using the `RVVHeader` mechanism?
> > We only need to have one mechanism to dump header code.
> Should we create `vsetvli/vsetvlmax` builtins? If we should, we may not be 
> able to use `RVVHeader` for these intrinsics.
oh, you are right. I forget that.
Could you please move class definition in top of this file due to all class 
centralized there.



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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 322297.
khchen marked 3 inline comments as done.
khchen added a comment.

1. address Jim's comment.
2. remove suffix `_vl` according by 
https://github.com/riscv/rvv-intrinsic-doc/pull/64


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  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, "q2Ssq2bq2Ssq2SsS

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 322300.
khchen added a comment.

Rebase


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2021-02-09 Thread Zakk Chen via Phabricator via cfe-commits

khchen added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

Jim wrote:
> Builtins for other extension don't have "__builtin_rvv_" prefix.
maybe we could rename BuiltinsRISCV.def as BuiltinsRVV.def, and other extension 
defines their own .def file?

@Jim do you have any suggestion?


Repository:
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[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

2021-02-16 Thread Zakk Chen via Phabricator via cfe-commits

khchen created this revision.
khchen added reviewers: craig.topper, jrtc27, rogfer01, frasercrmck, HsiangKai, 
evandro.
Herald added subscribers: vkmr, dexonsmith, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96843

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -132,6 +132,9 @@
   bool HasMaskedOffOperand;
   bool HasVL;
   bool HasGeneric;
+  bool HasAutoDef;
+  bool HasManualCodegen;
+  std::string ManualCodegen;
   RVVTypes Types;  // Include output and other input
   std::vector IntrinsicTypes; // Type name in LLVM IR intrinsic suffix
   uint8_t RISCV_Extensions = 0;
@@ -140,8 +143,9 @@
   RVVIntrinsic(StringRef Name, StringRef Suffix, StringRef MangledName,
StringRef IRName, bool HasSideEffects, bool IsMask,
bool HasMaskedOffOperand, bool HasVL, bool HasGeneric,
+   bool HasAutoDef, bool HasManualCodegen, StringRef ManualCodegen,
const RVVTypes &Types,
-   const std::vector &RVVIntrinsicTypes);
+   const std::vector &IntrinsicTypes);
   ~RVVIntrinsic() = default;
 
   StringRef getName() const { return Name; }
@@ -150,6 +154,9 @@
   bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
   bool hasVL() const { return HasVL; }
   bool hasGeneric() const { return HasGeneric; }
+  bool hasAutoDef() const { return HasAutoDef; }
+  bool hasManualCodegen() const { return HasManualCodegen; }
+  StringRef getManualCodegen() const { return ManualCodegen; }
   size_t getNumOperand() const { return Types.size() - 1; }
   // Get output and input types
   ArrayRef getTypes() const { return Types; }
@@ -176,6 +183,7 @@
 class RVVEmitter {
 private:
   RecordKeeper &Records;
+  std::string HeaderCode;
   // Concat BasicType, LMUL and Proto as key
   StringMap LegalTypes;
   StringSet<> IllegalTypes;
@@ -604,11 +612,15 @@
StringRef NewMangledName, StringRef IRName,
bool HasSideEffects, bool IsMask,
bool HasMaskedOffOperand, bool HasVL,
-   bool HasGeneric, const RVVTypes &Types,
+   bool HasGeneric, bool HasAutoDef,
+   bool HasManualCodegen, StringRef ManualCodegen,
+   const RVVTypes &Types,
const std::vector &IntrinsicTypes)
 : IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask),
   HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL),
-  HasGeneric(HasGeneric), Types(Types), IntrinsicTypes(IntrinsicTypes) {
+  HasGeneric(HasGeneric), HasAutoDef(HasAutoDef),
+  HasManualCodegen(HasManualCodegen), ManualCodegen(ManualCodegen.str()),
+  Types(Types), IntrinsicTypes(IntrinsicTypes) {
 
   // Init Name and MangledName
   Name = NewName.str();
@@ -645,8 +657,6 @@
 
   auto getIntrinsicTypesString =
   [this](const std::vector &IntrinsicTypes, raw_ostream &OS) {
-OS << "  ID = Intrinsic::riscv_" + getIRName() + ";\n";
-
 OS << "  IntrinsicTypes = {";
 for (const auto &Idx : IntrinsicTypes) {
   if (Idx == -1)
@@ -663,6 +673,11 @@
 OS << "};\n";
   };
 
+  OS << "  ID = Intrinsic::riscv_" + getIRName() + ";\n";
+  if (hasManualCodegen()) {
+OS << getManualCodegen().str();
+return;
+  }
   if (!IsMask) {
 getIntrinsicTypesString(getIntrinsicTypes(), OS);
 return;
@@ -756,6 +771,11 @@
   std::vector> Defs;
   createRVVIntrinsics(Defs);
 
+  // Dump header
+  if (HeaderCode.size()) {
+OS << HeaderCode;
+  }
+
   // Dump RVV boolean types.
   auto dumpType = [&](auto T) {
 OS << "typedef " << T->clang_builtin_str() << " " << T->type_str() << ";\n";
@@ -875,7 +895,6 @@
 
 void RVVEmitter::createRVVIntrinsics(
 std::vector> &Out) {
-
   std::vector RV = Records.getAllDerivedDefinitions("RVVBuiltin");
   for (auto *R : RV) {
 StringRef Name = R->getValueAsString("Name");
@@ -889,11 +908,19 @@
 bool HasGeneric = R->getValueAsBit("HasGeneric");
 bool HasSideEffects = R->getValueAsBit("HasSideEffects");
 std::vector Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
+bool HasManualCodegen = R->getValueAsBit("HasManualCodegen");
+StringRef Manual

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-17 Thread Zakk Chen via Phabricator via cfe-commits

khchen updated this revision to Diff 324197.
khchen added a comment.

remove float32_t and float64_t to avoid collisions with other project.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-generic/vfadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
  clang/test/CodeGen/RISCV/vadd.c
  clang/test/Headers/riscv-vector-header.c
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h
  llvm/docs/CommandGuide/tblgen.rst

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