[llvm] [clang] [RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (PR #71513)
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/71513
This patch reference ac1ffd3caca12c254e0b8c847aa8ce8e51b6cfbf to suppot a soft
coding way to identify whether a cpu has a feature `unaligned-scalar-mem` by
`RISCVProcessors.td`.
This patch does not provide test case since there is no risc-v cpu support
`unaligned-scalar-mem` in llvm upstream now.
>From 1a6da0d00af17ae17e6c569f12f3e34fbbdf611d Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 7 Nov 2023 18:48:04 +0800
Subject: [PATCH] [RISCV][Clang][TargetParser] Support getting feature
unaligned-scalar-mem from mcpu.
This patch suppots a soft coding way to identify whether a cpu has a feature
"unaligned-scalar-mem" by RISCVProcessors.td.
This patch does not provide test case since there is no cpu
support unaligned-scalar-mem in llvm upstream now.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 3 +++
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 1 +
llvm/lib/TargetParser/RISCVTargetParser.cpp| 12 +---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 9 +++--
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index a05f4b7ea64b487..346fb67ff277e9c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,6 +63,9 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const
Arg *A,
D.Diag(clang::diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Mcpu;
}
+
+ if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
+Features.push_back("+unaligned-scalar-mem");
}
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index a4cb7988eb398b7..5cc8a4a95304537 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -31,6 +31,7 @@ bool parseTuneCPU(StringRef CPU, bool IsRV64);
StringRef getMArchFromMcpu(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
+bool hasFastUnalignedAccess(StringRef CPU);
} // namespace RISCV
} // namespace llvm
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp
b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 30a1023c0673208..85cdd1289a9538f 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -20,7 +20,7 @@ namespace llvm {
namespace RISCV {
enum CPUKind : unsigned {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -28,12 +28,13 @@ enum CPUKind : unsigned {
struct CPUInfo {
StringLiteral Name;
StringLiteral DefaultMarch;
+ bool FastUnalignedAccess;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};
constexpr CPUInfo RISCVCPUInfo[] = {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) \
- {NAME, DEFAULT_MARCH},
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN)
\
+ {NAME, DEFAULT_MARCH, FAST_UNALIGN},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -44,6 +45,11 @@ static const CPUInfo *getCPUInfoByName(StringRef CPU) {
return nullptr;
}
+bool hasFastUnalignedAccess(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ return Info && Info->FastUnalignedAccess;
+}
+
bool parseCPU(StringRef CPU, bool IsRV64) {
const CPUInfo *Info = getCPUInfoByName(CPU);
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 12174fd83f56648..593b5613825ca50 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -49,7 +49,7 @@ static std::string getMArch(const Record &Rec) {
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
- << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
+ << "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -60,9 +60,14 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
+bool FastUnalignedAccess =
+any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
+ return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
+});
+
OS << "PROC(" << Rec->getName() << ", "
<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"" << MArch << "\"})\n";
+ << "{\"" << MArch << "\"}, " << FastUnalig
[llvm] [clang] [RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (PR #71513)
@@ -44,6 +45,11 @@ static const CPUInfo *getCPUInfoByName(StringRef CPU) {
return nullptr;
}
+bool hasFastUnalignedAccess(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ return Info && Info->FastUnalignedAccess;
yetingk wrote:
It's possible that `Info` is `nullptr` here when CPU is not defined in
`RISCVProcessors.td`.
https://github.com/llvm/llvm-project/pull/71513
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[clang] [llvm] [RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (PR #71513)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/71513
>From 1a6da0d00af17ae17e6c569f12f3e34fbbdf611d Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 7 Nov 2023 18:48:04 +0800
Subject: [PATCH 1/2] [RISCV][Clang][TargetParser] Support getting feature
unaligned-scalar-mem from mcpu.
This patch suppots a soft coding way to identify whether a cpu has a feature
"unaligned-scalar-mem" by RISCVProcessors.td.
This patch does not provide test case since there is no cpu
support unaligned-scalar-mem in llvm upstream now.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 3 +++
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 1 +
llvm/lib/TargetParser/RISCVTargetParser.cpp| 12 +---
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 9 +++--
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index a05f4b7ea64b487..346fb67ff277e9c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -63,6 +63,9 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const
Arg *A,
D.Diag(clang::diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Mcpu;
}
+
+ if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
+Features.push_back("+unaligned-scalar-mem");
}
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index a4cb7988eb398b7..5cc8a4a95304537 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -31,6 +31,7 @@ bool parseTuneCPU(StringRef CPU, bool IsRV64);
StringRef getMArchFromMcpu(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64);
+bool hasFastUnalignedAccess(StringRef CPU);
} // namespace RISCV
} // namespace llvm
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp
b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 30a1023c0673208..85cdd1289a9538f 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -20,7 +20,7 @@ namespace llvm {
namespace RISCV {
enum CPUKind : unsigned {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -28,12 +28,13 @@ enum CPUKind : unsigned {
struct CPUInfo {
StringLiteral Name;
StringLiteral DefaultMarch;
+ bool FastUnalignedAccess;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};
constexpr CPUInfo RISCVCPUInfo[] = {
-#define PROC(ENUM, NAME, DEFAULT_MARCH) \
- {NAME, DEFAULT_MARCH},
+#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN)
\
+ {NAME, DEFAULT_MARCH, FAST_UNALIGN},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
@@ -44,6 +45,11 @@ static const CPUInfo *getCPUInfoByName(StringRef CPU) {
return nullptr;
}
+bool hasFastUnalignedAccess(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ return Info && Info->FastUnalignedAccess;
+}
+
bool parseCPU(StringRef CPU, bool IsRV64) {
const CPUInfo *Info = getCPUInfoByName(CPU);
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 12174fd83f56648..593b5613825ca50 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -49,7 +49,7 @@ static std::string getMArch(const Record &Rec) {
static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
- << "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
+ << "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -60,9 +60,14 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
+bool FastUnalignedAccess =
+any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
+ return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
+});
+
OS << "PROC(" << Rec->getName() << ", "
<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
- << "{\"" << MArch << "\"})\n";
+ << "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
>From 231d0f97282e5475f821cb5b0bce6934a42b884b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 7 Nov 2023 21:28:15 +0800
Subject: [PATCH 2/2] Add const qualifier for FastUnalignedAccess
---
llvm/utils/TableGen/RISCVTarget
[clang] [llvm] [RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (PR #71513)
@@ -60,9 +60,14 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
+bool FastUnalignedAccess =
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/71513
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[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [llvm] [RISCV][Clang][TargetParser] Support getting feature unaligned-scalar-mem from mcpu. (PR #71513)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/71513 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Bump zicfilp to 0.4 (PR #75134)
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/75134
Bump to https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0. Actually there
is no functional change here.
>From ec87b87a67acdcb8faedec327e0938476ddb0893 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Dec 2023 11:46:17 +0800
Subject: [PATCH] [RISCV] Bump zicfilp to 0.4
---
clang/test/Preprocessor/riscv-target-features.c | 6 +++---
llvm/docs/RISCVUsage.rst| 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +-
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
llvm/test/MC/RISCV/attribute-arch.s | 4 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 +-
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 6fc921a8c6ee15..35208b2eae8fbd 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1056,12 +1056,12 @@
// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zicfilp0p2 -x c -E -dM %s \
+// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zicfilp0p2 -x c -E -dM %s \
+// RUN: -march=rv64i_zicfilp0p4 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
-// CHECK-ZICFILP-EXT: __riscv_zicfilp 2000{{$}}
+// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 65dd0d83448ed1..842ebf45305952 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -197,7 +197,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
LLVM implements assembler support for the `0.8.0 draft specification
`_.
``experimental-zicfilp``
- LLVM implements the `0.2 draft specification
`__.
+ LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6322748430063c..85c34dd6206307 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -174,7 +174,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
-{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfilp", RISCVExtensionVersion{0, 4}},
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 030ae06af6d282..b34ccb3ff0f937 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -271,7 +271,7 @@
; RV32ZVFBFMIN: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
-; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2"
+; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -360,7 +360,7 @@
; RV64ZVFBFMIN: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
-; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p2"
+; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index aa919f266592f4..3ed48401e43fc8 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -309,5 +309,5 @@
.attribute arch, "rv32i_xcvbi"
# CHECK: attribute 5, "rv32i2p1_xcvbi1p0"
-.attribute arch, "rv32i_zicfilp0p2"
-# CHECK: attribute 5, "rv32i2p1_zicfilp0p2"
+.attribute arch, "rv32i_zicfilp0p4"
+# CHECK: attribute 5, "rv32i2p1_zicfilp0p4"
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp
b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 549964eed55518..3de14907899eb6 100644
--- a/llvm/unittests/Support/RISCVISAIn
[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)
@@ -2429,15 +2455,32 @@ let HasMasked = false, HasVL = false, IRName = "" in {
SupportOverloading = false,
ManualCodegen = [{
{
-assert(isa(ResultType));
-unsigned NF = cast(ResultType)->getNumElements();
-llvm::Value *ReturnTuple = llvm::PoisonValue::get(ResultType);
-for (unsigned I = 0; I < NF; ++I) {
- ReturnTuple = Builder.CreateInsertValue(ReturnTuple, Ops[I], {I});
+if (isa(ResultType)) {
+ unsigned NF = cast(ResultType)->getNumElements();
+ llvm::Value *ReturnTuple = llvm::PoisonValue::get(ResultType);
+ for (unsigned I = 0; I < NF; ++I) {
+ReturnTuple = Builder.CreateInsertValue(ReturnTuple, Ops[I], {I});
+ }
+ return ReturnTuple;
+} else {
yetingk wrote:
Looks like we don't need the else?
https://github.com/llvm/llvm-project/pull/70355
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/70355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vcreate intrinsics for RVV non-tuple types (PR #70355)
https://github.com/yetingk approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/70355 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/6] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -27,6 +27,11 @@ using namespace llvm; +static cl::opt yetingk wrote: The new commit [2830d3e](https://github.com/llvm/llvm-project/pull/68075/commits/2830d3ebf9eb9aae758740e6c38359984b8684b2) adds a new feature to replace this. In the feature, we can add clang option to pass the feature to llvm. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 834bb96261b3e7b65a0bbd8f2651c3d307f1de79 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/6] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 6fc921a8c6ee15..79cf98c2c53b19 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1278,3 +1279,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 65dd0d83448ed1..e3b0c42c0f9855 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -199,6 +199,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6322748430063c..95b326cf559b4d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -175,6 +175,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..90c340ccd4f39e 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCIn
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: Rebase and bump to 0.4 https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][NFC] Use AddTargetFeature to add fast-unaligned-access (PR #74280)
https://github.com/yetingk approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/74280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump zicfilp to 0.4 (PR #75134)
@@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V xventanacondops 1.0 Experimental extensions -zicfilp 0.2 This is a long dummy description +zicfilp 0.4 This is a long dummy description yetingk wrote: It's added by #66715. I guess it is means that we don't check the description. https://github.com/llvm/llvm-project/pull/75134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Bump zicfilp to 0.4 (PR #75134)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/75134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/zicfiss-valid.s| 102 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
15 files changed, 325 insertions(+), 5 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 35208b2eae8fb..a480877dc5f2a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1278,3 +1279,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 842ebf4530595..6bb00c096fde3 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -196,7 +196,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
-``experimental-zicfilp``
+``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 85c34dd620630..c8f1047c2fd47 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -175,6 +175,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
+{"zicfiss", RISCVExtensionVersion{0, 4}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea..8e7ba6a7029c2 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
sta
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: Rebase and ping. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/zicfiss-valid.s| 102 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
15 files changed, 325 insertions(+), 5 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 35208b2eae8fbd..a480877dc5f2a0 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1278,3 +1279,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 842ebf45305952..6bb00c096fde36 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -196,7 +196,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
-``experimental-zicfilp``
+``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 85c34dd6206307..c8f1047c2fd47c 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -175,6 +175,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
+{"zicfiss", RISCVExtensionVersion{0, 4}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..8e7ba6a7029c29 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Succes
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
yetingk wrote:
Use `ArrayRef` or `SmallVectorImpl` instead of `SmallVector`. `SmallVector`
actually use two template parameters.
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
yetingk wrote:
`StringRef` -> `const StringRef &`
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
+
+ addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags);
+ addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags);
+
+ // Collect all flags except march=*
+ for (StringRef Flag : Flags) {
+if (Flag.startswith("!march=") || Flag.startswith("-march="))
+ continue;
+
+NewFlags.push_back(Flag.str());
+ }
+
+ llvm::StringSet<> AllArchExts;
+ // Reconstruct multi-lib list, and break march option into seperated
+ // extension. e.g. march=rv32im -> +i +m
+ for (auto M : RISCVMultilibSet) {
+bool Skip = false;
+
+MultilibBuilder NewMultilib =
+MultilibBuilder(M.gccSuffix(), M.osSuffix(), M.includeSuffix());
+for (StringRef Flag : M.flags()) {
yetingk wrote:
`StringRef` -> `const StringRef &`
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compatible.
+/// Definition of compatible:
+/// - ABI must be the same.
+/// - multi-lib is a subset of current arch, e.g. multi-lib=march=rv32im
+/// is a subset of march=rv32imc.
+/// - march that contains atomic extension can't reuse multi-lib that
+/// doesn't has atomic, vice versa. e.g. multi-lib=march=rv32im and
+/// march=rv32ima are not compatible, because software and hardware
+/// atomic operation can't work together correctly.
+static bool
+RISCVMultilibSelect(const MultilibSet &RISCVMultilibSet, StringRef Arch,
+const Multilib::flags_list &Flags,
+llvm::SmallVector &SelectedMultilibs) {
+ // Try to find the perfect matching multi-lib first.
+ if (RISCVMultilibSet.select(Flags, SelectedMultilibs))
+return true;
+
+ llvm::StringMap FlagSet;
+ Multilib::flags_list NewFlags;
+ std::vector NewMultilibs;
+
+ auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ Arch, /*EnableExperimentalExtension=*/true,
+ /*ExperimentalExtensionVersionCheck=*/false);
+ if (!ParseResult) {
+// Ignore any error here, we assume it will handled in another place.
+consumeError(ParseResult.takeError());
+return false;
+ }
+ auto &ISAInfo = *ParseResult;
+
+ auto CurrentExts = ISAInfo->getExtensions();
yetingk wrote:
Maybe use accurate type instead of `auto`. LLVM only uses `auto` if it makes
the code more readable or easier to maintain.
Ref:
https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable
https://github.com/llvm/llvm-project/pull/73765
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[clang] [RISCV] Implement multi-lib reuse rule for RISC-V bare-metal toolchain (PR #73765)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/73765 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: Ping. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: > It seems that the author of Zimop implementation doesn't have commit access. > @yetingk Would you mind to commit it and rebase your PR on that? It will make > this PR simpler. Sure. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [clang] [flang] [clang-tools-extra] [libc] [llvm] [compiler-rt] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/75182 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 99d35bbe5bab93b4a39a436d1bc9626e68c401ef Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 7 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/zicfiss-valid.s| 102 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
15 files changed, 323 insertions(+), 5 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 2111b3f1c5832b..4229dca8dc3374 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
@@ -1287,3 +1288,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 3125f2d7c9cfdb..1666f8093c7b7b 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
-``experimental-zicfilp``
+``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index e71e96e3417e46..83d7162822ad5a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -194,6 +194,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
+{"zicfiss", RISCVExtensionVersion{0, 4}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"zimop", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..8e7ba6a7029c29 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: Rebase. > It seems that the author of Zimop implementation doesn't have commit access. > @yetingk Would you mind to commit it and rebase your PR on that? It will make > this PR simpler. It's weird that `SSPUSH` and `SSPOPCHK` are not fit into `mop.r` instruction now. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][Clang] Remove default feature -save-restore. (PR #76390)
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/76390
It's unnecessary to defaultly pass feature `-save-restore`, since risc-v
backend defaultly disables save-restore functionality.
>From 97fe56d808f1752ac4b7d26deecabb857e0a4208 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 26 Dec 2023 02:11:30 -0800
Subject: [PATCH] [RISCV][Clang] Remove default feature -save-restore.
It's unnecessary to defaultly pass -save-restore, since riscv backend defaultly
disable save-restore functionality.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++
clang/test/Driver/riscv-default-features.c | 2 --
clang/test/Driver/riscv-features.c | 2 +-
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 25b43cefce6b57..f385a97eca991b 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -169,10 +169,8 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// GCC Compatibility: -mno-save-restore is default, unless -msave-restore is
// specified.
- if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore,
false))
-Features.push_back("+save-restore");
- else
-Features.push_back("-save-restore");
+ AddTargetFeature(Args, Features, options::OPT_msave_restore,
+ options::OPT_mno_save_restore, "save-restore");
// -mno-unaligned-access is default, unless -munaligned-access is specified.
AddTargetFeature(Args, Features, options::OPT_munaligned_access,
diff --git a/clang/test/Driver/riscv-default-features.c
b/clang/test/Driver/riscv-default-features.c
index 6e48f7cc37dcb0..4c3883c1cc1184 100644
--- a/clang/test/Driver/riscv-default-features.c
+++ b/clang/test/Driver/riscv-default-features.c
@@ -2,9 +2,7 @@
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck
%s -check-prefix=RV64
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
-// RV32-SAME: -save-restore
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
-// RV64-SAME: -save-restore
// Dummy function
int foo(void){
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index 716f3f6da57b88..d3700f71aa7e1d 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -24,7 +24,7 @@
// SAVE-RESTORE: "-target-feature" "+save-restore"
// NO-SAVE-RESTORE: "-target-feature" "-save-restore"
-// DEFAULT: "-target-feature" "-save-restore"
+// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 |
FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
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[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
yetingk wrote:
They should use same encoding as some instructions of Zimop, but currently,
there is no `mop.r` could be fitted to `sspush` and `sspopchk`. The 24th bit of
`sspush` is 0 but the 24th bit of all `mop.r` is 1. The 25th bit of `sspopchk`
is 0 but but the 25th bit of all `mop.r` is 1.
ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/mop-r.adoc
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV][Clang] Remove -save-restore from default features. (PR #76390)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/76390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][Clang] Remove -save-restore from default features. (PR #76390)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/76390
>From 71c202c4f16451f7d0d9e17239f95418ea315c0a Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 26 Dec 2023 02:11:30 -0800
Subject: [PATCH] [RISCV][Clang] Remove default feature -save-restore.
It's unnecessary to defaultly pass -save-restore, since riscv backend defaultly
disable save-restore functionality.
---
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 7 ---
clang/test/Driver/riscv-default-features.c | 2 --
clang/test/Driver/riscv-features.c | 2 +-
3 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 25b43cefce6b57..8ae47d1680bd22 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -167,13 +167,6 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("-relax");
}
- // GCC Compatibility: -mno-save-restore is default, unless -msave-restore is
- // specified.
- if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore,
false))
-Features.push_back("+save-restore");
- else
-Features.push_back("-save-restore");
-
// -mno-unaligned-access is default, unless -munaligned-access is specified.
AddTargetFeature(Args, Features, options::OPT_munaligned_access,
options::OPT_mno_unaligned_access, "fast-unaligned-access");
diff --git a/clang/test/Driver/riscv-default-features.c
b/clang/test/Driver/riscv-default-features.c
index 6e48f7cc37dcb0..4c3883c1cc1184 100644
--- a/clang/test/Driver/riscv-default-features.c
+++ b/clang/test/Driver/riscv-default-features.c
@@ -2,9 +2,7 @@
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck
%s -check-prefix=RV64
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
-// RV32-SAME: -save-restore
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
-// RV64-SAME: -save-restore
// Dummy function
int foo(void){
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index 716f3f6da57b88..d3700f71aa7e1d 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -24,7 +24,7 @@
// SAVE-RESTORE: "-target-feature" "+save-restore"
// NO-SAVE-RESTORE: "-target-feature" "-save-restore"
-// DEFAULT: "-target-feature" "-save-restore"
+// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 |
FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
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[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
yetingk wrote:
Sorry, I will give a fix for this.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
@@ -0,0 +1,30 @@
+//===-- RISCVInstrInfoZcmop.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard Compressed
+// May-Be-Operations Extension (Zcmop).
+// This version is still experimental as the 'Zcmop' extension hasn't been
+// ratified yet. It is based on v0.2 of the specification.
+//
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class CMOPInst imm3, string opcodestr>
+: RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {
+ let Inst{6-2} = 0;
+ let Inst{7} = 1;
+ let Inst{10-8} = imm3;
+ let Inst{12-11} = 0;
+}
+
+foreach i = 0...7 in {
+let Predicates = [HasStdExtZcmop, HasStdExtCOrZca] in {
yetingk wrote:
`HasStdExtCOrZca` could be implied by `HasStdExtZcmop`, so I think you don't
need list it.
https://github.com/llvm/llvm-project/pull/76395
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[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
@@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", + "'Zcmop' (Compressed May-Be-Operations)", + [FeatureStdExtZca]>; yetingk wrote: The spec says Zcmop requires Zca. Is this means Zcmop imply Zca? I am not sure with this. https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][Clang] Remove -save-restore from default features. (PR #76390)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/76390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Remove redundant variable Log2LMUL from vset intrinsic. NFC (PR #76422)
https://github.com/yetingk approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/76422 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
https://github.com/yetingk approved this pull request. LGTM. But please wait for @topperc's review. https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 11 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 7 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/zicfiss-valid.s| 102 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
15 files changed, 324 insertions(+), 6 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 43fcb35aba039c..5605a5ed7f29cb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
@@ -1296,3 +1297,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 836a4e9ff08e55..53c56e3fb23018 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
-``experimental-zicfilp``
+``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 14079a0eb07603..052abc4a3a1063 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -196,6 +196,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
+{"zicfiss", RISCVExtensionVersion{0, 4}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"zimop", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 184000b48987e6..d23f60302f42c7 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Suc
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
yetingk wrote: Rebase but I didn't use alias to Zimop and Zcmop ways to achieve this code, since using them will lose some information like `Uses = [SSP]`. https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010,
"ssamoswap.w">;
let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
-
-//===--===/
-// Compress Instruction tablegen backend.
-//===--===//
-
-let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
yetingk wrote:
I remove some CompressPat since I don't know how to test sspush/sspopchk
without transforming to compressed ones.
https://github.com/llvm/llvm-project/pull/66043
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[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 11 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 71
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 7 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/compressed-zicfiss.s | 53 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 17 +++
llvm/test/MC/RISCV/zicfiss-valid.s| 102 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 1 +
15 files changed, 324 insertions(+), 6 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/compressed-zicfiss.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 43fcb35aba039c..5605a5ed7f29cb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -119,6 +119,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
@@ -1296,3 +1297,11 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p4 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 836a4e9ff08e55..53c56e3fb23018 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -212,7 +212,7 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
-``experimental-zicfilp``
+``experimental-zicfilp``, ``experimental-zicfiss``
LLVM implements the `0.4 draft specification
`__.
``experimental-zicond``
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 14079a0eb07603..052abc4a3a1063 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -196,6 +196,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 4}},
+{"zicfiss", RISCVExtensionVersion{0, 4}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"zimop", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 184000b48987e6..d23f60302f42c7 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Suc
[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"zicsr", "zimop", "zcmop"};
yetingk wrote:
I add a patch to not imply Zcmop and enable c.sspush when Zcmop enabled.
https://github.com/llvm/llvm-project/pull/66043
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[llvm] [clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/66043 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/4] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057..6f043ade98f409 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index fee067ee3ad141..8fbe7ed9ca0766 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo@plt
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo@plt
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo@plt
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar@plt
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar@plt
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
yetingk wrote: Rebase and ping. I also update the first comment of the first comment of this pr since the control stack mode is removed and we add new feature `forced-sw-shadow-stack`. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
yetingk wrote: Unwinder could use property `GNU_PROPERTY_RISCV_FEATURE_1_ZICFISS` to know the binary uses `ssp` as the shadow stack register. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417/files https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/5] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057..6f043ade98f409 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index fee067ee3ad141..8fbe7ed9ca0766 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo@plt
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo@plt
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo@plt
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar@plt
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar@plt
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret
[llvm] [clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -57,11 +57,12 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the platform register ``x18`` on AArch64 and
-``x3`` (``gp``) on RISC-V. For simplicity we will refer to this as the
-``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is
-designated as a scratch register. This generally means that any code that may
-run on the same thread as code compiled with ShadowCallStack must either target
+The instrumentation makes use of the platform register ``x18`` on AArch64,
+``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with
+hardware shadow stack, which needs `Zicfiss`_ and ``-mllvm
-riscv-hardware-shadow-stack``.
yetingk wrote:
Modified. The latest patch I add new options `{m,mno}-forced-sw-shadow-stack`
to control feature `forced-sw-shadow-stack`
https://github.com/llvm/llvm-project/pull/68075
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[clang] [llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057..6f043ade98f409 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index fee067ee3ad141..8fbe7ed9ca0766 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo@plt
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo@plt
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo@plt
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar@plt
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar@plt
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret
[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057..6f043ade98f409 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index b41b87aaf4d0d8..1861d2e36227c3 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret i32 %res
@@ -140,6
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -57,11 +57,14 @@ compiled application or the operating system. Integrating the runtime into the operating system should be preferred since otherwise all thread creation and destruction would need to be intercepted by the application. -The instrumentation makes use of the platform register ``x18`` on AArch64 and -``x3`` (``gp``) on RISC-V. For simplicity we will refer to this as the -``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is -designated as a scratch register. This generally means that any code that may -run on the same thread as code compiled with ShadowCallStack must either target +The instrumentation makes use of the platform register ``x18`` on AArch64, +``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with +hardware shadow stack, which needs `Zicfiss`_ and ``-mno-forced-sw-shadow-stack`` +(default option). ``-mforced-sw-shadow-stack`` make risc-v backend generate +software shadow stack with `Zicfiss`_ when shadow stack enabled. yetingk wrote: Done. Thank you for your suggestion. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -151,9 +155,10 @@ Usage To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag to both compile and link command lines. On aarch64, you also need to pass -``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3`` -(``gp``) is always reserved. It is, however, important to disable GP relaxation -in the linker. This can be done with the ``--no-relax-gp`` flag in GNU ld. +``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V with software +shadow stack, ``x3`` (``gp``) is always reserved. It is, however, important to +disable GP relaxation in the linker. This can be done with the ``--no-relax-gp`` +flag in GNU ld. yetingk wrote: Done. Thank you for your suggestion. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 939352b - [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.
Author: Yeting Kuo
Date: 2022-07-05T11:02:44+08:00
New Revision: 939352b6ec31db4e8defe07856868438fbc5340d
URL:
https://github.com/llvm/llvm-project/commit/939352b6ec31db4e8defe07856868438fbc5340d
DIFF:
https://github.com/llvm/llvm-project/commit/939352b6ec31db4e8defe07856868438fbc5340d.diff
LOG: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.
RVV C intrinsics use pointers to scalar for base address and their corresponding
IR intrinsics but use pointers to vector. It makes some vector load intrinsics
need specific ManualCodegen and MaskedManualCodegen to just add bitcast for
transforming to IR.
For simplifying riscv_vector.td, the patch make RISCVEmitter detect pointer
operands and bitcast them.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D129043
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index b11b780ec1f7d..d96020ee40d02 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@ class IsFloat {
}
let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
- IntrinsicTypes = {ResultType, Ops[1]->getType()};
- Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
- // Move mask to right before vl.
- std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- IntrinsicTypes = {ResultType, Ops[3]->getType()};
- Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
- class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+ class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
let Name = "vlm_v";
let IRName = "vlm";
let HasMasked = false;
@@ -601,26 +591,15 @@ let HasUnMaskedOverloaded = false,
}
let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
- IntrinsicTypes = {ResultType, Ops[1]->getType()};
- Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
- Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
- // Move mask to right before vl.
- std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
- IntrinsicTypes = {ResultType, Ops[3]->getType()};
- Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
multiclass RVVVLEBuiltin types> {
let Name = NAME # "_v",
IRName = "vle",
MaskedIRName ="vle_mask" in {
foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
if !not(IsFloat.val) then {
- def : RVVBuiltin<"Uv", "UvPCUe", type>;
+ def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
}
}
}
@@ -685,61 +664,39 @@ multiclass RVVVLSEBuiltin types> {
IRName = "vlse",
MaskedIRName ="vlse_mask",
HasUnMaskedOverloaded = false,
- ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
- }],
- MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(),
TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
- }] in {
+ UnMaskedPolicy = HasPassthruOperand in {
foreach type = types in {
- def : RVVBuiltin<"v", "vPCet", type>;
+ def : RVVOutBuiltin<"v", "vPCet", type>;
if !not(IsFloat.val) then {
-def : RVVBuiltin<"Uv", "UvPCUet", type>;
+def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
}
}
}
}
multiclass RVVIndexedLoad {
- let ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
- }],
- MaskedManualCodegen = [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(),
TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()};
-Ops[1]
[clang] [llvm] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
yetingk wrote: > Will > [riscv-non-isa/riscv-elf-psabi-doc#417](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417) > be implemented in a separate patch? Sure. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/9] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057..6f043ade98f409 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index b41b87aaf4d0d8..1861d2e36227c3 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret i32 %res
@@ -140,6
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -106,9 +112,15 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+ STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/68075
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -51,9 +51,15 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+ STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/68075
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[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
yetingk wrote: Ping. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/8] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss.
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +-
llvm/test/CodeGen/RISCV/shadowcallstack.ll | 130 +++
2 files changed, 142 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 8dfea6d3862057c..6f043ade98f4093 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -51,9 +51,14 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Store return address to shadow call stack
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
+BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
+return;
+ }
+
Register SCSPReg = RISCVABI::getSCSPReg();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
int64_t SlotSize = STI.getXLen() / 8;
// Load return address from shadow call stack
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
index b41b87aaf4d0d88..1861d2e36227c33 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll
@@ -3,6 +3,10 @@
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV32-ZICFISS
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfiss -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s --check-prefix=RV64-ZICFISS
define void @f1() shadowcallstack {
; RV32-LABEL: f1:
@@ -12,6 +16,14 @@ define void @f1() shadowcallstack {
; RV64-LABEL: f1:
; RV64: # %bb.0:
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f1:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f1:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:ret
ret void
}
@@ -25,6 +37,14 @@ define void @f2() shadowcallstack {
; RV64-LABEL: f2:
; RV64: # %bb.0:
; RV64-NEXT:tail foo
+;
+; RV32-ZICFISS-LABEL: f2:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:tail foo
+;
+; RV64-ZICFISS-LABEL: f2:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:tail foo
tail call void @foo()
ret void
}
@@ -65,6 +85,32 @@ define i32 @f3() shadowcallstack {
; RV64-NEXT:addi gp, gp, -8
; RV64-NEXT:.cfi_restore gp
; RV64-NEXT:ret
+;
+; RV32-ZICFISS-LABEL: f3:
+; RV32-ZICFISS: # %bb.0:
+; RV32-ZICFISS-NEXT:sspush ra
+; RV32-ZICFISS-NEXT:addi sp, sp, -16
+; RV32-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV32-ZICFISS-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-ZICFISS-NEXT:.cfi_offset ra, -4
+; RV32-ZICFISS-NEXT:call bar
+; RV32-ZICFISS-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-ZICFISS-NEXT:addi sp, sp, 16
+; RV32-ZICFISS-NEXT:sspopchk ra
+; RV32-ZICFISS-NEXT:ret
+;
+; RV64-ZICFISS-LABEL: f3:
+; RV64-ZICFISS: # %bb.0:
+; RV64-ZICFISS-NEXT:sspush ra
+; RV64-ZICFISS-NEXT:addi sp, sp, -16
+; RV64-ZICFISS-NEXT:.cfi_def_cfa_offset 16
+; RV64-ZICFISS-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-ZICFISS-NEXT:.cfi_offset ra, -8
+; RV64-ZICFISS-NEXT:call bar
+; RV64-ZICFISS-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-ZICFISS-NEXT:addi sp, sp, 16
+; RV64-ZICFISS-NEXT:sspopchk ra
+; RV64-ZICFISS-NEXT:ret
%res = call i32 @bar()
%res1 = add i32 %res, 1
ret i32 %res
@@ -14
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating the runtime into the operating system should be preferred since otherwise all thread creation and destruction would need to be intercepted by the application. -The instrumentation makes use of the platform register ``x18`` on AArch64 and -``x3`` (``gp``) on RISC-V. For simplicity we will refer to this as the -``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is -designated as a scratch register. This generally means that any code that may -run on the same thread as code compiled with ShadowCallStack must either target +The instrumentation makes use of the platform register ``x18`` on AArch64, +``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with +hardware shadow stack, which needs `Zicfiss`_ and ``-mno-forced-sw-shadow-stack`` +(default option). Note that with ``Zicfiss``_ the RISC-V backend will default to +the hardware based shadow call stack. Users can force the RISC-V backend to +generate the software shadow call stack with ``Zicfiss``_ by passing +``-mforced-sw-shadow-stack``. +For simplicity we will refer to this as the ``SCSReg``. On some platforms, +``SCSReg`` is reserved, and on others, it is designated as a scratch register. +This generally means that any code that may run on the same thread as code compiled with ShadowCallStack must either target yetingk wrote: Done. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -151,9 +157,12 @@ Usage To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag to both compile and link command lines. On aarch64, you also need to pass -``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3`` -(``gp``) is always reserved. It is, however, important to disable GP relaxation -in the linker. This can be done with the ``--no-relax-gp`` flag in GNU ld. +``-ffixed-x18`` unless your target already reserves ``x18``. No additional flags +need to be passed on RISC-V because the software based shadow stack uses ``x3`` (``gp``), +which is always reserved, and the hardware based shadow call stack uses a dedicated register, ``ssp``. yetingk wrote: Done. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
@@ -27,6 +27,11 @@ // DEFAULT-NOT: "-target-feature" "-save-restore" // DEFAULT-NOT: "-target-feature" "+save-restore" +// RUN: %clang --target=riscv32-unknown-elf -### %s -mforced-sw-shadow-stack 2>&1 | FileCheck %s -check-prefix=FORCE-SW-SCS yetingk wrote: Done. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add Zicfiss support to the shadow call stack implementation. (PR #68075)
yetingk wrote: Ping. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32]
in
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+
+let Predicates = [HasStdExtZicfiss, IsRV64] in
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
+ "$rs1"> {
+ let rd = 0;
+ let imm12 = 0b10011100;
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32]
in
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+
+let Predicates = [HasStdExtZicfiss, IsRV64] in
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
+ "$rs1"> {
+ let rd = 0;
+ let imm12 = 0b10011100;
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
+ let imm12 = 0b10011100;
+ let rs1 = 0b0;
+ let rd = 0b0;
+}
+
+def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp",
"$rd"> {
+ let imm12 = 0b10011101;
+ let rs1 = 0b0;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def SSPUSH : RVInstR<0b101, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+ "sspush", "$rs2"> {
+ let rd = 0b0;
+ let rs1 = 0b0;
+}
+} // Predicates = [HasStdExtZicfiss]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def C_SSPUSH : RVC_SSInst<0b1, GPRX1, "c.sspush">;
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32]
in
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+
+let Predicates = [HasStdExtZicfiss, IsRV64] in
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
+ "$rs1"> {
+ let rd = 0;
+ let imm12 = 0b10011100;
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
+ let imm12 = 0b10011100;
+ let rs1 = 0b0;
+ let rd = 0b0;
+}
+
+def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp",
"$rd"> {
+ let imm12 = 0b10011101;
+ let rs1 = 0b0;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def SSPUSH : RVInstR<0b101, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+ "sspush", "$rs2"> {
+ let rd = 0b0;
+ let rs1 = 0b0;
+}
+} // Predicates = [HasStdExtZicfiss]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def C_SSPUSH : RVC_SSInst<0b1, GPRX1, "c.sspush">;
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
+} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtC], Uses = [SSP], Defs = [SSP],
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// Instruction class templates
+//===--===//
+
+class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> :
+ RVInst16<(outs), (ins reg_class:$rs1), opcodestr, "$rs1", [],
InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1val;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+ let DecoderMethod = "decodeCSSPushPopchk";
+}
+
+//===--===//
+// Instructions
+//===--===//
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let DecoderNamespace = "RV32Zicfiss", Predicates = [HasStdExtZicfiss, IsRV32]
in
+def SSLW : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "sslw",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+
+let Predicates = [HasStdExtZicfiss, IsRV64] in
+def SSLD : RVInstI<0b100, OPC_SYSTEM, (outs GPRX1X5:$rd), (ins), "ssld",
"$rd"> {
+ let rs1 = 0;
+ let imm12 = 0b10011100;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Predicates = [HasStdExtZicfiss] in {
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1),
"sspopchk",
+ "$rs1"> {
+ let rd = 0;
+ let imm12 = 0b10011100;
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSINCP : RVInstI<0b100, OPC_SYSTEM, (outs), (ins), "ssincp", ""> {
+ let imm12 = 0b10011100;
+ let rs1 = 0b0;
+ let rd = 0b0;
+}
+
+def SSRDP : RVInstI<0b100, OPC_SYSTEM, (outs GPRNoX0:$rd), (ins), "ssrdp",
"$rd"> {
+ let imm12 = 0b10011101;
+ let rs1 = 0b0;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def SSPUSH : RVInstR<0b101, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2),
+ "sspush", "$rs2"> {
+ let rd = 0b0;
+ let rs1 = 0b0;
+}
+} // Predicates = [HasStdExtZicfiss]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtCOrZca] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def C_SSPUSH : RVC_SSInst<0b1, GPRX1, "c.sspush">;
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
in
+def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">;
+} // Predicates = [HasStdExtZicfiss, HasStdExtCOrZca]
+
+let Predicates = [HasStdExtZicfiss, HasStdExtC], Uses = [SSP], Defs = [SSP],
+hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def C_SSINCP : RVInst16<(outs), (ins), "c.ssincp", "", [], InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = 0b00011;
+ let Inst{6-2} = 0b0;
+ let Inst{1-0} = 0b01;
+}
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
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[clang] [RISCV] Support predefined marcro __riscv_misaligned_[fast,avoid]. (PR #65756)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/65756 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support predefined macro __riscv_misaligned_[fast,avoid]. (PR #65756)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/65756
>From 391711dd39e2ee2e8f5d3dac6f466649238f4517 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Fri, 8 Sep 2023 19:46:03 +0800
Subject: [PATCH 1/2] [RISCV] Support predefined marcro
__riscv_misaligned_{fast,avoid}.
RISC-V C API introduce predefined macro to achieve hints about unaligned
accesses [0].
This defines __riscv_misaligned_fast when using -mno-strict-align, otherwise,
defines __riscv_misaligned_avoid.
Note: This ignores __riscv_misaligned_slow which is also defined by spec.
The spec has mentioned https://github.com/riscv-non-isa/riscv-c-api-doc/pull/40
[0]: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/40
---
clang/lib/Basic/Targets/RISCV.cpp | 7 +++
clang/lib/Basic/Targets/RISCV.h | 3 +++
clang/test/Preprocessor/riscv-target-features.c | 12
3 files changed, 22 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index d55ab76395c8271..119d905be57249b 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -204,6 +204,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (VScale && VScale->first && VScale->first == VScale->second)
Builder.defineMacro("__riscv_v_fixed_vlen",
Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock));
+
+ if (FastUnalignedAccess)
+Builder.defineMacro("__riscv_misaligned_fast");
+ else
+Builder.defineMacro("__riscv_misaligned_avoid");
}
static constexpr Builtin::Info BuiltinInfo[] = {
@@ -322,6 +327,8 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
HasLegalHalfType = true;
+ FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem");
+
return true;
}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 6be0e49ca2f5525..e5424d318401fb0 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -29,6 +29,9 @@ class RISCVTargetInfo : public TargetInfo {
std::string ABI, CPU;
std::unique_ptr ISAInfo;
+private:
+ bool FastUnalignedAccess;
+
public:
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple) {
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 4dd83cfa0620b90..4db1cf7a49272fb 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1228,3 +1228,15 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-AVOID
+// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-AVOID
+// CHECK-MISALIGNED-AVOID: __riscv_misaligned_avoid 1
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
+// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
+// CHECK-MISALIGNED-FAST: __riscv_misaligned_fast 1
>From 04600b863b4726163f22df2fb077b103108ce585 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Thu, 26 Oct 2023 14:14:37 +0800
Subject: [PATCH 2/2] [RISCV] Refine riscv-target-features.c
---
clang/test/Preprocessor/riscv-target-features.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 4db1cf7a49272fb..58ba4e595dbed92 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1235,8 +1235,8 @@
// RUN: -o - | FileCheck %s --check-prefix=CHECK-MISALIGNED-AVOID
// CHECK-MISALIGNED-AVOID: __riscv_misaligned_avoid 1
-// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
-// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
-// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
-// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
+// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
+// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
+// RUN: %clang --target=riscv64-unknown-linux-gnu -march=rv64i -E -dM %s \
+// RUN: -munaligned-access -o - | FileCheck %s
--check-prefix=CHECK-MISALIGNED-FAST
// CHECK-MISALIGNED-FAST: _
[clang] [RISCV] Support predefined macro __riscv_misaligned_[fast,avoid]. (PR #65756)
@@ -1228,3 +1228,15 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/65756
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[clang] [RISCV] Support predefined macro __riscv_misaligned_[fast,avoid]. (PR #65756)
https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/65756 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] bd9c0f0 - [RISCV] Add Svpbmt extension support.
Author: Yeting Kuo
Date: 2022-12-28T23:57:54-08:00
New Revision: bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
URL:
https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
DIFF:
https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3.diff
LOG: [RISCV] Add Svpbmt extension support.
Spec of Svpbmt:
https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140692
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 7791703cbbe46..c514ad889d0b2 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -41,6 +41,7 @@
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svpbmt
// CHECK-NOT: __riscv_svinval
// CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd
@@ -436,6 +437,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// CHECK-SVNAPOT-EXT: __riscv_svnapot 100{{$}}
+// RUN: %clang -target riscv32 -march=rv32isvpbmt -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvpbmt -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
+// CHECK-SVPBMT-EXT: __riscv_svpbmt 100{{$}}
+
// RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 522988f8b053d..70e86ed6a30c8 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -53,6 +53,7 @@ on support follow.
``F``Supported
``M``Supported
``Svinval`` Assembly Support
+ ``Svpbmt`` Supported
``V``Supported
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index c94d426fb72e3..eb851a7e1ed92 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -413,6 +413,10 @@ def FeatureStdExtSvnapot
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
+def FeatureStdExtSvpbmt
+: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
+ "'Svpbmt' (Page-Based Memory Types)">;
+
def FeatureStdExtSvinval
: SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
"'Svinval' (Fine-Grained Address-Translation Cache
Invalidation)">;
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 328749b12845c..4f56d1aa00955 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zicbop", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
+{"svpbmt", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index dda8d65350658..4acb1ad2fc3bb 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck
--check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck
--check-prefix=RV32ZICBOP %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck
--check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck
--check-prefix=RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck
--check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck
--check-prefix=RV32ZCA %s
@@ -77,6 +78,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck
--check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck
--check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck
--check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck
--check-prefix=RV64SVPBMT %s
; RUN: llc -mtriple=riscv64 -matt
[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/66043
___
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/68075
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to shadow stack.
This patch only supports the shadow stack mode.
[spec]:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#push-to-and-pop-from-the-shadow-stack
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
yetingk wrote: This is based on #66762. https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 818e76d - [RISCV] Add MC layer support for Zicfilp.
Author: Yeting Kuo
Date: 2023-08-16T08:52:51+08:00
New Revision: 818e76d6f2dd90362e71e84f492c167958ef3257
URL:
https://github.com/llvm/llvm-project/commit/818e76d6f2dd90362e71e84f492c167958ef3257
DIFF:
https://github.com/llvm/llvm-project/commit/818e76d6f2dd90362e71e84f492c167958ef3257.diff
LOG: [RISCV] Add MC layer support for Zicfilp.
This adds extension Zicfilp and support pseudo instruction lpad.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D157362
Added:
llvm/test/MC/RISCV/zicfilp-invalid.s
llvm/test/MC/RISCV/zicfilp-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 3f91d0d99f2290..c2722fb34a1a72 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -71,6 +71,7 @@
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zicfilp {{.*$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
// RUN: -o - | FileCheck %s
@@ -774,3 +775,11 @@
// RUN: -march=rv64i_zacas1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zicfilp0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zicfilp0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
+// CHECK-ZICFILP-EXT: __riscv_zicfilp 2000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 4d319fc6dc6a4b..51d5c2922c6dde 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -202,6 +202,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification
`_.
+``experimental-zicfilp``
+ LLVM implements the `0.2 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 007166a518cb3c..594b8ba28424dd 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -168,6 +168,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfa", RISCVExtensionVersion{0, 2}},
{"zfbfmin", RISCVExtensionVersion{0, 8}},
+{"zicfilp", RISCVExtensionVersion{0, 2}},
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6ef7f1078aa3ca..ce1d3f53ffe6f7 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -660,6 +660,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isUImm6() const { return IsUImm<6>(); }
bool isUImm7() const { return IsUImm<7>(); }
bool isUImm8() const { return IsUImm<8>(); }
+ bool isUImm20() const { return IsUImm<20>(); }
bool isUImm8GE32() const {
int64_t Imm;
@@ -1478,6 +1479,8 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc,
unsigned &Opcode,
"operand must be a symbol with "
"%hi/%tprel_hi modifier or an integer in
"
"the range");
+ case Match_InvalidUImm20:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 20) - 1);
case Match_InvalidUImm20AUIPC:
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 20) - 1,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fb33b1e3a6d5f1..8cce9dc4742b92 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -648,6 +648,13 @@ def FeatureStdExtZvksg
"other extensions: Zvks and Zvkg.",
[FeatureStdExtZ
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
yetingk wrote: > The patch basically changes the ShadowCallStack back-end to emit an > sspush/sspopchk instead of the usual SCS push/pop, which seems like a > reasonable approach to me. However, it would be helpful to mention the > dependency on `-fsanitize=shadow-call-stack` in the commit message, and you > should also update [the > documentation](https://clang.llvm.org/docs/ShadowCallStack.html). Thank you for the reminder. I have updated the document by [e32fc6c](https://github.com/llvm/llvm-project/pull/68075/commits/e32fc6cfb624d2ee90dc5b1da2c2e505f9920ac0). https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
yetingk wrote:
> Do we need an enable other than just the feature being in -march? The shadow
> stack pointer has to be set up when the application starts.
The hardware shadow stack support in this pr needs
`-fsanitize=shadow-call-stack` now.
https://github.com/llvm/llvm-project/pull/68075
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
yetingk wrote:
> What if we're compiling for a platform that only uses the software shadow
> stack and does not support the hardware shadow stack even if the CPU supports
> it?
I think I should move the implement out of `emitSCSEpilogue`/`emitSCSPrologue`
and enable hardware shadow stack by a new option, like
`-riscv-hardware-shadow-stack`?
https://github.com/llvm/llvm-project/pull/68075
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/5] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instructions in Zicfiss extension. Zicfiss extension is
to support shadow stack for control flow integrity.
Differential Revision: https://reviews.llvm.org/D152793
---
.../test/Preprocessor/riscv-target-features.c | 9 ++
llvm/docs/RISCVUsage.rst | 3 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 29 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 7 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +-
.../lib/Target/RISCV/RISCVInstrInfoZicfiss.td | 86 +++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td| 9 ++
llvm/test/MC/RISCV/attribute-arch.s | 3 +
llvm/test/MC/RISCV/rv32zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv32zicfiss-valid.s| 103 ++
llvm/test/MC/RISCV/rv64zicfiss-invalid.s | 20
llvm/test/MC/RISCV/rv64zicfiss-valid.s| 103 ++
14 files changed, 402 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zicfiss-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zicfiss-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 02b67dc7944ba88..163eba81543ee5b 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -113,6 +113,7 @@
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
+// CHECK-NOT: __riscv_zicfiss {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
@@ -1220,3 +1221,11 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfiss0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
+// CHECK-ZICFISS-EXT: __riscv_zicfiss 3000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d12d58738c609a..31c55def0a7694a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -205,6 +205,9 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicfilp``
LLVM implements the `0.2 draft specification
`__.
+``experimental-zicfiss``
+ LLVM implements the `0.3.1 draft specification
`__.
+
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a02c9842e85839a..c414b62c5f31092 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -170,6 +170,8 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zfbfmin", RISCVExtensionVersion{0, 8}},
{"zicfilp", RISCVExtensionVersion{0, 2}},
+{"zicfiss", RISCVExtensionVersion{0, 3}},
+
{"zicond", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d561d90d3088c1a..14b3122f0fecbdb 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
yetingk wrote:
> I think we could enable hardware shadow stack by a new option, like
> -riscv-hardware-shadow-stack?
There is a commit
https://github.com/llvm/llvm-project/pull/68075/commits/45c048c4013ea70e26d20eea6f2c481a7b5eae50
for this
https://github.com/llvm/llvm-project/pull/68075
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
https://github.com/yetingk edited https://github.com/llvm/llvm-project/pull/68075 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support predefined marcro __riscv_misaligned_{fast,avoid}. (PR #65756)
yetingk wrote: Ping. https://github.com/llvm/llvm-project/pull/65756 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
