Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' b22c3da64b gdbstub: Send a reply to the vKill packet. db616b3cea target/arm: Add missing clear_tail calls 240db5cc11 target/arm: Use vector operations for saturation 88a9504b9f target/arm: Split out FPSCR.QC to a vector field e9d315769a target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] 78d9813d1a target/arm: Split out flags setting from vfp compares 7addfd4039 target/arm: Fix arm_cpu_dump_state vs FPSCR 930c986b1b target/arm: Fix vfp_gdb_get/set_reg vs FPSCR a034668e9b target/arm: Remove neon min/max helpers bb77972f61 target/arm: Use tcg integer min/max primitives for neon d4bcca5e91 target/arm: Use vector minmax expanders for aarch32 58c8e77c23 target/arm: Use vector minmax expanders for aarch64 c75e5516d5 target/arm: Rely on optimization within tcg_gen_gvec_or a3de217232 hw/arm/armsse: Fix miswiring of expansion IRQs de29583b07 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 8fb1a5bac0 MAINTAINERS: Remove Peter Crosthwaite from various entries acc80866a5 arm: Allow system registers for KVM guests to be changed by QEMU code 05e851518b linux-user/elfload: enable HWCAP_CPUID for AArch64 1e0293cc26 target/arm: expose remaining CPUID registers as RAZ 0443bd4878 target/arm: expose MPIDR_EL1 to userspace ad0122bcbf target/arm: expose CPUID registers to userspace 1cc2635c69 target/arm: relax permission checks for HWCAP_CPUID registers 592467aa65 target/arm: Restructure disas_fp_int_conv af2989a366 target/arm: Force result size into dp after operation f26458f2fa target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be ee1b241af9 target/arm: Implement HACR_EL2 845bd274c6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit 845bd274c624 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit ee1b241af96d (target/arm: Implement HACR_EL2) 3/27 Checking commit f26458f2fa7e (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit af2989a36697 (target/arm: Force result size into dp after operation) 5/27 Checking commit 592467aa6590 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 1cc2635c6964 (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit ad0122bcbfcd (target/arm: expose CPUID registers to userspace) 8/27 Checking commit 0443bd48780a (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit 1e0293cc26e0 (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit 05e851518be8 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit acc80866a588 (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit 8fb1a5bac0c0 (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit de29583b07df (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit a3de21723286 (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit c75e5516d5de (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 58c8e77c23c0 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit d4bcca5e9117 (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit bb77972f618b (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit a034668e9b5d (target/arm: Remove neon min/max helpers) 20/27 Checking commit 930c986b1b61 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 7addfd403939 (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit 78d9813d1a48 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit e9d315769a5c (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit 88a9504b9f85 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit 240db5cc1112 (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit db616b3ceae7 (target/arm: Add missing clear_tail calls) 27/27 Checking commit b22c3da64b53 (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
