Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu t [tag update] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' 1fcacb9030 gdbstub: Send a reply to the vKill packet. facc45d026 target/arm: Add missing clear_tail calls fe47ae1ac0 target/arm: Use vector operations for saturation beb3acb4a2 target/arm: Split out FPSCR.QC to a vector field 8187800f5f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] 61090e681c target/arm: Split out flags setting from vfp compares 753b33ef6a target/arm: Fix arm_cpu_dump_state vs FPSCR a6ac25752e target/arm: Fix vfp_gdb_get/set_reg vs FPSCR 70ae1e5a51 target/arm: Remove neon min/max helpers aa0575d473 target/arm: Use tcg integer min/max primitives for neon 00d818ea1d target/arm: Use vector minmax expanders for aarch32 7e76c6e511 target/arm: Use vector minmax expanders for aarch64 26a48e84cf target/arm: Rely on optimization within tcg_gen_gvec_or 17db94065e hw/arm/armsse: Fix miswiring of expansion IRQs f5b0afe7e5 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 dafa19baa4 MAINTAINERS: Remove Peter Crosthwaite from various entries 3e133e44a1 arm: Allow system registers for KVM guests to be changed by QEMU code f2cfb74b09 linux-user/elfload: enable HWCAP_CPUID for AArch64 ca0002eebc target/arm: expose remaining CPUID registers as RAZ 4b893eb212 target/arm: expose MPIDR_EL1 to userspace 9d5e5704e0 target/arm: expose CPUID registers to userspace b1a6cabff4 target/arm: relax permission checks for HWCAP_CPUID registers a252f2d3f9 target/arm: Restructure disas_fp_int_conv 095c71f97a target/arm: Force result size into dp after operation dbb6c95fc5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be 0319bf2a5a target/arm: Implement HACR_EL2 1e79fd6dec target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit 1e79fd6decaa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit 0319bf2a5af5 (target/arm: Implement HACR_EL2) 3/27 Checking commit dbb6c95fc539 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit 095c71f97a76 (target/arm: Force result size into dp after operation) 5/27 Checking commit a252f2d3f9f7 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit b1a6cabff49f (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit 9d5e5704e04b (target/arm: expose CPUID registers to userspace) 8/27 Checking commit 4b893eb21287 (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit ca0002eebc43 (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit f2cfb74b0916 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 3e133e44a1b8 (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit dafa19baa45b (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit f5b0afe7e5f6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit 17db94065e2f (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit 26a48e84cf68 (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 7e76c6e5113a (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit 00d818ea1d8a (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit aa0575d473a8 (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit 70ae1e5a51e0 (target/arm: Remove neon min/max helpers) 20/27 Checking commit a6ac25752edc (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 753b33ef6a9f (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit 61090e681cb1 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit 8187800f5f67 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit beb3acb4a272 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit fe47ae1ac0ef (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit facc45d0266a (target/arm: Add missing clear_tail calls) 27/27 Checking commit 1fcacb90300d (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
