Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu t [tag update] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' 73ac529141 gdbstub: Send a reply to the vKill packet. 4b247465c1 target/arm: Add missing clear_tail calls 89be70063e target/arm: Use vector operations for saturation e77ac93de2 target/arm: Split out FPSCR.QC to a vector field c22864f292 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] ff918185bd target/arm: Split out flags setting from vfp compares 11f919937a target/arm: Fix arm_cpu_dump_state vs FPSCR dd99a43005 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR e004fed65e target/arm: Remove neon min/max helpers 8f4545ca63 target/arm: Use tcg integer min/max primitives for neon ab9ebe5a3d target/arm: Use vector minmax expanders for aarch32 72d6045bf1 target/arm: Use vector minmax expanders for aarch64 a7e7d40b7b target/arm: Rely on optimization within tcg_gen_gvec_or 990b62b71d hw/arm/armsse: Fix miswiring of expansion IRQs ea4ce7fac8 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 40282cba68 MAINTAINERS: Remove Peter Crosthwaite from various entries 530553605c arm: Allow system registers for KVM guests to be changed by QEMU code cf4f6b485e linux-user/elfload: enable HWCAP_CPUID for AArch64 c38db4cedc target/arm: expose remaining CPUID registers as RAZ bc98ce37e8 target/arm: expose MPIDR_EL1 to userspace 5b3cbe3a2c target/arm: expose CPUID registers to userspace 3cbbe863dd target/arm: relax permission checks for HWCAP_CPUID registers 9054387819 target/arm: Restructure disas_fp_int_conv 72c798db01 target/arm: Force result size into dp after operation 9b1c8067b0 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be c2f33f799d target/arm: Implement HACR_EL2 5d803e29a6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit 5d803e29a608 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit c2f33f799db1 (target/arm: Implement HACR_EL2) 3/27 Checking commit 9b1c8067b058 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit 72c798db0186 (target/arm: Force result size into dp after operation) 5/27 Checking commit 905438781946 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 3cbbe863ddc4 (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit 5b3cbe3a2cb1 (target/arm: expose CPUID registers to userspace) 8/27 Checking commit bc98ce37e86a (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit c38db4cedc34 (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit cf4f6b485e7d (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 530553605c71 (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit 40282cba687a (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit ea4ce7fac88a (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit 990b62b71dd4 (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit a7e7d40b7b98 (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 72d6045bf127 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit ab9ebe5a3d40 (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit 8f4545ca6381 (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit e004fed65e8b (target/arm: Remove neon min/max helpers) 20/27 Checking commit dd99a430053c (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 11f919937a85 (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit ff918185bd76 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit c22864f2927f (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit e77ac93de248 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit 89be70063eac (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit 4b247465c1e0 (target/arm: Add missing clear_tail calls) 27/27 Checking commit 73ac529141df (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
