Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu t [tag update] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' acf570635b gdbstub: Send a reply to the vKill packet. cfd8f55e95 target/arm: Add missing clear_tail calls 259bb867b8 target/arm: Use vector operations for saturation 6b04328ef7 target/arm: Split out FPSCR.QC to a vector field de7292c5a8 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] 999ec7bd2d target/arm: Split out flags setting from vfp compares 20031f4d81 target/arm: Fix arm_cpu_dump_state vs FPSCR 7f2ccbe2fc target/arm: Fix vfp_gdb_get/set_reg vs FPSCR 3652215042 target/arm: Remove neon min/max helpers a2f9ae9d00 target/arm: Use tcg integer min/max primitives for neon 2a97616341 target/arm: Use vector minmax expanders for aarch32 0cbd8e1d73 target/arm: Use vector minmax expanders for aarch64 60dbc19c09 target/arm: Rely on optimization within tcg_gen_gvec_or 612e1a64f9 hw/arm/armsse: Fix miswiring of expansion IRQs 79033fb4ff hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 b0353d09d8 MAINTAINERS: Remove Peter Crosthwaite from various entries 1f2b02b2cd arm: Allow system registers for KVM guests to be changed by QEMU code 06a5266ef7 linux-user/elfload: enable HWCAP_CPUID for AArch64 60eef60261 target/arm: expose remaining CPUID registers as RAZ dfe0bf2269 target/arm: expose MPIDR_EL1 to userspace 027c283aef target/arm: expose CPUID registers to userspace 641715c1a5 target/arm: relax permission checks for HWCAP_CPUID registers 0fce875951 target/arm: Restructure disas_fp_int_conv 743fa18abf target/arm: Force result size into dp after operation 93602e2cd3 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be 59084e04e5 target/arm: Implement HACR_EL2 7150f17967 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit 7150f17967aa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit 59084e04e5d6 (target/arm: Implement HACR_EL2) 3/27 Checking commit 93602e2cd3f5 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit 743fa18abfb8 (target/arm: Force result size into dp after operation) 5/27 Checking commit 0fce87595153 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 641715c1a53d (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit 027c283aef86 (target/arm: expose CPUID registers to userspace) 8/27 Checking commit dfe0bf226921 (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit 60eef60261b6 (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit 06a5266ef754 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 1f2b02b2cd7a (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit b0353d09d85b (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit 79033fb4ff44 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit 612e1a64f9e9 (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit 60dbc19c096f (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 0cbd8e1d7369 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit 2a976163412b (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit a2f9ae9d00dc (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit 3652215042cd (target/arm: Remove neon min/max helpers) 20/27 Checking commit 7f2ccbe2fc14 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 20031f4d81ce (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit 999ec7bd2d81 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit de7292c5a8d3 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit 6b04328ef702 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit 259bb867b8c7 (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit cfd8f55e9599 (target/arm: Add missing clear_tail calls) 27/27 Checking commit acf570635b34 (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
