Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu t [tag update] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' 6035ee1d0b gdbstub: Send a reply to the vKill packet. 6abc10e3cf target/arm: Add missing clear_tail calls 3b446a483a target/arm: Use vector operations for saturation 5ae122d95f target/arm: Split out FPSCR.QC to a vector field dcf4734824 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] 93f672cd3e target/arm: Split out flags setting from vfp compares a4923fb2a2 target/arm: Fix arm_cpu_dump_state vs FPSCR 59b60a009c target/arm: Fix vfp_gdb_get/set_reg vs FPSCR 2d72031bc3 target/arm: Remove neon min/max helpers 0dc3071aa6 target/arm: Use tcg integer min/max primitives for neon 12249be0d4 target/arm: Use vector minmax expanders for aarch32 210b86c4d0 target/arm: Use vector minmax expanders for aarch64 ec442a042e target/arm: Rely on optimization within tcg_gen_gvec_or ec303c3244 hw/arm/armsse: Fix miswiring of expansion IRQs 8a6530ed11 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 375c511d5e MAINTAINERS: Remove Peter Crosthwaite from various entries 2a062aa5d8 arm: Allow system registers for KVM guests to be changed by QEMU code fde061cf2a linux-user/elfload: enable HWCAP_CPUID for AArch64 345f47dc8b target/arm: expose remaining CPUID registers as RAZ b96e5b9001 target/arm: expose MPIDR_EL1 to userspace 06c582053e target/arm: expose CPUID registers to userspace 8aeda9f436 target/arm: relax permission checks for HWCAP_CPUID registers e3ceeef98a target/arm: Restructure disas_fp_int_conv 49958fb0df target/arm: Force result size into dp after operation fc1287b91f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be fa29b1076a target/arm: Implement HACR_EL2 95fcc314e3 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit 95fcc314e34d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit fa29b1076a08 (target/arm: Implement HACR_EL2) 3/27 Checking commit fc1287b91f25 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit 49958fb0df5d (target/arm: Force result size into dp after operation) 5/27 Checking commit e3ceeef98ab2 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 8aeda9f436db (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit 06c582053ec6 (target/arm: expose CPUID registers to userspace) 8/27 Checking commit b96e5b900130 (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit 345f47dc8bac (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit fde061cf2ae3 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 2a062aa5d85a (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit 375c511d5ef0 (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit 8a6530ed11d6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit ec303c324426 (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit ec442a042e1b (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 210b86c4d0a5 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit 12249be0d48f (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit 0dc3071aa652 (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit 2d72031bc357 (target/arm: Remove neon min/max helpers) 20/27 Checking commit 59b60a009c37 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit a4923fb2a25e (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit 93f672cd3e36 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit dcf4734824cb (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit 5ae122d95fb6 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit 3b446a483a40 (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit 6abc10e3cfa5 (target/arm: Add missing clear_tail calls) 27/27 Checking commit 6035ee1d0be8 (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
