Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu 0d3e41d5ef..0266c739ab master -> master * [new tag] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' c903d16f69 gdbstub: Send a reply to the vKill packet. f41dbe7001 target/arm: Add missing clear_tail calls a3938310ec target/arm: Use vector operations for saturation 9b991d3ba4 target/arm: Split out FPSCR.QC to a vector field 268d1b9f5d target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] f1d08942ee target/arm: Split out flags setting from vfp compares 91e223f0f1 target/arm: Fix arm_cpu_dump_state vs FPSCR 764d782f4d target/arm: Fix vfp_gdb_get/set_reg vs FPSCR 47067fd53b target/arm: Remove neon min/max helpers 05f1c9b528 target/arm: Use tcg integer min/max primitives for neon 1f1543646b target/arm: Use vector minmax expanders for aarch32 06f27fadf8 target/arm: Use vector minmax expanders for aarch64 fc2e976aa2 target/arm: Rely on optimization within tcg_gen_gvec_or 1afa20583c hw/arm/armsse: Fix miswiring of expansion IRQs fdd25e9b24 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 1827768bd1 MAINTAINERS: Remove Peter Crosthwaite from various entries 991af7236f arm: Allow system registers for KVM guests to be changed by QEMU code a9636655dd linux-user/elfload: enable HWCAP_CPUID for AArch64 5112145efe target/arm: expose remaining CPUID registers as RAZ 12fd99a4ba target/arm: expose MPIDR_EL1 to userspace aff8cd32cc target/arm: expose CPUID registers to userspace 1ef1d6626a target/arm: relax permission checks for HWCAP_CPUID registers ba75efcd06 target/arm: Restructure disas_fp_int_conv a1f51e1111 target/arm: Force result size into dp after operation 50d5b46b34 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be 847bae167b target/arm: Implement HACR_EL2 db698e8bd5 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit db698e8bd558 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit 847bae167b24 (target/arm: Implement HACR_EL2) 3/27 Checking commit 50d5b46b34cb (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit a1f51e11115a (target/arm: Force result size into dp after operation) 5/27 Checking commit ba75efcd0632 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 1ef1d6626a73 (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit aff8cd32cc4a (target/arm: expose CPUID registers to userspace) 8/27 Checking commit 12fd99a4baf8 (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit 5112145efe84 (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit a9636655dd31 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 991af7236fdf (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit 1827768bd11f (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit fdd25e9b24c8 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit 1afa20583c29 (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit fc2e976aa28e (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit 06f27fadf836 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit 1f1543646b22 (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit 05f1c9b5283e (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit 47067fd53bc4 (target/arm: Remove neon min/max helpers) 20/27 Checking commit 764d782f4d64 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 91e223f0f1af (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit f1d08942ee79 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit 268d1b9f5d61 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit 9b991d3ba404 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit a3938310ec20 (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit f41dbe70013f (target/arm: Add missing clear_tail calls) 27/27 Checking commit c903d16f6993 (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to [email protected]
