On 17/11/2025 12:53, Konrad Dybcio wrote:
On 11/16/25 3:30 PM, Bryan O'Donoghue wrote:
On 14/11/2025 15:59, Luca Weiss wrote:
On Fri Nov 14, 2025 at 4:51 PM CET, Bryan O'Donoghue wrote:
On 14/11/2025 11:15, Luca Weiss wrote:
Add bindings, driver and dts to support the Camera Subsystem on the
SM6350 SoC.
These patches were tested on a Fairphone 4 smartphone with WIP sensor
drivers (Sony IMX576 and IMX582), the camera pipeline works properly as
far as I can tell.
Though when stopping the camera stream, the following clock warning
appears in dmesg. But it does not interfere with any functionality,
starting and stopping the stream works and debugcc is showing 426.4 MHz
while the clock is on, and 'off' while it's off.
Any suggestion how to fix this, is appreciated.
[ 5738.590980] ------------[ cut here ]------------
[ 5738.591009] gcc_camera_axi_clk status stuck at 'on'
[ 5738.591049] WARNING: CPU: 0 PID: 6918 at drivers/clk/qcom/clk-branch.c:87
clk_branch_toggle+0x170/0x190
Do you have a full and complete kernel tree we could look at here ?
Sure, this branch has everything in:
https://github.com/sm6350-mainline/linux/tree/sm6350-6.17.y/
For further refence, at least two other people have tested this branch
in postmarketOS, nothing particularly exciting to report from there,
apart from that the sdm-skin-thermal thermal zone (thermistor right next
to SoC) is currently configured with 55 degC as critical trip, which is
quickly achieved when starting a video recording, but that's not really
an issue with camss, but will need some tweaking regardless.
https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/7281
diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index a4d6dff9d0f7f..229629ef82809 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -908,9 +908,7 @@ static struct clk_branch gcc_camera_ahb_clk = {
static struct clk_branch gcc_camera_axi_clk = {
.halt_reg = 0x17018,
- .halt_check = BRANCH_HALT,
- .hwcg_reg = 0x17018,
- .hwcg_bit = 1,
No reason to drop the hwcg description
+ .halt_check = BRANCH_VOTED,
It'd be useful to explain why we should ignore the hw feedback in this case
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
Konrad
vfe170 is what we have on sdm845
So I'm just asking Luca to try the sdm845 method of waggling this clock
since what we have doesn't work.
---
bod
