[Bug target/117878] RISC-V: ICE when build spec17 526.blender_r with -O3 -march=rv64gcv_zvl256b

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117878

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21

commit r15-5917-gfb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21
Author: Pan Li <pan2...@intel.com>
Date:   Wed Dec 4 13:53:52 2024 +0800

    RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

    According to the the initial analysis of PR117878, the ice comes from
    the out-of-range operand access for recog_data.operand[].  Thus, add
    one assert here to expose this explicitly.

            PR target/117878

    gcc/ChangeLog:

            * config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
            out of range access.
            (nonvlmax_avl_type_p): Ditto.

    Signed-off-by: Pan Li <pan2...@intel.com>