[Bug target/117878] RISC-V: ICE when build spec17 526.blender_r with -O3 -march=rv64gcv_zvl256b

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117878

--- Comment #10 from Li Pan <pan2.li at intel dot com> ---
(In reply to Robin Dapp from comment #9)
> Should be fixed.

Thanks Robin for fixing this, do we still need to do something like
ix86_pre_reload_split for the risc-v backend? Which avoid the the define expand
to be generated during reload.