[Bug target/117878] RISC-V: ICE when build spec17 526.blender_r with -O3 -march=rv64gcv_zvl256b

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117878

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
(In reply to Robin Dapp from comment #1)
> Is this related to PR117353?  Seems very similar.

Yes, very similar but ice at different pass.

The similar approach like ix86_pre_reload_split can fix the code example in
PR117353.

Does it reasonable to do riscv_pre_reload_split similar as x86 side?