On 11/12/25 10:16 PM, Akhil P Oommen wrote: > On 11/12/2025 4:37 PM, Konrad Dybcio wrote: >> On 11/10/25 5:37 PM, Akhil P Oommen wrote: >>> AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides >>> in Raytracing related workloads. Add support for loading the AQE firmware >>> and initialize the necessary registers. >>> >>> Since AQE engine has dependency on preemption context records, expose >>> Raytracing support to userspace only when preemption is enabled. >>> >>> Signed-off-by: Akhil P Oommen <[email protected]> >>> ---
[...] >>> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >>> @@ -616,6 +616,9 @@ static int hw_init(struct msm_gpu *gpu) >>> goto out; >>> >>> gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); >>> + if (a6xx_gpu->aqe_iova) >>> + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, >>> a6xx_gpu->aqe_iova); >> >> I believe you should also set CP_AQE_APRIV_CNTL per-pipe > > We already configure CP_APRIV_CNTL_PIPE for this. Aaaah right the register I mentioned is separate on gen7 >> Should we also enable AQE1 while at it, to reduce potential backwards >> compatibility issues? Would that require solving the iommu woes? > Yeah, AQE1 is strictly for LPAC workloads. So lets wait for LPAC support > first. Sounds good, thanks Konrad
