On 11/12/2025 4:37 PM, Konrad Dybcio wrote:
> On 11/10/25 5:37 PM, Akhil P Oommen wrote:
>> AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
>> in Raytracing related workloads. Add support for loading the AQE firmware
>> and initialize the necessary registers.
>>
>> Since AQE engine has dependency on preemption context records, expose
>> Raytracing support to userspace only when preemption is enabled.
>>
>> Signed-off-by: Akhil P Oommen <[email protected]>
>> ---
>
> Side question: is the AQE fully functional on any gen7 targets?
> A750?
Yes. Only A750 has it in the A7x family.
>
> [...]
>
>> - adreno_gpu->has_ray_tracing =
>> - !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
>> + /*
>> + * AQE requires preemption records, so disable raytracing
>> + * if preemption is not supported
>> + */
>> + if (gpu->nr_rings == 1)
>
> "nr_rings > 1"?
Ack.
>
>> + adreno_gpu->has_ray_tracing =
>> + !!(fuse_val &
>> A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
>> } else if (adreno_is_a740(adreno_gpu)) {
>> /* Raytracing is always enabled on a740 */
>> adreno_gpu->has_ray_tracing = true;
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> index b507ff4e1756..7921b4a68937 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
>> @@ -58,6 +58,8 @@ struct a6xx_gpu {
>>
>> struct drm_gem_object *sqe_bo;
>> uint64_t sqe_iova;
>> + struct drm_gem_object *aqe_bo;
>> + uint64_t aqe_iova;
>>
>> struct msm_ringbuffer *cur_ring;
>> struct msm_ringbuffer *next_ring;
>> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> index 78dcb9bc3377..2ef69161f1d0 100644
>> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> @@ -616,6 +616,9 @@ static int hw_init(struct msm_gpu *gpu)
>> goto out;
>>
>> gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
>> + if (a6xx_gpu->aqe_iova)
>> + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0,
>> a6xx_gpu->aqe_iova);
>
> I believe you should also set CP_AQE_APRIV_CNTL per-pipe
We already configure CP_APRIV_CNTL_PIPE for this.
>
> Should we also enable AQE1 while at it, to reduce potential backwards
> compatibility issues? Would that require solving the iommu woes?
Yeah, AQE1 is strictly for LPAC workloads. So lets wait for LPAC support
first.
-Akhil
>
> Konrad
