On 11/10/25 5:37 PM, Akhil P Oommen wrote:
> GMU registers are always at a fixed offset from the GPU base address,
> a consistency maintained at least within a given architecture generation.
> In A8x family, the base address of the GMU has changed, but the offsets
> of the gmu registers remain largely the same. To enable reuse of the gmu
> code for A8x chipsets, update the gmu register offsets to be relative
> to the GPU's base address instead of GMU's.
>
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
The resulting diff is a little convoluted, but I think it generally
does the right thing
[...]
> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
> + const char *name, resource_size_t *start)
> +{
> + void __iomem *ret;
> + struct resource *res = platform_get_resource_byname(pdev,
> + IORESOURCE_MEM, name);
> +
> + if (!res) {
> + DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n",
> name);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + ret = ioremap(res->start, resource_size(res));
> + if (!ret) {
> + DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n",
> name);
> + return ERR_PTR(-EINVAL);
> + }
You can use devres here too, devm_platform_get_and_ioremap_resource()
Konrad
