On Wed, Dec 19, 2018 at 1:11 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> Hello Dwaine,
>
> On 18/12/2018 21:30, Molock, Dwaine S. (GSFC-5820) wrote:
> > Hello Sebastian,
> >
> > Do you have the prebuilt bit files or a Git repo of the RISC-V design
> > you used on the Digilent
Hello Dwaine,
On 18/12/2018 21:30, Molock, Dwaine S. (GSFC-5820) wrote:
Hello Sebastian,
Do you have the prebuilt bit files or a Git repo of the RISC-V design
you used on the Digilent Genesys2 development board for RTEMS development?
I’m looking into having someone modifying the E310 design
On 19/12/2018 07:30, Molock, Dwaine S. (GSFC-5820) wrote:
> I’m looking into having someone modifying the E310 design for the Digilent
> Arty
> board to add an external memory controller to access the DDR memory.
I would be interesting in a bitfile for an Arty board that uses the external DDR
con
Hello Sebastian,
Do you have the prebuilt bit files or a Git repo of the RISC-V design you used
on the Digilent Genesys2 development board for RTEMS development?
I’m looking into having someone modifying the E310 design for the Digilent Arty
board to add an external memory controller to access
Hello Dwaine,
On 20/09/2018 18:58, Molock, Dwaine S. (GSFC-5820) wrote:
Hello Sebastian,
Which FPGA development board and RISC-V design did you use for implementation
and testing?
I used a Digilent Genesys2 with a custom SoC with Rocket and BOOM cores.
I tried to port RTEMS to the SiFive E3
Hello Sebastian,
Which FPGA development board and RISC-V design did you use for implementation
and testing?
Did you use the generic or patched version of QEMU?
Thanks,
Dwaine
> On Sep 6, 2018, at 2:31 AM, Sebastian Huber
> wrote:
>
> Hello Alex,
>
> On 06/09/18 08:28, Slide wrote:
>> Hi Se
Hello Alex,
On 06/09/18 08:28, Slide wrote:
Hi Sebastian,
Is your work for both RV32 and RV64?
yes.
Does it support MMU or just PMP?
The BSP performs no low-level initialization and it doesn't touch the
MMU or PMP. It runs in machine mode. To run in another mode more works
is necessary.
Hi Sebastian,
Is your work for both RV32 and RV64? Does it support MMU or just PMP?
Thanks!
Alex
On Wed, Sep 5, 2018, 22:29 Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> Hello Dwaine,
>
> I finished my work to add SMP support to the RISC-V architecture for
> RTEMS. It is now o
Hello Dwaine,
I finished my work to add SMP support to the RISC-V architecture for
RTEMS. It is now on par with the ARM, PowerPC and SPARC ports. I had
only a two hart system for testing (FPGA based). It would be nice to get
some funding to add support for high end targets such as:
https://w
On 12/06/18 21:13, Molock, Dwaine S. (GSFC-5820) wrote:
Hi Sebastian,
Will these ports work on the RISC-V designs from SiFive
(https://www.sifive.com)?
The SoC of your target is based on the SiFive Rocket Chip. I will also
try to get it running on the Qemu targets. Supporting a particular
S
Hi Sebastian,
Will these ports work on the RISC-V designs from SiFive
(https://www.sifive.com)?
Thanks,
Dwaine
On Jun 12, 2018, at 9:25 AM, Sebastian Huber
mailto:sebastian.hu...@embedded-brains.de>>
wrote:
Hello Molock,
we work currently on the SMP support for RISC-V (32-bit and 64-bit). T
Hello Molock,
we work currently on the SMP support for RISC-V (32-bit and 64-bit). The
aim is to run the tests on Qemu and a FPGA Board with two BOOMv2 processors.
https://devel.rtems.org/ticket/3433
My current task is a tool chain update to include a bug fix for:
https://sourceware.org/bugz
Hello,
What is the current state of RTEMS support for the RISC-V processor?
What development boards and designs were used for RTEMS RISC-V development?
Thanks,
Dwaine
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