On Wed, Dec 19, 2018 at 1:11 AM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote:
> Hello Dwaine, > > On 18/12/2018 21:30, Molock, Dwaine S. (GSFC-5820) wrote: > > Hello Sebastian, > > > > Do you have the prebuilt bit files or a Git repo of the RISC-V design > > you used on the Digilent Genesys2 development board for RTEMS > development? > > > > I’m looking into having someone modifying the E310 design for the > > Digilent Arty board to add an external memory controller to access the > > DDR memory. > > sorry, the bit files were provided by our customer and they are not > available to everyone. The bit files itself wouldn't be a problem, but > without documentation you cannot do much with them. > I am not sure if this is suitable but it is open: https://github.com/SpinalHDL/VexRiscv > > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. > > _______________________________________________ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users
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