Hi Sebastian, Will these ports work on the RISC-V designs from SiFive (https://www.sifive.com)?
Thanks, Dwaine On Jun 12, 2018, at 9:25 AM, Sebastian Huber <sebastian.hu...@embedded-brains.de<mailto:sebastian.hu...@embedded-brains.de>> wrote: Hello Molock, we work currently on the SMP support for RISC-V (32-bit and 64-bit). The aim is to run the tests on Qemu and a FPGA Board with two BOOMv2 processors. https://devel.rtems.org/ticket/3433 My current task is a tool chain update to include a bug fix for: https://sourceware.org/bugzilla/show_bug.cgi?id=23244 This fix is necessary to run 64-bit applications in an address rage above 0x80000000 (SDRAM address in some standard chips). We need also specialized GCC multilibs for this. I would like to merge the riscv32 and riscv64 tool chain into one riscv tool chain. There was some discussion necessary with the RISC-V maintainers to achieve this. The overall work should be finished in two to three months. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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