Hello Dwaine,
On 20/09/2018 18:58, Molock, Dwaine S. (GSFC-5820) wrote:
Hello Sebastian,
Which FPGA development board and RISC-V design did you use for implementation
and testing?
I used a Digilent Genesys2 with a custom SoC with Rocket and BOOM cores.
I tried to port RTEMS to the SiFive E310 SoC for the Digilent Arty
board. Unfortunately the SiFive E310 has no external memory controller
and you cannot do much with 16KiB of RAM in RTEMS. See also:
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/qlW16wV7Cek
Did you use the generic or patched version of QEMU?
I used this Qemu without patches:
https://github.com/riscv/riscv-qemu
The upstream Qemu didn't work at the time.
Thanks,
Dwaine
On Sep 6, 2018, at 2:31 AM, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
Hello Alex,
On 06/09/18 08:28, Slide wrote:
Hi Sebastian,
Is your work for both RV32 and RV64?
yes.
Does it support MMU or just PMP?
The BSP performs no low-level initialization and it doesn't touch the MMU or
PMP. It runs in machine mode. To run in another mode more works is necessary.
In general, RTEMS is not a micro kernel, so a MMU could be used only for static
memory maps.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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