On 7/24/25 6:34 AM, Yang Jialong wrote:
The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.
Signed-off-by: Yang Jialong
---
hw/intc/riscv_aplic.c | 6 +-
1 file changed, 5 insert
x27;ll take the opportunity and remove myself from the premises too. Feel
free to reach out with questions about code I did in the past, but at
this moment I'm no longer able to keep up with qemu-ppc activities.
Signed-off-by: Daniel Henrique Barboza
---
MAINTAINERS | 3 ---
1 file changed, 3 deleti
On 7/24/25 4:59 AM, Cédric Le Goater wrote:
Frédéric has moved to other tasks within IBM and no longer does QEMU
development.
Cc: Frédéric Barrat
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git
ot;BXPC"
[...]
Signed-off-by: Sunil V L
Acked-by: Michael S. Tsirkin
---
Reviewed-by: Daniel Henrique Barboza
tests/data/acpi/riscv64/virt/APIC | Bin 116 -> 116 bytes
tests/data/acpi/riscv64/virt/FACP | Bin 276 -> 276 bytes
tests/qtest/bios-tables-test-a
On 7/24/25 8:03 AM, Sunil V L wrote:
Signed-off-by: Sunil V L
Acked-by: Michael S. Tsirkin
---
Reviewed-by: Daniel Henrique Barboza
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests
and MADT to reflect
correct versions.
Update the code comments to reflect ACPI 6.6 version details.
Signed-off-by: Sunil V L
Acked-by: Michael S. Tsirkin
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt-acpi-build.c | 25 ++---
1 file changed, 10 insertions(+), 15
e and tedious to post in the commit msg so I
encourage referring to [1] and [2] to see the new features we're adding
into the QEMU roms.
[1] https://github.com/riscv-software-src/opensbi/releases/tag/v1.6
[2] https://github.com/riscv-software-src/opensbi/releases/tag/v1.7
Signed-off-by: Danie
update the roms for 10.1 to avoid yet another release with
OpenSBI v1.5.1.
Please download the roms from:
https://gitlab.com/danielhb/qemu/-/tree/opensbi_update
Daniel Henrique Barboza (1):
roms/opensbi: Update to v1.7
.../opensbi-riscv32-generic-fw_dynamic.bin| Bin 268312 -> 268752
top level helper and pass the value along.
[1] https://gitlab.com/qemu-project/qemu/-/issues/3020
Suggested-by: Richard Henderson
Fixes: 3157a553ec ("target/riscv: Add Smrnmi mnret instruction")
Closes: https://gitlab.com/qemu-project/qemu/-/issues/3020
Signed-off-by: Daniel Henriq
Hi,
Please disregard this patch. Richard taught me how to fix the unwinding instead.
Thanks,
Daniel
On 7/14/25 9:08 AM, Daniel Henrique Barboza wrote:
There is no guarantee that we'll able to get a proper opcode to put into
mtval for illegal inst exceptions, as demonstrated in [1].
means.
[1] https://gitlab.com/qemu-project/qemu/-/issues/3020
Closes: https://gitlab.com/qemu-project/qemu/-/issues/3020
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu_helper.c | 5 +
target/riscv/op_helper.c | 21 +
2 files changed, 26 insertion
roken while we work on it.
The revert will fix Linux and will give us time to do a proper fix.
[1] https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02525.html
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 323
1 file change
eviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 323
1 file changed, 273 insertions(+), 50 deletions(-)
This recent QEMU patch broke the RISC-V vector optimized ChaCha20 code
in the Linux kernel. I simplified the reproducer to the follow
Ping
It would be nice to have all CSRs for 'info registers' for the next release.
We have one week before the freeze :D
Thanks,
Daniel
On 6/23/25 2:21 PM, Daniel Henrique Barboza wrote:
Hi,
The output of HMP 'info registers', implemented by the cpu_dump_state
callba
: Charalampos Mitrodimas
---
The additional test is appreciated. Thanks!
Reviewed-by: Daniel Henrique Barboza
tests/tcg/riscv64/Makefile.softmmu-target | 4 ++
tests/tcg/riscv64/test-mepc-masking.S | 73 +++
2 files changed, 77 insertions(+)
create mode 100644
mode) were written to MEPC, the bits would not be cleared
correctly, causing incorrect behavior on MRET.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2855
Signed-off-by: Charalampos Mitrodimas
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 8
addisp,sp,-16
0x80958b02: e422 sd s0,8(sp)
(qemu)
Suggested-by: Dr. David Alan Gilbert
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.h| 1 +
target/riscv/riscv-qmp-cmds.c | 148 +++
provides global system control for multi-core
configurations, while the CPC device manages power control for
CPU clusters in RISC-V systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Reviewed-by: Daniel Henrique Barboza
hw
vp_index);
+}
+RISCVCPU *vp = RISCV_CPU(cpu_state);
+vp->env.resetvec = address;
+}
+#endif
+
Reviewed-by: Daniel Henrique Barboza
static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig
*src)
{
#define BOOL_FIELD(x) dest->x |= src->x;
diff --git a/target/riscv/c
On 7/2/25 4:28 AM, Alexandre Ghiti wrote:
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Reviewed-by: Deepak Gupta
Signed-off-by: Alexandre Ghiti
---
Reviewed-by: Daniel Henrique Barboza
Changes in v2:
- Fix riscv32 max config (thanks
On 6/27/25 10:21 AM, Max Chou wrote:
According to the RISC-V instruction set manual, the minimum VLEN needs
to respect the following extensions:
Extension Minimum VLEN
* V 128
* Zve64[d|f|x] 64
* Zve32[f|x] 32
Signed-off-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c
On 6/30/25 9:07 PM, Dr. David Alan Gilbert wrote:
* Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
Hi Daniel,
The RISC-V target has *a lot* of CPU registers, with more registers
being added along the way when new extensions are added. In this world,
'info registers'
On 6/20/25 9:59 PM, liu.xuem...@zte.com.cn wrote:
From: Xuemei Liu
This adds powerdown support by implementing the ACPI GED.
Signed-off-by: Xuemei Liu
Co-authored-by: Björn Töpel
---
Changes in v3:
- Added missing param to virt_is_acpi_enabled
- Fixed failure of bios-tables-test
hw/ri
On 6/30/25 1:00 PM, Philippe Mathieu-Daudé wrote:
Hi Daniel,
On 30/6/25 15:22, Daniel Henrique Barboza wrote:
The RISC-V target has *a lot* of CPU registers, with more registers
being added along the way when new extensions are added. In this world,
'info registers' will throw
us 000a00a0
CPU#1
mstatus 000a00a0
(qemu)
The API is introduced as TARGET_RISCV only.
Cc: Dr. David Alan Gilbert
Cc: Marcel Apfelbaum
Cc: Philippe Mathieu-Daudé
Signed-off-by: Daniel Henrique Barboza
---
hmp-commands-info.hx | 17 +
hw/core/cpu-com
-ying Fu
Signed-off-by: Djordje Todorovic
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/boston-aia.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 6ed5c636cc..34cc0abe79 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Acked-by: Daniel Henrique Barboza
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv/mips.rst | 25 +
docs/system/target-riscv.rst| 1 +
hw/riscv/Kconfig
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z.
Signed-off-by: Chao-ying Fu
Signe
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Acked-by: Daniel Henrique Barboza
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Acked-by: Daniel Henrique Barboza
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++
target/riscv
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/meson.build
On 6/25/25 11:18 AM, Djordje Todorovic wrote:
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
2 files changed, 12 i
---
Reviewed-by: Daniel Henrique Barboza
hw/intc/riscv_aclint.c | 21 +++--
hw/intc/riscv_aplic.c | 10 +++---
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index b0139f03f5..22ac4133d5 100644
--- a/hw
On 6/25/25 4:36 AM, Alexandre Ghiti wrote:
Hi Daniel,
On Sat, Jun 7, 2025 at 7:54 PM Daniel Henrique Barboza
wrote:
On 6/5/25 11:21 AM, Alexandre Ghiti wrote:
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti
Hi Radim,
It seems like this patch is breaking 'make check-functional':
12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT
90.06s killed by signal 15 SIGTERM
Checking the logs I verified that the problem can be reproduced by running the
'spike' machine as follo
riscv_cpu_dump_state() is using the same pattern to print a CSR given
its number. Add a helper to avoid code repetition.
While we're at it fix the identation of the 'flags & CPU_DUMP_VPU'
block.
Signed-off-by: Daniel Henrique Barboza
---
targ
ntify FPU and VPU CSRs
and skip them - they'll be printed in the FPU/VPU blocks later.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 55 --
target/riscv/cpu.h | 2 ++
target/riscv/csr.c | 18 +++
3 files changed, 39
We're missing fflags and frm.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 67e4eda4f9..95d0b88937 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -593,6 +
rs'. The vector CSRs are being handled by
another patch [1].
Patches based on alistair/riscv-to-apply.next.
[1]
https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (3):
target/riscv/cpu: add riscv_dump_csr() helper
target/riscv/cpu
not show VPU regs in info_registers(), so add
CPU_DUMP_VPU to hmp_info_registers(). This will print vector registers
for all RISC-V machines and, as said above, has no impact in other
archs.
Cc: Dr. David Alan Gilbert
Signed-off-by: Daniel Henrique Barboza
---
monitor/hmp-cmds-target.c | 4 ++--
1 file c
-ext.adoc#avl-encoding
According to the spec, the above use cases are reserved, and
"Implementations may set vill in either case."
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2422
Signed-off-by: Vasilis Liaskovitis
---
Reviewed-by: Daniel Henrique Barboza
target/r
Hi,
Seems like this patch doesn't build:
FAILED: libqemu-riscv64-softmmu.a.p/hw_riscv_virt.c.o
(...)
../hw/riscv/virt.c
../hw/riscv/virt.c: In function ‘virt_machine_init’:
../hw/riscv/virt.c:1732:9: error: too few arguments to function
‘virt_is_acpi_enabled’; expected 1, have 0
1732 | if
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z. Ex: Use 4 cores and 2 threads with e
(CCing Michael and Marcel)
For better visibility I suggest copying the maintainers of hw/pci/pci.c when
submitting this patch in the next version:
$ ./scripts/get_maintainer.pl -f hw/pci/pci.c
"Michael S. Tsirkin" (supporter:PCI)
Marcel Apfelbaum (supporter:PCI)
qemu-devel@nongnu.org (open lis
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 +++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
Hi,
Thanks for putting this into a patch. A comment below:
On 6/18/25 4:25 AM, Vasilis Liaskovitis wrote:
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
and rd arguments are x0.
In this case, if the new property is true, only the vill bit will be set.
See
https
On 6/9/25 8:59 AM, Ben Dooks wrote:
On 09/06/2025 12:30, Daniel Henrique Barboza wrote:
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
On 6/9/25 8:47 AM, Ben Dooks wrote:
On 09/06/2025 12:30, Daniel Henrique Barboza wrote:
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
On 6/9/25 8:32 AM, Ben Dooks wrote:
On 09/06/2025 12:24, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC
On 6/9/25 7:40 AM, Ben Dooks wrote:
On 07/06/2025 21:17, Daniel Henrique Barboza wrote:
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by: Ben Dooks
---
v2:
- whitespace fixes
- use g_autofree
On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05e
Hi,
(added Alistair in CC)
I suggest adding the RISC-V maintainer, Alistair, in the CC for the next
posting. It helps in the series visibility.
It would also be nice to add a RISC-V reference in the subject, e.g.
"RISCV: Add initial CVA6 implementation", to help ppl from the common
qemu-devel M
On 6/5/25 11:21 AM, Alexandre Ghiti wrote:
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Add support for IOMMU
- Make svrsw60t59b depend on sv39 (deepak)
Open question: svrsw60t59b in IO
e the definitions. They can be added
back when really necessary.
Signed-off-by: Zhenzhong Duan
---
Reviewed-by: Daniel Henrique Barboza
include/hw/riscv/iommu.h | 6 ++
hw/riscv/riscv-iommu-pci.c | 6 --
hw/riscv/riscv-iommu-sys.c | 6 --
3 files changed, 2 insertions(+), 16 dele
On 6/5/25 6:26 AM, Philippe Mathieu-Daudé wrote:
On 5/6/25 11:00, Daniel Henrique Barboza wrote:
The SBI spec states, for console write byte:
"This is a blocking SBI call and it will only return after writing the
specified byte to the debug console. It will also return, with
SBI_ERR_F
from v1:
- removed the "SBI_EXT_DBCN_CONSOLE_WRITE" bit from the commit msg
- v1 link:
https://lore.kernel.org/qemu-riscv/20250605090012.1268809-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (1):
target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
target/risc
his current
state.
[1]
https://lore.kernel.org/qemu-devel/CAFEAcA_kEndvNtw4EHySXWwQPoGs029yAzZGGBcV=zghaj7...@mail.gmail.com/
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/kvm/kvm-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
target/riscv/cpu.c
Hi,
New version where typos in patch 1 were fixed. No other changes made.
All patches acked.
Changes from v2:
- patch 1
- fixed typos dince -> since and specd -> spec
- v2 link:
https://lore.kernel.org/qemu-riscv/20250604174329.1147549-1-dbarb...@ventanamicro.com/
Daniel Henrique Barb
in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c
ve_u.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
target/riscv/tcg/tcg-cpu.c| 9 +
tests/data/acpi/riscv64/virt/RHCT | Bin 400 -> 406 bytes
3 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu
ll have a 'zero byte written'
semantic [1] - something that we're not ready to deal in this current
state.
[1] https://lore.kernel.org/qemu-devel/
CAFEAcA_kEndvNtw4EHySXWwQPoGs029yAzZGGBcV=zghaj7...@mail.gmail.com/
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/
Hi,
This patch is faling 'make check-functional':
2/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi
ERROR1.25s exit status 1
4/12 qemu:func-quick+func-riscv32 / func-riscv32-riscv_opensbi
ERROR1.39s exit st
It seems like this patch is breaking 'make check-functional':
UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1
RUST_BACKTRACE=1
LD_LIBRARY_PATH=/home/danielhb/work/qemu/build/contrib/plugins:/home/danielhb/work/qemu/build/tests/tcg/plugins
MSAN_OPTIONS=halt_
ognize it
as a RVA22 compliant CPU and we won't force the CPU into the profile
path.
[1]
https://lore.kernel.org/qemu-riscv/87y0usiz22@all.your.base.are.belong.to.us/
Reported-by: Björn Töpel
Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize")
Signed
Please disregard this post - some old patches were left in the dir when I
pressed "send" ...
Thanks,
Daniel
On 6/4/25 2:37 PM, Daniel Henrique Barboza wrote:
Hi,
In this version I fixed the problems caused in bios-table-test qtest by
patches 1 and 2.
A small change was also made
ve_u.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c| 1 +
target/riscv/tcg/tcg-cpu.c| 9 +
tests/data/acpi/riscv64/virt/RHCT | Bin 400 -> 406 bytes
3 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20250529202315.1684198
ventanamicro.com/
Daniel Henrique Barboza (3):
target/riscv/cpu.c: add 'sdtrig' in riscv,isa
target/riscv/cpu.c: add 'ssstrict' to riscv,isa
target/riscv/cpu.c: do better with 'named features' doc
target/riscv/cpu.c| 16 ++--
targe
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20250529202315.1684198-4-db
Use this new helper in the cases where we want a CPU to
be compatible to a certain profile, leaving the user callback to be used
exclusively by users.
Fixes: fba92a92e3 ("target/riscv: add 'rva22u64' CPU")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Revi
in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Message-ID: <20250529202315.1684198
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20250529202315.1684198-4-db
ve_u.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c| 1 +
target/riscv/tcg/tcg-cpu.c| 9 +
tests/data/acpi/riscv64/virt/RHCT | Bin 400 -> 406 bytes
3 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
h 'mmu' and satp_mode if the profile is being enabled.
Suggested-by: Andrew Jones
Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Björn Töpel
Tested-by: Björn Töpel
---
target
ventanamicro.com/
Daniel Henrique Barboza (3):
target/riscv/cpu.c: add 'sdtrig' in riscv,isa
target/riscv/cpu.c: add 'ssstrict' to riscv,isa
target/riscv/cpu.c: do better with 'named features' doc
target/riscv/cpu.c| 16 ++--
targe
Alistair,
This series is breaking bios-table-test on patches 1 and 2 because we're
adding more stuff in the default riscv,isa and I forgot to update the
bios table.
I'll send a v2. Thanks,
Daniel
On 5/29/25 5:23 PM, Daniel Henrique Barboza wrote:
Hi,
These simple patches add t
On 6/4/25 6:38 AM, Philippe Mathieu-Daudé wrote:
(+Marc-André and Paolo who I forgot to Cc first)
On 4/6/25 11:17, Daniel Henrique Barboza wrote:
On 6/4/25 4:32 AM, Philippe Mathieu-Daudé wrote:
On 3/6/25 20:04, Daniel Henrique Barboza wrote:
On 6/3/25 10:19 AM, Philippe Mathieu-Daudé
On 6/4/25 4:32 AM, Philippe Mathieu-Daudé wrote:
On 3/6/25 20:04, Daniel Henrique Barboza wrote:
On 6/3/25 10:19 AM, Philippe Mathieu-Daudé wrote:
Hi Daniel,
(now merged as commit a6b53378f537)
On 25/4/24 17:50, Daniel Henrique Barboza wrote:
SBI defines a Debug Console extension "
On 6/3/25 10:19 AM, Philippe Mathieu-Daudé wrote:
Hi Daniel,
(now merged as commit a6b53378f537)
On 25/4/24 17:50, Daniel Henrique Barboza wrote:
SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.
The
These properties were deprecated in QEMU 8.2, commit 8043effd9b.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 17 -
target/riscv/cpu.h | 1 -
target/riscv/tcg/tcg-cpu.c | 31 +--
3 files changed, 1 insertion(+), 48
We have support for sdtrig for awhile but we are not advertising it. It
is enabled by default via the 'debug' flag. Use the same flag to also
advertise sdtrig.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ris
in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --g
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 14 --
1 file
Hi,
These simple patches add two missing named features in riscv,isa. Third
patch is a doc change I figured was worth doing.
Drew, as far as Server SoC Reference platform goes, we don't have
'sdext'. I guess we'll have to postpone the Server Soc Ref work for now.
Daniel
with all other CPU
types.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fe21e0fb44..4a30cf8444 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2713,7 +2713,6 @@ static void
Add an always present IOMMU platform device for the rvsp-ref board.
The IRQs being used are similar to what the 'virt' board is using: IRQs
36 to 39, one IRQ for queue.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/Kconfig | 1 +
hw/riscv/server_platform_
/server_platform_requirements.adoc
Signed-off-by: Fei Wu
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..70978fd53c 100644
--- a
atch 4 (new):
- add riscv-iommu-sys platform device
- v2 link:
https://lore.kernel.org/qemu-riscv/20240312135222.3187945-1-fei2...@intel.com/
[1]
https://lore.kernel.org/qemu-riscv/20240312135222.3187945-1-fei2...@intel.com/
[2]
https://lore.kernel.org/qemu-riscv/CAHBxVyG186Zo7nAm7o8=vhbtzu+x8ry
compliance
- AIA
- PCIe AHCI
- PCIe NIC
- No virtio device
- No fw_cfg device
- No ACPI table provided
- Only minimal device tree nodes
[1] https://github.com/riscv-non-isa/riscv-server-platform
Signed-off-by: Fei Wu
Signed-off-by: Daniel Henrique Barboza
---
configs/devices/riscv64
-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (3):
target/riscv/tcg: restrict satp_mode changes in cpu_set_profile
target/riscv/tcg: decouple profile enablement from user prop
target/riscv: add profile->present flag
target/riscv/cpu.h| 15
target/riscv/riscv-
h 'mmu' and satp_mode if the profile is being enabled.
Suggested-by: Andrew Jones
Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Reviewed-by: Björn Töpel
Tested-by: Björn Töpel
---
target
ognize it
as a RVA22 compliant CPU and we won't force the CPU into the profile
path.
[1]
https://lore.kernel.org/qemu-riscv/87y0usiz22@all.your.base.are.belong.to.us/
Reported-by: Björn Töpel
Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize")
Signed
Use this new helper in the cases where we want a CPU to
be compatible to a certain profile, leaving the user callback to be used
exclusively by users.
Fixes: fba92a92e3 ("target/riscv: add 'rva22u64' CPU")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Revi
On 5/21/25 12:54 PM, Ben Dooks wrote:
Add a (currently Genesy2 based) CVA6 machine.
Has SPI and UART, the GPIO and Ethernet are currently black-holed
as there is no hardware model for them (lowRISC ethernet and Xilinx
GPIO)
Signed-off-by: Ben Dooks
---
Please remove the blank line at the
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