Re: [PATCH v4 02/11] target/riscv: Add cpu_set_exception_base

[Daniel Henrique Barboza]

On 6/25/25 11:18 AM, Djordje Todorovic wrote:

Add a new function, so we can change reset vector from platforms
during runtime.

Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
  target/riscv/cpu.h       | 4 ++++
  target/riscv/translate.c | 8 ++++++++
  2 files changed, 12 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 229ade9ed9..fba0b0506b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -656,6 +656,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
  target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);

+#ifndef CONFIG_USER_ONLY

+void cpu_set_exception_base(int vp_index, target_ulong address);
+#endif
+
  FIELD(TB_FLAGS, MEM_IDX, 0, 3)
  FIELD(TB_FLAGS, FS, 3, 2)
  /* Vector flags */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d7a6de02df..c3fbae7cfe 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1427,3 +1427,11 @@ void riscv_translate_init(void)
      load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
                               "load_val");
  }
+
+#ifndef CONFIG_USER_ONLY
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+    RISCVCPU *vp = RISCV_CPU(qemu_get_cpu(vp_index));
+    vp->env.resetvec = address;
+}

Sorry to not noticing this in v3 but I don't think this code belongs here. 
There's
no translation related code being done. This code is better placed in
target/riscv/cpu.c.

Also, qemu_get_cpu() can return NULL. Given that you handled the NULL cases in 
patch 1
to support sparse IDs I believe it would be consistent to do the same here for
the sake of future users of this API.


Thanks,

Daniel

+#endif