Hi, (added Alistair in CC)
I suggest adding the RISC-V maintainer, Alistair, in the CC for the next posting. It helps in the series visibility. It would also be nice to add a RISC-V reference in the subject, e.g. "RISCV: Add initial CVA6 implementation", to help ppl from the common qemu-devel ML to quickly identify what the series is about. Thanks, Daniel On 5/27/25 8:24 AM, Ben Dooks wrote:
This implements the CVA6 (the corev_apu from the fpga) model. v2: - fixed whitespace and rebased patches
