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https://github.com/llvm/llvm-project/pull/90582
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jayfoad wrote:
Too late to backport - no more 18.x releases are planned.
https://github.com/llvm/llvm-project/pull/90582
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https://github.com/llvm/llvm-project/pull/95377
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@@ -1735,8 +1737,11 @@ defm : SIBufferAtomicPat<"SIbuffer_atomic_dec", i64,
"BUFFER_ATOMIC_DEC_X2">;
let OtherPredicates = [HasAtomicCSubNoRtnInsts] in
defm : SIBufferAtomicPat<"SIbuffer_atomic_csub", i32, "BUFFER_ATOMIC_CSUB",
["noret"]>;
-let SubtargetPredicate = isGFX12Pl
jayfoad wrote:
This looks like it is affecting codegen even when xnack is disabled? That
should not happen.
https://github.com/llvm/llvm-project/pull/96162
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jayfoad wrote:
> > This looks like it is affecting codegen even when xnack is disabled? That
> > should not happen.
>
> It shouldn't. I put the xnack replay subtarget check before using *_ec
> equivalents. See the code here:
> [65eb443#diff-35f4d1b6c4c17815f6989f86abbac2e606ca760f9d93f501ff50
@@ -967,6 +967,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasLDSFPAtomicAddF32() const { return GFX8Insts; }
bool hasLDSFPAtomicAddF64() const { return GFX90AInsts; }
+ bool hasXnackReplay() const { return GFX8Insts; }
jayfoad wro
@@ -867,13 +867,104 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Returns true if it is a naturally aligned multi-dword load
@@ -867,13 +867,104 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Returns true if it is a naturally aligned multi-dword load
@@ -1701,17 +1732,33 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const
CombineInfo &CI,
return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM;
}
case S_LOAD_IMM:
-switch (Width) {
-default:
- return 0;
-case 2:
- return AMDGPU::S_LOAD_DWORDX2_IMM;
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@@ -167,6 +167,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasAtomicFlatPkAdd16Insts = false;
bool HasAtomicFaddRtnInsts = false;
bool HasAtomicFaddNoRtnInsts = false;
+ bool HasAtomicMemoryAtomicFaddF32DenormalSupport = false;
ja
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@@ -17565,6 +17565,12 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
if (CanCombineFCOPYSIGN_EXTEND_ROUND(N))
return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0));
+ // We only take the sign bit from the sign operand.
+ EVT SignVT = N1.getValueTy
https://github.com/jayfoad approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/97151
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@@ -313,8 +327,7 @@ void
AMDGPUAtomicOptimizerImpl::visitIntrinsicInst(IntrinsicInst &I) {
// value to the atomic calculation. We can only optimize divergent values if
// we have DPP available on our subtarget, and the atomic operation is 32
// bits.
- if (ValDivergent
@@ -230,8 +245,7 @@ void
AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) {
// value to the atomic calculation. We can only optimize divergent values if
// we have DPP available on our subtarget, and the atomic operation is 32
// bits.
- if (ValDivergent
@@ -178,6 +178,21 @@ bool AMDGPUAtomicOptimizerImpl::run(Function &F) {
return Changed;
}
+static bool isOptimizableAtomic(Type *Ty) {
+ switch (Ty->getTypeID()) {
+ case Type::FloatTyID:
+ case Type::DoubleTyID:
+return true;
+ case Type::IntegerTyID: {
+unsigne
jayfoad wrote:
> [AMDGPU] Enable atomic optimizer for divergent i64 and double values
Needs some i64 tests
https://github.com/llvm/llvm-project/pull/96934
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@@ -1700,19 +1725,30 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const
CombineInfo &CI,
case 8:
return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM;
}
- case S_LOAD_IMM:
+ case S_LOAD_IMM: {
+// If XNACK is enabled, use the constrained opcodes when the first l
@@ -1212,8 +1228,17 @@ void SILoadStoreOptimizer::copyToDestRegs(
// Copy to the old destination registers.
const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
- const auto *Dest0 = TII->getNamedOperand(*CI.I, OpName);
- const auto *Dest1 = TII->getNamedOperand(*
@@ -1700,19 +1725,30 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const
CombineInfo &CI,
case 8:
return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM;
}
- case S_LOAD_IMM:
+ case S_LOAD_IMM: {
+// If XNACK is enabled, use the constrained opcodes when the first l
@@ -867,13 +867,61 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Ignore the alignment check if XNACK support is disabled.
+
@@ -867,13 +867,61 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Ignore the alignment check if XNACK support is disabled.
+
@@ -867,13 +867,61 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Ignore the alignment check if XNACK support is disabled.
+
@@ -1700,19 +1722,29 @@ unsigned SILoadStoreOptimizer::getNewOpcode(const
CombineInfo &CI,
case 8:
return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM;
}
- case S_LOAD_IMM:
+ case S_LOAD_IMM: {
+// If XNACK is enabled, use the constrained opcodes when the first l
@@ -658,17 +658,17 @@ define amdgpu_kernel void
@image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
;
; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT:s_load_dwordx8 s[0:7], s[0:1], 0x24
+; GFX1013-NEXT:s_load_dwordx8
@@ -1212,8 +1228,14 @@ void SILoadStoreOptimizer::copyToDestRegs(
// Copy to the old destination registers.
const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
- const auto *Dest0 = TII->getNamedOperand(*CI.I, OpName);
- const auto *Dest1 = TII->getNamedOperand(*
@@ -866,13 +866,61 @@ def SMRDBufferImm : ComplexPattern;
def SMRDBufferImm32 : ComplexPattern;
def SMRDBufferSgprImm : ComplexPattern;
+class SMRDAlignedLoadPat : PatFrag <(ops node:$ptr), (Op
node:$ptr), [{
+ // Ignore the alignment check if XNACK support is disabled.
+
@@ -6,7 +6,7 @@ declare i32 @llvm.amdgcn.global.atomic.csub(ptr addrspace(1),
i32)
; GCN-LABEL: {{^}}global_atomic_csub_rtn:
; PREGFX12: global_atomic_csub v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9:]+}},
s{{\[[0-9]+:[0-9]+\]}} glc
-; GFX12PLUS: global_atomic_sub_clamp_u32 v0, v0, v1
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https://github.com/llvm/llvm-project/pull/96162
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@@ -34,18 +34,17 @@ entry:
}
define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp(
-; SDAG-GFX11-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
-; SDAG-GFX11: ; %bb.0: ; %entry
-; SDAG-GFX11-NEXT:s_load_b128 s[0:3], s[0:1], 0x24
-; SDAG-GFX11-NEXT:s_wait
https://github.com/jayfoad approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/96163
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https://github.com/jayfoad approved this pull request.
Makes sense to me.
For the ordered case I think this would only be profitable if fabs is free
_and_ you don't have integer "test"-style instructions.
https://github.com/llvm/llvm-project/pull/100390
jayfoad wrote:
> Looks worse for x86 without the fabs check. Not sure if this is useful for
> any targets.
Seems unlikely that this would ever be profitable in the ordered case, since
you can implement that with pretty simple integer checks on the exponent field.
(Check that it isn't 0 and is
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LGTM.
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@@ -0,0 +1,366 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii
-passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji
@@ -54,11 +54,11 @@ define i32 @abs_nonpoison(i32 %arg) {
; FAST-NEXT: Cost Model: Found an estimated cost of 80 for instruction:
%V16I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> undef, i1 false)
; FAST-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16
https://github.com/jayfoad approved this pull request.
LGTM for backporting.
https://github.com/llvm/llvm-project/pull/102446
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https://github.com/jayfoad requested changes to this pull request.
> this isn't fixing any known correctness issue
Exactly. I don't think there is any reason to backport this.
https://github.com/llvm/llvm-project/pull/84118
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/90204
Iterator MI can advance in insertWait() but we need original instruction
to set temporal hint. Just move it before handling volatile.
>From b544217fb31ffafb9b072de53a28c71acc169cf8 Mon Sep 17 00:00:00 2001
From:
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Author: Mirko BrkuĊĦanin
Date: 2024-04-26T13:35:58+01:00
New Revision: b544217fb31ffafb9b072de53a28c71acc169cf8
URL:
https://github.com/llvm/llvm-project/commit/b544217fb31ffafb9b072de53a28c71acc169cf8
DIFF:
https://github.com/llvm/llvm-project/commit/b544217fb31ffafb9b072de53a28c71acc169cf8.dif
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/90582
image_msaa_load is actually encoded as a VSAMPLE instruction and
requires the appropriate waitcnt variant.
>From 17b75a9517891d662e677a357713c920bb79c43c Mon Sep 17 00:00:00 2001
From: David Stuttard
Date: Tue,
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jayfoad wrote:
Let's not backport this yet since @pendingchaos has pointed out a problem with
#90201.
https://github.com/llvm/llvm-project/pull/90582
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/90719
Code to determine if a waitcnt is required before a barrier instruction
only
considered S_BARRIER.
gfx12 adds barrier_signal/wait so need to enhance the existing code to
look for
a barrier start (which is just an
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>From 17b75a9517891d662e677a357713c920bb79c43c Mon Sep 17 00:00:00 2001
From: David Stuttard
Date: Tue, 30 Apr 2024 10:41:51 +0100
Subject: [PATCH 1/2] [AMDGPU] Fix gfx12 waitcnt type for image_msaa_load
(#90201
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jayfoad wrote:
> Let's not backport this yet since @pendingchaos has pointed out a problem
> with #90201.
Fixed by #90710 which I have added to this PR.
https://github.com/llvm/llvm-project/pull/90582
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jayfoad wrote:
> Hi @jayfoad (or anyone else). If you would like to add a note about this fix
> in the release notes (completely optional). Please reply to this comment with
> a one or two sentence description of the fix. When you are done, please add
> the release:note label to this PR.
I do
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https://github.com/llvm/llvm-project/pull/91034
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jayfoad wrote:
> Fixed encoding of AMDGPU instructions
I don't think the release notes should say that. It makes it sound like all
encodings were wrong.
https://github.com/llvm/llvm-project/pull/91034
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jayfoad wrote:
> @jayfoad What do you think about merging this PR to the release branch?
LGTM, but it was me that requested it.
https://github.com/llvm/llvm-project/pull/79457
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htt
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This is only valid on targets with architected SGPRs.
>From c5949b09b05e7417d0494b2301781b84d22b95ef Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Thu, 25 Jan 2024 07:48:06 +
Subject: [PATCH] [AMDGPU] New ll
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jayfoad wrote:
@tstellar does this backport PR look OK? I created it with `gh pr create -f -B
release/18.x` and I wasn't sure if I had to edit anything, apart from adding
the release milestone.
https://github.com/llvm/llvm-project/pull/79689
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This just missed the branch creation and is the last piece of functionality
required to get AMDGPU GFX12 support working in the 18.x release.
>From c265c8527285075a58b2425198dbd4cca8b69477 Mon Sep 17 00:00:00
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jayfoad wrote:
> jayfoad closed this by deleting the head repository 3 hours ago
Sorry. Recreated as #79839
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>From c265c8527285075a58b2425198dbd4cca8b69477 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Thu, 25 Jan 2024 07:48:06 +
Subject: [PATCH 1/2] [AMDGPU] New llvm.amdgcn.wave.id intrinsic (#79325)
This is only
@@ -6883,6 +6883,23 @@ bool AMDGPULegalizerInfo::legalizeStackSave(MachineInstr
&MI,
return true;
}
+bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI,
+ MachineIRBuilder &B) const {
+ // With architected SGPRs, waveIDinGroup
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/105549
Fix SIInsertWaitcnts to account for this by adding extra waits to avoid
WAW dependencies.
>From 9a2103df4094af38f59e1adce5414b94672e6d6e Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Wed, 21 Aug 2024 16:23:49 +
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/105550
When a loop contains a VMEM load whose result is only used outside the
loop, do not bother to flush vmcnt in the loop head on GFX12. A wait for
vmcnt will be required inside the loop anyway, because VMEM instruct
jayfoad wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/105549?utm_source=stack-comment-downstack-mergeability-warning";
jayfoad wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/105550?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/jayfoad ready_for_review
https://github.com/llvm/llvm-project/pull/105549
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@@ -953,6 +953,12 @@ def FeatureRequiredExportPriority :
SubtargetFeature<"required-export-priority",
"Export priority must be explicitly manipulated on GFX11.5"
>;
+def FeatureVmemWriteVgprInOrder : SubtargetFeature<"vmem-write-vgpr-in-order",
jayfoad wrot
@@ -1778,11 +1778,12 @@ bool
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
if (IsVGPR) {
// RAW always needs an s_waitcnt. WAW needs an s_waitcnt unless the
// previous write and this write are the same type of VMEM
-
@@ -4371,8 +4375,10 @@ define amdgpu_kernel void
@global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT:buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT:buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT:bu
@@ -754,13 +754,21 @@ define amdgpu_kernel void
@constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GFX12-NEXT:global_load_u16 v6, v8, s[0:1] offset:8
; GFX12-NEXT:global_load_u16 v5, v8, s[0:1] offset:4
; GFX12-NEXT:global_load_u16 v4, v8, s[0:1]
+; GFX12-NEX
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jayfoad wrote:
### Merge activity
* **Aug 22, 6:34 AM EDT**: @jayfoad started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/105549).
https://github.com/llvm/llvm-project/pull/105549
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jayfoad wrote:
I'm not sure if I should have done three different backport requests for the
three commits. It could be confusing if they get squash-and-merged onto the
release branch.
https://github.com/llvm/llvm-project/pull/105808
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/106977
SMUL_LOHI and UMUL_LOHI are different operations because the high part of the
result is different, so it is not OK to optimize the signed version to
MUL_U24/MULHI_U24 or the unsigned version to MUL_I24/MULHI_I2
jayfoad wrote:
This is a backport of #105831.
https://github.com/llvm/llvm-project/pull/106977
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https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/106977
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jayfoad wrote:
> > This sounds sketchy to me. Is it really valid to enter a second call inside
> > another call's CALLSEQ markers, but only if we avoid adding a second nested
> > set of markers? It feels like attacking the symptom of the issue, but not
> > the root cause. (I'm not certain it's
jayfoad wrote:
> Is this PR a fix for a regression or a critical issue?
No, I believe it has been broken for about 3 years (since
d7e03df719464354b20a845b7853be57da863924) but it was only reported to me
recently.
I guess this means it is not appropriate for 19.1.0.
https://github.com/llvm/ll
jayfoad wrote:
> > Is this PR a fix for a regression or a critical issue?
>
> No, I believe it has been broken for about 3 years (since
> [d7e03df](https://github.com/llvm/llvm-project/commit/d7e03df719464354b20a845b7853be57da863924))
> but it was only reported to me recently.
>
> I guess thi
Author: Jay Foad
Date: 2021-01-14T14:02:43Z
New Revision: a1cba5b7a1fb09d2d4082967e2466a5a89ed698a
URL:
https://github.com/llvm/llvm-project/commit/a1cba5b7a1fb09d2d4082967e2466a5a89ed698a
DIFF:
https://github.com/llvm/llvm-project/commit/a1cba5b7a1fb09d2d4082967e2466a5a89ed698a.diff
LOG: [Sel
Author: Jay Foad
Date: 2021-01-14T14:02:43Z
New Revision: 517196e569129677be32d6ebcfa57bac552268a4
URL:
https://github.com/llvm/llvm-project/commit/517196e569129677be32d6ebcfa57bac552268a4
DIFF:
https://github.com/llvm/llvm-project/commit/517196e569129677be32d6ebcfa57bac552268a4.diff
LOG: [Ana
Author: Jay Foad
Date: 2021-01-14T14:02:43Z
New Revision: 90b310f6caf0b356075c70407c338b3c751eebb3
URL:
https://github.com/llvm/llvm-project/commit/90b310f6caf0b356075c70407c338b3c751eebb3
DIFF:
https://github.com/llvm/llvm-project/commit/90b310f6caf0b356075c70407c338b3c751eebb3.diff
LOG: [Sup
Author: Jay Foad
Date: 2021-01-14T18:15:17Z
New Revision: 868da2ea939baf8c71a6dcb878cf6094ede9486e
URL:
https://github.com/llvm/llvm-project/commit/868da2ea939baf8c71a6dcb878cf6094ede9486e
DIFF:
https://github.com/llvm/llvm-project/commit/868da2ea939baf8c71a6dcb878cf6094ede9486e.diff
LOG: [Sel
Author: Jay Foad
Date: 2021-01-19T10:39:56Z
New Revision: 49dce85584e34ee7fb973da9ba617169fd0f103c
URL:
https://github.com/llvm/llvm-project/commit/49dce85584e34ee7fb973da9ba617169fd0f103c
DIFF:
https://github.com/llvm/llvm-project/commit/49dce85584e34ee7fb973da9ba617169fd0f103c.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-01-19T16:36:43Z
New Revision: de2f9423995d52a5457752256815dc54d317c8d1
URL:
https://github.com/llvm/llvm-project/commit/de2f9423995d52a5457752256815dc54d317c8d1
DIFF:
https://github.com/llvm/llvm-project/commit/de2f9423995d52a5457752256815dc54d317c8d1.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-01-19T16:46:47Z
New Revision: 0808c7009a06773e78772c7b74d254fd3572f0ea
URL:
https://github.com/llvm/llvm-project/commit/0808c7009a06773e78772c7b74d254fd3572f0ea
DIFF:
https://github.com/llvm/llvm-project/commit/0808c7009a06773e78772c7b74d254fd3572f0ea.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-01-19T18:47:14Z
New Revision: 18cb7441b69a22565dcc340bac0e58bc9f301439
URL:
https://github.com/llvm/llvm-project/commit/18cb7441b69a22565dcc340bac0e58bc9f301439
DIFF:
https://github.com/llvm/llvm-project/commit/18cb7441b69a22565dcc340bac0e58bc9f301439.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-01-21T15:54:54Z
New Revision: c0b3c5a06451aad4351e35c74ccf2fe5da917a41
URL:
https://github.com/llvm/llvm-project/commit/c0b3c5a06451aad4351e35c74ccf2fe5da917a41
DIFF:
https://github.com/llvm/llvm-project/commit/c0b3c5a06451aad4351e35c74ccf2fe5da917a41.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-01-22T09:48:54Z
New Revision: 14eea6b0ecddfe7d1c68754a8bfb7c21cde82df8
URL:
https://github.com/llvm/llvm-project/commit/14eea6b0ecddfe7d1c68754a8bfb7c21cde82df8
DIFF:
https://github.com/llvm/llvm-project/commit/14eea6b0ecddfe7d1c68754a8bfb7c21cde82df8.diff
LOG: [Leg
Author: Jay Foad
Date: 2021-01-05T11:54:48Z
New Revision: 4e6054a86c0cb0697913007c99b59f3f65c9d04b
URL:
https://github.com/llvm/llvm-project/commit/4e6054a86c0cb0697913007c99b59f3f65c9d04b
DIFF:
https://github.com/llvm/llvm-project/commit/4e6054a86c0cb0697913007c99b59f3f65c9d04b.diff
LOG: [AMD
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