e32m1TU
bb 2:
...
vle
vle
vse
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:16
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]
I thought vsetvli insertion will try to merge them into one for
)
|
bb 3
I don't think we should do this on VSETVL PASS.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:16
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Normalize user vsetvl intrinsics[PR112092]
I thought vsetvli insertion wil
:
__riscv_vsetvl_ratio64
I am no proposing it since it has been used for a long time. Just raise my
concern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:33
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Normalize user vsetvl
OK
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-08 17:09
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Eliminate unused parameter warning.
From: xuli
The parameter orig_fndecl is not used, use anonymous parameters instead.
../.././gcc/gcc/config
Sorry for wrong description on the log:
After this patch, the IR is:
_36 = .SELECT_VL (ivtmp_34, POLY_INT_CST [4, 4]);
_22 = (int) _36;
vect_cst__21 = [vec_duplicate_expr] _22;
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-08 18:53
To: gcc-patches
CC: richard.sandiford
OK。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-09 14:50
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges
From: Pan Li
This patch would like to fine the frm insn emit when we
meet abnormal edge
Bootstrap + regression on X86 passed.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-08 18:53
To: gcc-patches
CC: richard.sandiford; rguenther; kito.cheng; kito.cheng; Juzhe-Zhong
Subject: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV
PR: https
info)
|| !LOOP_VINFO_VECT_FACTOR (loop_vinfo).is_constant ()))
LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo) = true;
}
The problem is SELECT_VL may produce non-VF in non-final iteration, wheras
MIN_EXPR always has VF on non-final iteration.
Maybe add an assertion to assert non-slp if s
Yes. No regression. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 07:56
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec
pattern
On 11/9/23 16:33, Juzhe-Zhong wrote
it can fix the issue.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 07:58
To: 钟居哲; rdapp.gcc; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.
On 11/9/23 15:43, 钟居哲 wrote:
> Hi. Robin.
[ ... ]
You may need a development version of binutils to ge
How to fix it ? I am pretty noob on testing CI.
Can Robin fix that?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:11
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V/testsuite: Fix zvfh tests.
On 11/9/23 18:09, juzhe.zh
I am using --with-arch=rv32gcv --with-abi=ilp32d
I change dg-additional-option into dg-option of all those tests.
Issues gone.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:15
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches; palmer; kito.cheng
Subject: Re: [PATCH] RISC-V
Thanks Jeff. Committed.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-11-10 09:26
To: Juzhe-Zhong; gcc-patches
CC: rguenther
Subject: Re: [PATCH V3] test: Fix FAIL of pr97428.c for RVV
On 11/7/23 08:18, Juzhe-Zhong wrote:
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/pr974
No test?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-10 16:14
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add HFmode for l/ll round and rint autovec
From: Pan Li
The internal-fn has support the FLOATN already. This patch
would like
Hi, Richard.
>> For nested_in_vect_loop we never have LOOP_VINFO_USING_SELECT_VL_P?
Could you give me an example of nested loop ?
For now, I can't produce a case.
Thanks a lot for the comments, I will try to refactor as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Da
ep_vectype,
> + LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo) ? &si : NULL);
again this makes the flow hard to follow. I suppose refactoring this
overall to
if (nested_in_vect_loop)
...
else if (LOOP_VINFO_USING_SELECT_VL_P (..))
...
else
...
and duplicate this tail into th
INFO_USING_SELECT_VL_P to be false if ncopies > 1. */
+ gcc_assert (!LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo));
If it is Ok for you. I am gonna testing it on X86 bootstrap + regtest.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-10 18:19
To: juzhe.zh...@riva
on RISC-V no regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-06 14:55
To: gcc-patches
CC: richard.sandiford; rguenther; Juzhe-Zhong
Subject: [PATCH V2] VECT: Support mask_len_strided_load/mask_len_strided_store
in loop vectorize
This patch adds strided load/store support on
no >= FIRST_PSEUDO_REGISTER;
+}
It depends on how targets configure REGMODE_NATURAL_SIZE target hook.
If we return QImode size, his patch is enable tracking bit ranges 7 bits subreg.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-11-12 19:53
To: 钟居哲
CC: Jeff Law; 丁乐华; gcc-patches; vm
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-12 21:47
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP l/ll round and rint HF mode autovec
From: Pan Li
This patch would like to support the FP below API auto vectorization
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-13 11:10
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix RVV dynamic frm tests failure
From: Pan Li
The hancement of mode-switching performs some optimization when
emit the frm backup
Does this patch fixes exposed bugs in current tests?
Or could you add test for it ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:06
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
Hi
I know the root cause is:
(reg:DI 15 a5 [orig:175 _103 ] [175])(reg:DI 15 a5 [orig:174 _100 ] [174])
is considered as true on rtx_equal_p.
I think return note1 == note2; will simplify your codes and fix this issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh
Sorry. It should be return note1 && note2 && note1 == note2;
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
&
regression of such issue
even if I didn't build toolchain with "zbb".
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:12
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.
&g
lation terminated.
My compile option is : --with-arch=rv32gcv_zfh_zvfh --with-abi=ilp32d
I am using SPIKE but I don't think simulator cause such issue since it is
compile issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:52
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff
Also, I didn't enable multi-lib.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 16:52
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.
> FAIL: gcc.target/riscv/rvv/autovec/slp-mask-run-1.c -O3 -ftree-v
I just checked definition of REG_EQUAL and REG_EQUIV.
As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on
REG_EQUIV and skip REG_EQUAL.
Could you check whether it does fix your issues ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:25
To: juzhe.zh
Ok. Lehua is going to take care of this issue. He has reproduced it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:31
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.
> I'm
a constant is loaded into a register that is never
assigned any other value, this kind of note is used.
I think REG_QEUIV is what I want. So I think you can test it to see if there is
regression on current tests.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 17:34
To: juzhe.zh...@riv
If there is a difference between them. I think we should fix riscv-common.cc.
Since I think "zvfh_zfh" should not be different with "zfh_zvfh"
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 18:17
To: Lehua Ding; juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.ch
Thanks for noticing it.
Will commit it with adjusting the testcase.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 18:05
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Optimize combine sequence by merge approach
test (with assembly check) instead of run test ?
If I don't build toolchain with "zbb" then we can't test such issue (VSETVL
BUG).
I may cause regression again if I change VSETVL pass in the future.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-13 18:31
To: juzhe.zh...
x27;s even a FIXME comment).
Address comments. The following patch doesn't change vect_check_gather_scatter
Also, I think RVV only needs to lower invariant stride into stride load/store.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-11-13 20:17
To: juzhe.zh...@rivai.ai
CC: gcc-patc
Could you test it v4096qi ?
Also, VLS modes need to be tested.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-15 11:48
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine the mask generation for vec_init case 2
From: Pan Li
We take
LGTM. You can commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Vineet Gupta
Date: 2023-11-15 14:41
To: gcc-patches
CC: Jeff Law; Robin Dapp; gnu-toolchain; Patrick O'Neill; Juzhe-Zhong; Vineet
Gupta
Subject: [PATCH] RISC-V: fix vsetvli pass testsuite failure [PR/112447]
From: Juzhe-
.
I think it should be COST MODEL issue.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-15 15:24
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Disallow RVV mode address for any
load/store[PR112535]
Curious about the code gen impact, does
Update just finished test CI.
Tested on aarch64 QEMU no regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-14 11:39
To: gcc-patches
CC: richard.sandiford; rguenther; Juzhe-Zhong
Subject: [PATCH] DOC/IFN/OPTAB: Add
mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN
This
Just finished X86 bootstrap && regtest no regression
And tested on aarch64 no regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-14 11:46
To: gcc-patches
CC: richard.sandiford; rguenther; Juzhe-Zhong
Subject: [PATCH] VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_ST
not new features, all same as RVV1.0.
Why do you invent the such ISA doesn't include any features that RVV1.0 doesn't
satisfy ?
I am not explicitly object this patch. But I should know the reason.
Btw, stage 1 will close soon. So I will review this patch on GCC-15 as long as
all other RISC-V maintainers agree.
juzhe.zh...@rivai.ai
e memory address is changed into "a7" which is wrong.
So. we should emit vsetvl, let GCC known the AVL "a7" used is a different value.
Then bug will be fixed.
But you remind me a thing, is that for whole register mode , we don't need this.
So, the code should be adjusted:
. So with compile option "-S", you will still see ASM as "vmulh.vv". but with
objdump, you will see th.vmulh.vv.
After this change, you can send V2, then I can continue to review on GCC-15.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-11-17 19:39
To:
Jeff has approved your patch.
You can commit it now.
Btw, CC Robin to let him know this patch.
Since he will support strcpy/strlenetc builtin with RVV instruction
sequence.
He will definitely needs compile option like this patch introduce.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date
(a4)'
/tmp/cc2KYYTs.s:3324: Error: unrecognized opcode `th.vse8.v v1,0(a4)'
But we need binutils support theadvector first, otherwise, it will fail during
building.
3. Add theadvector gating on target-support.exp. We don't want to run
theadvector test
when we don't
Oh. I suddenly realize this fix was included by Robin's indexed load/store fix
patch.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636654.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-20 12:12
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc;
Hi, Richi.
strided load/store has been posted for a while.
Can this feature be available on GCC-14 ?
Or postpone it to GCC-15 ?
Thanks.
juzhe.zh...@rivai.ai
发件人： juzhe.zh...@rivai.ai
发送时间： 2023-11-16 15:21
收件人： 钟居哲; gcc-patches
抄送： richard.sandiford; rguenther
主题： Re: [PATCH] DOC/IFN/OPTAB
I don't get it. Why do we need remove them ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-22 03:43
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
Hi,
this remove
LGTM。
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-22 14:03
To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: testsuite: Remove redundant vector_hw and zvfh_hw.
> I don't get it. Why do we need remove them ?
I
want to support the highpart overlap above. (Currently, we don't any overlap
between source and dest in such instructions).
So, I wonder whether we can pass "machine_mode" into register filter. Ok, I
think it's too late since stage 1 closes. I wonder we can add it in GCC-15?
Committed as it is obvious bug fix.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-22 18:53
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix incorrect use of vcompress in permutation
auto-vectorization
This patch fixes
Oh. You mean this patch also fixes FLTO failed case ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-11-23 19:55
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Disable AVL propagation of vrgather instruction
I was just about to
Thanks Robin.
I have sent V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637921.html
with adding PR/target 112670
Could you commit it for me ?
I am sorry that make you doing redundant work.
I didn't realize they are same issue :)
juzhe.zh...@rivai.ai
From: Robin Dapp
d 1: V16QI "vr")))
That is, same mode, same instruction pattern. We want the constraint to be
different according to TARGET_MIN_VLEN.
Currently, I don't know whether we can have an approach to support this feature.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 202
checked the dump is :
F foo (F a, F b)
{
[local count: 1073741824]:
= { 0.0, 9.0e+0, 0.0, 0.0 };
return ;
}
The dump IR seems reasonable to me.
I wonder whether we should walk around in RISC-V backend to generate the same
IR as ARM SVE ?
Or we should adjust the test ?
Thanks.
juzhe.zh...@rivai.ai
pr112743-0.c -> pr112743-1.c for consistent.
Otherwise LGTM. No need to send V2.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-29 14:37
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for ICE in block move when zve32f
From: Pan
Sorry for sending it twice.
Add
Co-authored-by: kito-cheng
Co-authored-by: kito-cheng in changelog.
No other difference.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-11-29 16:34
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-11-29 16:46
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Add explicit braces to eliminate warning.
From: xuli
../.././gcc/gcc/config/riscv/riscv.cc: In function ‘void
;
}
This is a prototype. Is this idea reasonable to Richi ?
Thanks.
juzhe.zh...@rivai.ai
Why does get_vector_mode doesn't exist a vector mode ?
It must exist a vector mode, otherwise, it will cause ICE in other situations.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-11-30 15:21
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] R
Thanks for support it.
LGTM from my side.
Wait for kito's more comments.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-12 10:08
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; gaofei; wangfeng; xuli
Subject: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
From:
ec[i];
}
}
Could you revise this piece of codes ?
Other comments has been addressed in V4:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629959.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 04:31
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kit
uld you run your rvv intrinsic api ci with this patch?
I am worrying that the resolve stuff will destroy the existing APi support.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 15:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v
It looks reasonable to me now.
But let's wait for kito's more comments.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 16:46
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-12 16:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add missed cond autovec testcases
This patch adds all missed cond autovec testcases. For not support
cond
Thanks Robin.
I have tried your codes. It works fine and tests passes.
Does your code O(nlogn) complexity ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 16:19
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH V4] RISC-V: Support
tree lhs = gimple_get_lhs (stmt);
mode = TYPE_MODE (TREE_TYPE (lhs));
If it is not a STORE, I assume it always has a LHS. Turns out that my original
thought is incorrect.
I think I know the fix.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 17:17
To: Juzhe-Zh
GCC testsuite (I belive we can reproduce with some case in GCC testsuite in the
future).
Is that reasonable ? If yes, I will fix all your comments and send V5.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 17:31
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.
Then you don't need to waste time on reduce the case from SPEC.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-12 17:36
To: Robin Dapp; gcc-patches
CC: Robin Dapp; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: Re: [PATCH V4] RISC-V: Support Dynamic LMUL Cost model
Th
Ok add it in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630048.html
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-12 21:29
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VECTOR BOOL vcond_mask
ation:
negate + cond_len_fma -> cond_len_fnma/cond_len_fms/cond_len_fnms.
That's what I want to support in gimple fold.
Let's see more comments from Richard and Richi.
juzhe.zh...@rivai.ai
>> Do we need the additional helper function?
Yes. We need the additional helper function since I will cal emit_insn
(gen_vec_extract (mode, mode)
in the following patch which fixes PR111391 ICE.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-13 20:31
To: Juzhe-Zhong; gcc-patc
Just realize this patch cause some unexpected ICE FAILs in GCC regression.
Now, V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630194.html
has fully passed the regression.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-13 21:01
To: gcc-patches
CC: kito.cheng
create_integer_operand (&ops[2], index);
+ expand_insn (icode, 3, ops);
This code is copied from optabs-query.cc
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to
Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in
vec_extract optab ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar
You mean try pr111391.c
that I added with rv64gcv_zve32x ?
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
move[PR111391]
Could you
../../../../gcc/gcc/cfgexpand.cc:4044
0x10699f3 expand_gimple_basic_block
Thanks for catching this.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
}
}
return true;
}
ASM:
vsetivli zero,2,e32,mf2,ta,ma
vslidedown.vi v2,v1,1
vmv.x.s a5,v2
slli a5,a5,32
vmv.x.s a0,v1
or a0,a5,a0
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dap
ot;vadd", bases::vadd, shapes::alu
should already known since it is a known function_base.
The last 3 arguments may need some elegant analysis or map table to quickly
grep.
So, I think we should consider this framework seriously.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-12 1
f the function_instance.
Then we can get the non-overloaeded function.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-15 10:02
To: pan2.li; gcc-patches
CC: pan2.li; yanzhang.wang; kito.cheng
Subject: Re: [PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV
intrinsic
Thanks for fixing it.
I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 kito
has refactored it) there.
But I think we need kito's more comments about that.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-18 12:19
To: gcc-patches
CC: kito.cheng; palmer; juzhe.
Thanks Richard.
Address comments on V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630699.html
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-09-17 23:29
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V2] internal-fn: Support undefined rtx for
LGTM。
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 20:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch
This patch add the missed PR111255 testcase which is fixed by this
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 20:29
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Removed misleading comments in testcases
This patch removed the misleading comments in testcases since we
support
Sorry for I made a mistake here.
Change 'mayb_lt' into '!ordered_p' in V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630835.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-19 10:25
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rd
Thanks for the refactoring.
This patch is needed in VLS fma support and undefined value enabling support.
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-18 19:37
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V
ve (dest, XEXP (XEXP (src, 0), 0));
+ riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (XEXP (src, 0),
1));
If it can fix your issue, plz send a patch and commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-09-19 01:38
To: Li, Pan2; Kito Cheng
CC: gc
I didn't see this issue.
They should be the bogus FAILs.
We should either fix testcases or ignore them.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-09-20 08:34
To: Juzhe-Zhong; Robin Dapp; gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu;
joer
/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,5 +1,4 @@
#include
-#include
and commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-20 08:52
To: 钟居哲
CC: Patrick O'Neill; Robin Dapp; gcc-patches; Kito.cheng; jeffreyalaw; palmer;
Edwin Lu; joern.ren
t;VF" so that you could also support VLS CEIL.
Besides, I want to see this following case:
a[i] = cond[i] ? CEIL (b[i]): c[i];
Ideally, we should be able to combine vfcvt + vmerge into vfcvt with mask.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-20 10:30
To: gcc-patches
CC: juzhe.
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-20 15:03
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Reorganize and rename combine patterns in
autovec-opt.md
This patch reorganize and rename the combine patterns
more reasonable.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-09-20 17:14
To: Lehua Ding; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Support combine cond extend and reduce sum to
widen reduce sum
Hi Lehua,
I think this is bette
Yes. We could wait for a more few days to backport.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-21 00:41
To: Juzhe-Zhong
CC: GCC Patches; Kito Cheng; Jeff Law; Robin Dapp
Subject: Re: [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS]
Does it also happened on gcc 13 branch? If
Thanks a lot. LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-21 11:12
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Optimized for strided load/store with stride ==
element width[PR111450]
From: xuli
When stride == element width, vlsse should be
LGTM
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-09-21 11:44
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more
generic names
This little rename
operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations
&& (flag_fp_int_builtin_inexact || !flag_trapping_math))
|| (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MAT
Also。 Remove math.h include。
Instead, plz use __builtin_ceil.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-21 18:32
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
This patch would
Hi, Patrick.
GNU rvv intrinsic api test-generator has been merged:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/commits/main
Could you include the full RVV intrinsic API test in your test CI?
Currently, we don't include all API test in the GCC testsuite since it's too
big.
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 08:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v4] RISC-V: Support ceil and ceilf auto-vectorization
From: Pan Li
Update in v4:
* Add test for _Float16.
* Remove unnecessary macro in def.h
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 09:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage __builtin_xx instead of math.h for test
From: Pan Li
The math.h may have problems in some environment, take __builtin__xx
LMUL_8))
change it into:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > LMUL_1)
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-22 09:33
To: gcc-patches
CC: kito.cheng; pal
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