Hi. Kito.
Could you review this code ? Regression is running....
/* Expand
(set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
Expand this data movement instead of simply forbid it since
we can improve the code generation for this following scenario
by RVV auto-vectorization:
(set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
(set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
Since RVV mode and scalar mode are in different REG_CLASS,
we need to explicitly move data from V_REGS to GR_REGS by scalar move. */
if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src))))
{
machine_mode vmode = GET_MODE (SUBREG_REG (src));
unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant ();
unsigned int nunits = vmode_size / mode_size;
scalar_mode smode = as_a<scalar_mode> (mode);
unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1;
if (num == 2)
{
/* If we want to extract 64bit value but ELEN < 64,
we use RVV vector mode with EEW = 32 to extract
the highpart and lowpart. */
smode = SImode;
nunits = nunits * 2;
}
vmode = riscv_vector::get_vector_mode (smode, nunits).require ();
enum insn_code icode
= convert_optab_handler (vec_extract_optab, vmode, smode);
gcc_assert (icode != CODE_FOR_nothing);
rtx v = gen_lowpart (vmode, SUBREG_REG (src));
for (unsigned int i = 0; i < num; i++)
{
class expand_operand ops[3];
rtx result;
if (num == 1)
result = dest;
else if (i == 0)
result = gen_lowpart (smode, dest);
else
result = gen_reg_rtx (smode);
create_output_operand (&ops[0], result, smode);
ops[0].target = 1;
create_input_operand (&ops[1], v, vmode);
create_integer_operand (&ops[2], index + i);
expand_insn (icode, 3, ops);
if (ops[0].value != result)
emit_move_insn (result, ops[0].value);
if (i == 1)
{
rtx tmp
= expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result),
gen_int_mode (32, Pmode), NULL_RTX, 0,
OPTAB_DIRECT);
rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0,
OPTAB_DIRECT);
emit_move_insn (dest, tmp2);
}
}
return true;
}
ASM:
vsetivli zero,2,e32,mf2,ta,ma
vslidedown.vi v2,v1,1
vmv.x.s a5,v2
slli a5,a5,32
vmv.x.s a0,v1
or a0,a5,a0
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-14 17:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
move[PR111391]
Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x
On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
<juzhe.zh...@rivai.ai> wrote:
>
> You mean try pr111391.c
> that I added with rv64gcv_zve32x ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 17:20
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
> Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
> move[PR111391]
> Could you check if it work correctly for rv64gcv_zve32x? add testcase
> no matter if it works or not :)
>
> On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
> <juzhe.zh...@rivai.ai> wrote:
> >
> > Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in
> > vec_extract optab ?
> >
> >
> >
> > juzhe.zh...@rivai.ai
> >
> > From: Kito Cheng
> > Date: 2023-09-14 16:11
> > To: Juzhe-Zhong
> > CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> > Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode
> > move[PR111391]
> > On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong <juzhe.zh...@rivai.ai> wrote:
> > >
> > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> > >
> > > I notice that previous patch (V2 patch) cause additional execution fail
> > > of pr69719.c
> > > This FAIL is because of the latent BUG of VSETVL PASS.
> > >
> > > So this patch includes VSETVL PASS fix even though it's not related to
> > > the PR111391.
> > >
> > > I have confirm the whole regression no additional FAILs are introduced.
> > >
> > > PR target/111391
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/autovec.md (@vec_extract<mode><vel>): Remove @.
> > > (vec_extract<mode><vel>): Ditto.
> > > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> > >
> > > ---
> > > gcc/config/riscv/autovec.md | 2 +-
> > > gcc/config/riscv/riscv-vsetvl.cc | 4 ++-
> > > gcc/config/riscv/riscv.cc | 32 +++++++++++++++++++
> > > .../riscv/rvv/autovec/partial/slp-9.c | 1 -
> > > .../gcc.target/riscv/rvv/autovec/pr111391.c | 28 ++++++++++++++++
> > > 5 files changed, 64 insertions(+), 3 deletions(-)
> > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> > >
> > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > > index e74a1695709..7121bab1716 100644
> > > --- a/gcc/config/riscv/autovec.md
> > > +++ b/gcc/config/riscv/autovec.md
> > > @@ -1442,7 +1442,7 @@
> > > ;;
> > > -------------------------------------------------------------------------
> > > ;; ---- [INT,FP] Extract a vector element.
> > > ;;
> > > -------------------------------------------------------------------------
> > > -(define_expand "@vec_extract<mode><vel>"
> > > +(define_expand "vec_extract<mode><vel>"
> >
> > Why remove this? I saw this change was introduced in v3?
> >
> >
> > > [(set (match_operand:<VEL> 0 "register_operand")
> > > (vec_select:<VEL>
> > > (match_operand:V_VLS 1 "register_operand")
> >
>
