I didn't see this issue. They should be the bogus FAILs. We should either fix testcases or ignore them.
juzhe.zh...@rivai.ai From: Patrick O'Neill Date: 2023-09-20 08:34 To: Juzhe-Zhong; Robin Dapp; gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu; joern.rennecke; jeremy.bennett; gnu-toolchain Subject: Re: [Committed] RISC-V: Support VLS unary floating-point patterns Hi, This patch highlights an issue Edwin and I have been having with the testsuite where rv64 testcases are run when testing rv32gcv. There's a large number of new failures in the rv32gcv testsuite from this seemingly innocuous patch. https://github.com/ewlu/riscv-gnu-toolchain/issues/166 (The repo is still a WIP - eventually will be non-gating patchworks pre-commit CI) From Edwin and my investigation the failures for rv32gcv look like [1]. /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11: fatal error: gnu/stubs-lp64d.h: No such file or directory compilation terminated. Top of the failing testcase: /* { dg-do compile } */ /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */ #include "def.h" The dg-options explicitly set rv64gcv, so I don't think this testcase should even be executed. For the 3 new failures on rv64gcv, they all explicitly set rv32gcv. /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ These are seen on non-multilib builds. Multilib rv32/64gc does not appear to have the same issue when compiling (we're currently testing multilib rv32/64gcv to see if they encounter issues when executing). Are other people seeing similar errors/is this a known issue? Patrick [1]: Executing on host: /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize --param riscv-autovec-preference=scalable -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects -fno-ident -S -o floating-point-mul-3.s (timeout = 600) spawn -ignore SIGHUP /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize --param riscv-autovec-preference=scalable -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects -fno-ident -S -o floating-point-mul-3.s In file included from /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515, from /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33, from /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27, from /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2, from /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4: /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11: fatal error: gnu/stubs-lp64d.h: No such file or directory compilation terminated. compiler exited with status 1 FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3 -ftree-vectorize --param riscv-autovec-preference=scalable (test for excess errors) On 9/19/23 04:26, Juzhe-Zhong wrote: > Extend current VLA patterns with VLS modes. > > Regression all passed. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Extend VLS modes. > * config/riscv/vector.md: Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test. > * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test. > > --- > gcc/config/riscv/autovec.md | 12 ++--- > gcc/config/riscv/vector.md | 20 +++---- > .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +- > .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++ > 4 files changed, 70 insertions(+), 17 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 769ef6daa36..75ed7ae4f2e 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -1031,9 +1031,9 @@ > ;; - vfneg.v/vfabs.v > ;; > ------------------------------------------------------------------------------- > (define_insn_and_split "<optab><mode>2" > - [(set (match_operand:VF 0 "register_operand") > - (any_float_unop_nofrm:VF > - (match_operand:VF 1 "register_operand")))] > + [(set (match_operand:V_VLSF 0 "register_operand") > + (any_float_unop_nofrm:V_VLSF > + (match_operand:V_VLSF 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > @@ -1052,9 +1052,9 @@ > ;; - vfsqrt.v > ;; > ------------------------------------------------------------------------------- > (define_insn_and_split "<optab><mode>2" > - [(set (match_operand:VF 0 "register_operand") > - (any_float_unop:VF > - (match_operand:VF 1 "register_operand")))] > + [(set (match_operand:V_VLSF 0 "register_operand") > + (any_float_unop:V_VLSF > + (match_operand:V_VLSF 1 "register_operand")))] > "TARGET_VECTOR && can_create_pseudo_p ()" > "#" > "&& 1" > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f7f37da692a..f66ffebba24 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -6756,8 +6756,8 @@ > ;; > ------------------------------------------------------------------------------- > > (define_insn "@pred_<optab><mode>" > - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") > - (if_then_else:VF > + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, > vr") > + (if_then_else:V_VLSF > (unspec:<VM> > [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") > @@ -6768,9 +6768,9 @@ > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM) > (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) > - (any_float_unop:VF > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > + (any_float_unop:V_VLSF > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > "TARGET_VECTOR" > "vf<insn>.v\t%0,%3%p1" > [(set_attr "type" "<float_insn_type>") > @@ -6783,8 +6783,8 @@ > (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) > > (define_insn "@pred_<optab><mode>" > - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") > - (if_then_else:VF > + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, > vr") > + (if_then_else:V_VLSF > (unspec:<VM> > [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") > @@ -6793,9 +6793,9 @@ > (match_operand 7 "const_int_operand" " i, i, i, i") > (reg:SI VL_REGNUM) > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > - (any_float_unop_nofrm:VF > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > + (any_float_unop_nofrm:V_VLSF > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")) > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] > "TARGET_VECTOR" > "vf<insn>.v\t%0,%3%p1" > [(set_attr "type" "<float_insn_type>") > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > index 5df90704885..d7b721b4e3e 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h > @@ -1,4 +1,5 @@ > #include <stdint-gcc.h> > +#include <math.h> > > typedef int8_t v1qi __attribute__ ((vector_size (1))); > typedef int8_t v2qi __attribute__ ((vector_size (2))); > @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size > (4096))); > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) > \ > { > \ > for (int i = 0; i < NUM; ++i) > \ > - a[i] = OP b[i]; > \ > + a[i] = OP (b[i]); > \ > } > > #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) > \ > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > new file mode 100644 > index 00000000000..c2ab0098afa > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c > @@ -0,0 +1,52 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 > -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 > -fdump-tree-optimized" } */ > + > +#include "def.h" > + > +DEF_OP_V (neg, 2, _Float16, -) > +DEF_OP_V (neg, 4, _Float16, -) > +DEF_OP_V (neg, 8, _Float16, -) > +DEF_OP_V (neg, 16, _Float16, -) > +DEF_OP_V (neg, 32, _Float16, -) > +DEF_OP_V (neg, 64, _Float16, -) > +DEF_OP_V (neg, 128, _Float16, -) > +DEF_OP_V (neg, 256, _Float16, -) > +DEF_OP_V (neg, 512, _Float16, -) > +DEF_OP_V (neg, 1024, _Float16, -) > +DEF_OP_V (neg, 2048, _Float16, -) > + > +DEF_OP_V (neg, 2, float, -) > +DEF_OP_V (neg, 4, float, -) > +DEF_OP_V (neg, 8, float, -) > +DEF_OP_V (neg, 16, float, -) > +DEF_OP_V (neg, 32, float, -) > +DEF_OP_V (neg, 64, float, -) > +DEF_OP_V (neg, 128, float, -) > +DEF_OP_V (neg, 256, float, -) > +DEF_OP_V (neg, 512, float, -) > +DEF_OP_V (neg, 1024, float, -) > + > +DEF_OP_V (neg, 2, double, -) > +DEF_OP_V (neg, 4, double, -) > +DEF_OP_V (neg, 8, double, -) > +DEF_OP_V (neg, 16, double, -) > +DEF_OP_V (neg, 32, double, -) > +DEF_OP_V (neg, 64, double, -) > +DEF_OP_V (neg, 128, double, -) > +DEF_OP_V (neg, 256, double, -) > +DEF_OP_V (neg, 512, double, -) > + > +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } > */ > +/* { dg-final { scan-assembler-not {csrr} } } */ > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
