在 2025/3/16 3:54, Jeff Law 写道:
On 3/14/25 2:29 PM, Vineet Gupta wrote:
Hi,
On 12/3/24 03:02, Jiawei wrote:
This patch series introduces support for RISC-V Profiles RV20, RV22[1],
and RV23[2][3].The updates enhance compatibility and streamline the
process
of leveraging RISC-V Profiles
RISC-V backend don't support '-mgeneral-regs-only' option, skip it.
https://godbolt.org/z/38M8vPW74
gcc/testsuite/ChangeLog:
* gcc.dg/pr119160.c: Skip for RISC-V backend.
---
gcc/testsuite/gcc.dg/pr119160.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg
在 2025/5/8 16:25, Richard Biener 写道:
On Thu, May 8, 2025 at 10:02 AM Jiawei wrote:
RISC-V backend don't support '-mgeneral-regs-only' option, skip it.
https://godbolt.org/z/38M8vPW74
The test should instead use
/* { dg-additional-options "-mgeneral-regs-only" {
Limit option '-mgeneral-regs-only' to those in supported backends.
Version log:
https://patchwork.sourceware.org/project/gcc/patch/20250508080102.1340059-1-jia...@iscas.ac.cn/
gcc/testsuite/ChangeLog:
* gcc.dg/pr119160.c: Limit backends.
---
gcc/testsuite/gcc.dg/pr119160.c | 3
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profile
This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified
Version log:
Update the testcases, using lowercase letter.
gcc/ChangeLog:
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profile
Committed on trunk, thanks!
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=43b450e3f72a53c744e77f55393962f1d349373a
BR,
Jiawei
在 2025/5/11 0:42, Jeff Law 写道:
On 5/10/25 6:30 AM, Jiawei wrote:
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to
The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.
[1]
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile
Versi
The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.
[1]
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile
gcc/C
This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote
Version log:
Update the testcases, using lowercase letter.
The augmented hypervisor series extensions 'sha'[1] is a new profile-defined
extension series that captures the full set of features that are mandated to
be supported along with the 'H' extension.
[1]
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile
Versi
/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-57.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def | 13 +
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi
;a=commit;h=4d7a634f6d41029811cdcbd5f7282b5b07890094
[1] https://godbolt.org/z/dhYoTMY1v
[2]
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=05daf617ea22e1d818295ed2d037456937e23530
gcc/ChangeLog:
* config/riscv/bitmanip.md (*bset_2): New pattern.
* config/riscv/peephole.m
Update the defination of RISC-V extensions in riscv-ext.def.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Update declaration.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def | 282 -
1 file changed, 141 insertions(+), 141 deletions(-)
diff
Committed since it is a simply typo fix.
Thanks
在 2025/6/5 9:38, Jiawei 写道:
Update the defination of RISC-V extensions in riscv-ext.def.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Update declaration.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def | 282
> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2025-06-03 03:37:10 (星期二)
> 收件人: Jiawei , gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@gmail.com, pal...@rivosinc.com, christoph.muell...@vrull.eu
> 主题: Re: [PATCH] RISC-V: Add Shlcofideleg extension.
>
>
>
> On
repository.[2] The latest news of KunMingHu can be found
in the XiangShan Biweekly.[3]
Co-Authored-By: Jiawei Chen
Co-Authored-By: Yangyu Chen
Co-Authored-By: Tang Haojin
[1] https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
[2]
https://github.com/OpenXiangShan/XiangShan/blob/master/src
在 2025/5/30 1:46, Jeff Law 写道:
On 5/28/25 9:05 PM, Jiawei wrote:
This seems like it would be much better as a combine pattern. In
fact, I'm a bit surprised that combine didn't simplify this series
of operations into a IOR. So I'd really like to see the .combine
dump w
This patch adds a new simplification rule to `simplify-rtx.cc` that
handles a common bit manipulation pattern involving a single-bit set
and clear followed by XOR.
The transformation targets RTL of the form:
(xor (and (rotate (~1), A) B) (ashift 1, A))
which is semantically equivalent to:
B
在 2025/6/10 7:20, Jeff Law 写道:
On 6/5/25 6:25 AM, Jiawei wrote:
Thanks for your suggestions, I found that the ior is successful
generated in combine pass without using the zbs extension, and in
other architecture it also work fine.
Yea, it's probably an artifact of how we ne
This patch adds a new simplification rule to `simplify-rtx.cc` that
handles a common bit manipulation pattern involving a single-bit set
and clear followed by XOR.
The transformation targets RTL of the form:
(xor (and (rotate (~1) A) B) (ashift 1 A))
which is semantically equivalent to:
B |
在 2025/6/11 23:53, Richard Sandiford 写道:
Jiawei writes:
This patch adds a new simplification rule to `simplify-rtx.cc` that
handles a common bit manipulation pattern involving a single-bit set
and clear followed by XOR.
The transformation targets RTL of the form:
(xor (and (rotate (~1
ombine dump, it is correct?
(insn 17 14 18 2 (set (reg:DI 146)
(ior:DI (ashift:DI (const_int 1 [0x1])
(subreg:QI (reg:DI 148 [ a ]) 0))
(reg:DI 144 [ *b_7(D) ]))) "/app/example.cpp":5:7 582 {*bsetdi}
(expr_list:REG_DEAD (reg:DI 148 [ a ])
(expr_list:REG_DEAD (reg:DI 144 [ *b_7(D) ])
(nil
BR,
Jiawei
c.target/riscv/arch-58.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */
LGTM, thanks.
Jiawei
在 2025/5/29 0:13, Jeff Law 写道:
On 5/28/25 4:23 AM, Jiawei wrote:
This patch adds a peephole2 optimization that combines a 'bclr'
followed by
a 'binv' into a single 'bset' instruction when the Zbs extension is
enabled.
The motivation for this patch i
c.target/riscv/arch-58.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */
LGTM, thanks.
Jiawei
/testsuite/ChangeLog:
* gcc.target/riscv/arch-smrnmi.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def | 13 +
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi | 4
gcc/testsuite
These patches add support for several privileged RISC-V extensions, including
Sm/scsrind, Smrnmi, Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl.
The CSRs definition in Binutils part, and gcc part just let the compiler and
user know these extensions are supported.
Jiawei (7):
RISC-V
.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-sscounterenw.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def | 13 +
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi
:
* gcc.target/riscv/arch-ssu64xl.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def| 13 +
gcc/config/riscv/riscv-ext.opt| 2 ++
gcc/doc/riscv-ext.texi| 4
gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c | 5
/testsuite/ChangeLog:
* gcc.target/riscv/arch-smcsrind.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def| 26 +++
gcc/config/riscv/riscv-ext.opt| 4 +++
gcc/doc/riscv-ext.texi| 8 ++
.../gcc.target
extension.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-sstvala.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def| 13 +
gcc/config/riscv/riscv-ext.opt| 2 ++
gcc/doc/riscv-ext.texi| 4
gcc
/testsuite/ChangeLog:
* gcc.target/riscv/arch-ssccptr.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def| 13 +
gcc/config/riscv/riscv-ext.opt| 2 ++
gcc/doc/riscv-ext.texi| 4
gcc/testsuite/gcc.target
the new extension.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-sstvecd.c: New test.
Signed-off-by: Jiawei
---
gcc/config/riscv/riscv-ext.def| 13 +
gcc/config/riscv/riscv-ext.opt| 2 ++
gcc/doc/riscv-ext.texi| 4
Thanks, pushed to trunk.
Jiawei
在 2025/6/5 14:36, Kito Cheng 写道:
LGTM :)
On Thu, Jun 5, 2025 at 2:21 PM Jiawei wrote:
These patches add support for several privileged RISC-V extensions, including
Sm/scsrind, Smrnmi, Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl.
The CSRs definition
Committed on trunk with typo fixed, thanks!
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f0cd40f71ba424bde94dcddbf1df67bb100b82ef
Jiawei
在 2025/6/4 21:33, Jeff Law 写道:
On 6/4/25 3:56 AM, Jiawei wrote:
This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the
Changes since v1:
- NFC with attribution to PR/119164 it helps fix and the testcase.
FRM mode switching state machine has DYN as default state which it also
fallsback to after transitioning to other states such as DYN_CALL.
Currently TARGET_MODE_EMIT generates a FRM restore on any transition t
This patch adds a new simplification rule to `simplify-rtx.cc` that
handles a common bit manipulation pattern involving a single-bit set
and clear followed by XOR.
The transformation targets RTL of the form:
(xor (and (rotate (~1) A) B) (ashift 1 A))
which is semantically equivalent to:
B |
Committed to trunk, thanks.
Jiawei
在 2025/6/16 11:21, Jiawei 写道:
Add b-ext in RVA/B23 as independent extension flags and add supm in
RVA23.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add b-ext and supm.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-53.c
Add b-ext in RVA/B23 as independent extension flags and add supm in
RVA23.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add b-ext and supm.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-53.c: Update testcase.
---
gcc/common/config/riscv/riscv-common.cc | 6 +++---
Committed to trunk, thanks.
Jiawei
在 2025/6/13 21:02, Richard Sandiford 写道:
Jiawei writes:
This patch adds a new simplification rule to `simplify-rtx.cc` that
handles a common bit manipulation pattern involving a single-bit set
and clear followed by XOR.
The transformation targets RTL of
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