Re: [PATCH] RISC-V: Allow all const_vec_duplicates as constants.

Lgtm Robin Dapp 於 2023年5月26日 週五 22:10 寫道： > Hi, > > as we can always broadcast an integer constant to a vector register > allow them in riscv_const_insns. We need as many instructions as > it takes to generate the constant and one vmv.vx. > > Regards > Robin > > gcc/ChangeLog: > > * co

Re: [PATCH V2] RISC-V: Fix zero-scratch-regs-3.c fail

LGTM 於 2023年5月26日 週五 08:46 寫道： > From: Juzhe-Zhong > > gcc/ChangeLog: > > * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict > VL and drop VL in ops. > > --- > gcc/config/riscv/riscv.cc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gcc/conf

Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches wrote: > > Sorry for disturbing but please help to take this PATCH in front of the > reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot. > > Pan > > -Original Message- > From: Li, Pan2 > Sent: Thursday, May 2

Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

LGTM On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches wrote: > > Thanks Robin. > > Sorry for not mentioned that it depends on another patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in > the reviewing queue. > > Yes, totally agree we can remove the comme

Re: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

LGTM, thanks :) On Thu, May 25, 2023 at 3:00 PM wrote: > > From: Juzhe-Zhong > > Currently mode switching incorrect codegen for the following case: > void fn (void); > > void f (void * in, void *out, int32_t x, int n, int m) > { > for (int i = 0; i < n; i++) { > vint32m1_t v = __riscv_vle3

Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

LGTM On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to add new sub extension (aka ZVFHMIN) to the > -march= option. To make it simple, only the sub extension itself is > involved in this patch, and the underlying FP16 related RVV intrins

Re: [PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

Thanks for this patch, just few minor comment, I think this is pretty close to accept :) Could you reference JiaWei's match_parallel[1] to prevent adding bunch of *_offset_operand and stack_push_up_to_*_operand? [1] https://patchwork.sourceware.org/project/gcc/patch/20230406062118.47431-5-jia..

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

On Mon, May 29, 2023 at 10:53 AM Jin Ma wrote: > > > > When testing a extension, it is often necessary for a certain program not > > > to > > > need some kind of extension, such as the bitmanip extension, to evaluate > > > the > > > performance or codesize of the extension. However, the current

Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

LGTM, but with one question. On Fri, May 26, 2023 at 7:36 PM wrote: > > From: Juzhe-Zhong > > This patch support FMA auto-vectorization pattern. > 1. Let's RA decide vmacc or vmadd. > 2. Fix bug of vector.md which generate incorrect information to VSETVL >PASS when testing ternop-3.c. Does

Re: [PATCH] RISC-V: Remove redundant printf of abs-run.c

Ok 於 2023年5月29日 週一 11:39 寫道： > From: Juzhe-Zhong > > Notice that this testcase cause unexpected fail: > FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess errors) > Excess errors: > /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.ta

Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

Ok, and just make sure this only appear for trunk, right? juzhe.zh...@rivai.ai 於 2023年5月29日 週一，12:19寫道： > This patch is fixing VSETVL PASS bug. Ok for trunk ? > > > > juzhe.zh...@rivai.ai > > From: juzhe.zhong > Date: 2023-05-26 11:01 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer

Re: [PATCH v7] RISC-V: Using merge approach to optimize repeating sequence in vec_init

LGTM, thanks On Mon, May 29, 2023 at 4:54 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to optimize the VLS vector initialization like > repeating sequence. From the vslide1down to the vmerge with a simple > cost model, aka every instruction only has 1 cost. > > Giv

Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

pushed the bug fixed part to gcc 13 branch On Mon, May 29, 2023 at 12:52 PM Li, Pan2 via Gcc-patches wrote: > > Committed with 2 patches, thanks Kito. > > Pan > > From: juzhe.zh...@rivai.ai > Sent: Monday, May 29, 2023 11:19 AM > To: kito.cheng > Cc: gcc-patches ; Kito.cheng > ; palmer ; Robin

Re: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

LGTM On Mon, May 29, 2023 at 9:03 PM wrote: > > From: Pan Li > > This patch would like to remove unnecessary comments of some self > explained parameters and try a better name to avoid misleading. > > Signed-off-by: Pan Li > > gcc/ChangeLog: > > * config/riscv/riscv-v.cc (emit_vlmax_ins

Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

LGTM On Tue, May 30, 2023 at 8:30 AM juzhe.zh...@rivai.ai wrote: > > Hi, this patch is same implementation as FMA which has been merged. > Ok for trunk? > > > > juzhe.zh...@rivai.ai > > From: juzhe.zhong > Date: 2023-05-29 14:53 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer; jeff

Re: [PATCH] RISC-V: Fix warning in riscv.md

You could use UINTVAL rather than (unsigned HOST_WIDE_INT) INTVAL On Tue, May 30, 2023 at 9:14 AM wrote: > > From: Juzhe-Zhong > > Notice there is warning: > ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison > between signed and unsigned integer expressions [-Wsign-compa

Re: [PATCH V2] RISC-V: Fix warning in riscv.md

LGTM :) On Tue, May 30, 2023 at 10:09 AM wrote: > > From: Juzhe-Zhong > > Notice there is warning: > ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison > between signed and unsigned integer expressions [-Wsign-compare] >if (INTVAL (operands[2]) == GET_MODE_MASK (H

Re: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

LGTM On Tue, May 30, 2023 at 10:15 AM juzhe.zh...@rivai.ai wrote: > > Ok for trunk ? > > > > juzhe.zh...@rivai.ai > > From: juzhe.zhong > Date: 2023-05-29 12:35 > To: gcc-patches > CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; > Juzhe-Zhong > Subject: [PATCH V2] RISC-V: Add

[PATCH] RISC-V: Basic VLS code gen for RISC-V

GNU vector extensions is widly used around this world, and this patch enable that with RISC-V vector extensions, this can help people leverage existing code base with RVV, and also can write vector programs in a familiar way. The idea of VLS code gen support is emulate VLS operation by VLA operati

Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V

> >> /* Return true if MODE is true VLS mode. */ > >> bool > >> vls_mode_p (machine_mode mode) > >> { > >> switch (mode) > >> { > >> case E_V4SImode: > >> case E_V2DImode: > >> case E_V8HImode: > >> case E_V16QImode: > >> return true; > >> default: > >> return

Re: [PATCH] riscv: update riscv_asan_shadow_offset

LGTM, I remember Luís updated[1] that, but apparently I forgot sync this to gcc, and just to remind, I plan to change that to dynamic offset[2] to make that work on Sv39, Sv48 and Sv57, but we are still running testing and debugging to make sure LSAN works well... [1] https://reviews.llvm.org/D97

Re: [PATCH] riscv: add work around for PR sanitizer/82501

LGTM, thanks :) On Tue, May 30, 2023 at 4:43 PM Andreas Schwab via Gcc-patches wrote: > > PR sanitizer/82501 > * c-c++-common/asan/pointer-compare-1.c: Disable use of small data > on RISC-V. > --- > gcc/testsuite/c-c++-common/asan/pointer-compare-1.c | 1 + > 1 file chang

Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V

(I am still on the meeting hell, and will be released very later, apology for short and incomplete reply, and will reply complete later) One point for adding VLS mode support is because SLP, especially for those SLP candidate not in the loop, those case use VLS type can be better, of cause using l

Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V

One more note: we found a real case in spec 2006, SLP convert two 8 bit into int8x2_t, but the value has live across the function call, it only need to save-restore 16 bit, but it become save-restore VLEN bits because it using VLA mode in backend, you could imagine when VLEN is larger, the performa

Re: [PATCH] riscv: update riscv_asan_shadow_offset

Andreas Schwab via Gcc-patches 於 2023年5月30日 週二 17:37 寫道： > Ok for 12 and 13 branch? > Yes, thanks! > -- > Andreas Schwab, SUSE Labs, sch...@suse.de > GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 > "And now for something completely different." >

Re: Re: [PATCH] RISC-V: Basic VLS code gen for RISC-V

It's long mail but I think this should explain most high level concept why I did this: I guess I skipped too much story about the VLS-mode support; VLS-mode support can be split into the middle-end and back-end. # Middle-end As Richard mentioned, those VLS types can be held by VLA-modes; for exam

Re: [PATCH] RISC-V: Fix unreachable test code for init repeat sequence.

OK On Wed, May 31, 2023 at 8:29 AM wrote: > > From: Pan Li > > This patch fix one unreachable test code, which is for debugging purpose > without cleanup before commit. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequen

Re: [PATCH V1] Testsuite: Fix a fail about xtheadcondmov-indirect-rv64.c

Could you use something like *[a-x0-9]+ for those operands to prevent us hitting that issue again? Ref: https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c#L9 On Wed, May 31, 2023 at 2:18 PM wrote: > > From: yulong > > I find fail of

Re: [PATCH] RISC-V: Add ZVFH extension to the -march= option

LGTM On Wed, May 31, 2023 at 2:58 PM wrote: > > From: Pan Li > > This patch would like to add new sub extension (aka ZVFH) to the -march= > option. > To make it simple, only the sub extension itself is involved in this patch, > and > the underlying FP16 related RVV intrinsic API depends on the

Re: Re: [PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

> >[1] > >https://patchwork.sourceware.org/project/gcc/patch/20230406062118.47431-5-jia...@iscas.ac.cn/ > Thanks for your review. > > The md file looks verbose with bunch of *_offset_operand and > stack_push_up_to_*_operand, but it significantly > simplies implementation of recognizing zmcp push

Re: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine mode.

LGTM, thanks :) On Thu, Jun 1, 2023 at 3:20 PM juzhe.zh...@rivai.ai wrote: > > LGTM. > > We are waiting for FP16 vector to start floating-point auto-vectorizations > > Thanks so much. > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-01 15:17 > To: gcc-patches > CC: juzhe.zhong; kito.c

Re: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

Lgtm Li, Pan2 via Gcc-patches 於 2023年6月1日 週四，20:10寫道： > Thanks Juzhe for pointing out this. > > Pan > > -Original Message- > From: Li, Pan2 > Sent: Thursday, June 1, 2023 8:09 PM > To: gcc-patches@gcc.gnu.org > Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 < > pan2...@intel.c

Re: [PATCH] RISC-V: Fix warning in predicated.md

Ok 於 2023年6月2日 週五 11:05 寫道： > From: Juzhe-Zhong > > Notice there is warning in predicates.md: > ../../../riscv-gcc/gcc/config/riscv/predicates.md: In function ‘bool > arith_operand_or_mode_mask(rtx, machine_mode)’: > ../../../riscv-gcc/gcc/config/riscv/predicates.md:33:14: warning: > comparison

Re: [PATCH] RISC-V: Optimize reverse series index vector

LGTM On Fri, Jun 2, 2023 at 2:32 PM wrote: > > From: Juzhe-Zhong > > This patch optimizes the following seriese vector: > [nunits - 1, nunits - 2, , 0] > > Before this patch: > vid > vmul > vadd > > After this patch: > vid > vrsub > > This patch is an obvious and simple optimization, ok for

Re: [PATCH V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid

LGTM, thanks for fixing this :) On Fri, Jun 2, 2023 at 10:05 AM wrote: > > From: Juzhe-Zhong > > Base on these: > https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232 > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233 > > Add _mu C++ overloaded intrinsics for load && viota &&

Re: Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations

Lgtm, thanks:) juzhe.zh...@rivai.ai 於 2023年6月2日 週五 15:20 寫道： > Thanks. I am gonna wait for Jeff or Kito final approve. > > -- > juzhe.zh...@rivai.ai > > > *From:* Robin Dapp > *Date:* 2023-06-02 15:18 > *To:* juzhe.zh...@rivai.ai; gcc-patches > *CC:* rdapp.gcc ; kit

Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM Li, Pan2 via Gcc-patches 於 2023年6月4日 週日 08:36 寫道： > Great! Thanks Juzhe and let’s wait kito’s approval. > > Pan > > From: 钟居哲 > Sent: Sunday, June 4, 2023 7:36 AM > To: Li, Pan2 ; gcc-patches > Cc: kito.cheng ; Li, Pan2 ; > Wang, Yanzhang > Subject: Re: [PATCH] RISC-V: Support RVV zvfh{m

Re: [NFC] RISC-V: Move optimization patterns into autovec-opt.md

Lgtm 於 2023年6月4日 週日，17:37寫道： > From: Juzhe-Zhong > > Move all optimization patterns into autovec-opt.md to make organization > easier maintain. > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md (*not): Move to > autovec-opt.md. > (*n): Ditto. > * config/riscv/autovec.m

Re: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

LGTM too, thanks On Sun, Jun 4, 2023 at 3:36 PM 钟居哲 wrote: > > LGTM. > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-04 15:19 > To: gcc-patches > CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang > Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API > From: Pan Li >

Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp

Only a few minor comments, otherwise LGTM :) But I guess we need to wait until binutils merge zc stuff. > Zcmp can share the same logic as save-restore in stack allocation: > pre-allocation > by cm.push, step 1 and step 2. > > please be noted cm.push pushes ra, s0-s11 in reverse order than what

Re: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.

LGTM On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai wrote: > > Thanks for catching this. > LGTM. > > > > juzhe.zh...@rivai.ai > > From: Li Xu > Date: 2023-06-05 16:18 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode

Re: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API

LGTM too, thanks :) On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai wrote: > > LGTM, > > > juzhe.zh...@rivai.ai > > > From: pan2.li > Date: 2023-06-05 16:20 > To: gcc-patches > CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang > Subject: [PATCH v2] RISC-V: S

Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API

> diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index e4f2ba90799..c338e3c9003 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [ > ]) > (define_mod

Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API

OK for landing this patch first, and fix by follow up patches. On Tue, Jun 6, 2023 at 9:41 AM juzhe.zh...@rivai.ai wrote: > > I think we should split instructions pattern which belongs to ZVFHMIN. > And add ZVFH gating into all original iterator for example: VF VWFetc. > > ___

Re: [PATCH V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization

LGTM, we would like to improve that on the combine pass, but it could be improved later. On Tue, Jun 6, 2023 at 8:04 PM wrote: > > From: Juzhe-Zhong > > Fix according to comments from Robin of V1 patch. > > This patch add combine optimization for following case: > __attribute__ ((noipa)) void >

Re: [PATCH] RISC-V: Fix ICE when include riscv_vector.h with rv64gcv

lgtm, thanks for fixing this :) On Wed, Jun 7, 2023 at 10:19 AM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to fix the incorrect requirement of the vector > builtin types for the ZVFH/ZVFHMIN extension. The incorrect requirement > will result in the ops mismatch with

Re: [PATCH] RISC-V: Support RVV VLA SLP auto-vectorization

Few comments, but all comments are asking adding more comment :P > @@ -398,6 +410,48 @@ rvv_builder::get_merge_scalar_mask (unsigned int > index_in_pattern) const >return gen_int_mode (mask, inner_int_mode ()); > } > > +/* Return true if the variable-length vector is single step. */ > +bool

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

I would like vendor cpu name start with vendor name, like ventana-veyron-v1 which is consistent with all other vendor cpu, and llvm are using same convention too. Raphael Moreira Zinsly 於 2023年6月7日 週三，21:18寫道： > gcc/ChangeLog: > > * config/riscv/riscv-cores.def: Add veyron-v1 > co

Re: [PATCH v2 0/3] RISC-V: Support ZC* extensions.

Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until binutils part has merged, I know you guys already implement that for a while, so I think it’s almost there :) Jiawei 於 2023年6月7日 週三，20:57寫道： > RISC-V Code Size Reduction(ZC*) extensions is a group of extensions > which def

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

> diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index 7d87ab7ce28..4078439e562 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) > RISCV_TUNE(

Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

I am thinking, is it possible to use mode attr to remove the overhead of checking the mode for other FP modes other than FP16? e.g. (define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [ (VNx1HF "TARGET_ZVFH") ... (VNx1SF "1") ... ]) "TARGET_VECTOR && riscv_vector::float_mode_supported_p (m

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

> On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches < > gcc-patches@gcc.gnu.org> wrote: > > > > diff --git a/gcc/config/riscv/riscv-cores.def > > b/gcc/config/riscv/riscv-cores.def > > > index 7d87ab7ce28..4078439e562 100644 > > > --- a/gcc/con

Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

I like JuZhe's proposal too since it's a less invasive way :) On Thu, Jun 8, 2023 at 9:18 PM Li, Pan2 via Gcc-patches wrote: > > Thanks Juzhe for the idea. It looks work well as we expected, with the > following try. > > > 1. Allow all FP=16 types for vfadd, then _zvfh and _zvfhmin will be OK

Re: [PATCH] RISC-V: Add Veyron V1 pipeline description

> > I'd very much like to see the condops go into GCC as well, but I've been > > hesitant to move it forward myself. We're still waiting on hardware and > > it wasn't clear to me that we really had consensus agreement to move the > > bits forward based on an announcement vs waiting on actual hardw

Re: [PATCH v1] RISC-V: Fix one warning of frm enum.

Lgtm juzhe.zh...@rivai.ai 於 2023年6月9日 週五，16:08寫道： > Ok. > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-09 15:53 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Fix one warning of frm enum. > From: Pan

Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

lgtm too, thanks :) On Fri, Jun 9, 2023 at 3:15 PM juzhe.zh...@rivai.ai wrote: > > LGTM. > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-09 15:07 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng > Subject: [PATCH v10] RISC-V: Refactor

Re: [PATCH v4] RISC-V: Add vector psabi checking.

Hmmm, I still saw some fail on testsuite after applying this patch, most are because the testcase has used vector type as argument or return value, but .. vector-abi-1.c should not fail I think? For other fails, I would suggest you could just add -Wno-psabi to rvv.exp === gcc: Une

Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS

Thankful you send this before weekend, I could run the fuzzy testing during this weekend :P On Fri, Jun 9, 2023 at 6:41 PM wrote: > > From: Juzhe-Zhong > > This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 && > Phase 6 > are quite messy and cause some bugs discovered by my

Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 vreinterpret

LGTM :) On Sat, Jun 10, 2023 at 7:59 AM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to add more tests for RVV FP16 vreinterpret, aka > > vfloat16*_t <==> v{u}int16*_t. > > There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already. > It doesn't bre

Re: [PATCH] RISC-V: Enable select_vl for RVV auto-vectorization

LGTM, thanks for this On Sat, Jun 10, 2023 at 8:42 AM wrote: > > From: Juzhe-Zhong > > Consider this following example: > void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict b, > int N) { > for (long i = 0; i < N; i++) { > c[i] = a[i] + b[i]; > } > }

Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

LGTM juzhe.zh...@rivai.ai 於 2023年6月12日 週一 10:58 寫道： > LGTM. > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-12 10:57 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefine

Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

Lgtm too :) 钟居哲 於 2023年6月12日 週一 05:48 寫道： > LGTM > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-11 08:33 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; > kito.cheng > Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API >

Re: [PATCH V2] RISC-V: Add ZVFHMIN block autovec testcase

LGTM too, thanks On Mon, Jun 12, 2023 at 5:46 PM Robin Dapp via Gcc-patches wrote: > > > +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when > > -march="*zvfhmin*". */ > > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 > > "vect" } } */ > > Thanks

Re: Re: [PATCH] RISC-V: Fix V_WHOLE && V_FRACT iterator requirement

Some more detail here: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616051.html On Mon, Jun 12, 2023 at 5:58 PM juzhe.zh...@rivai.ai wrote: > > I'd like you to defer to you commit my patch with your test (Jeff has > approved my patch, just feel free to commit). > > Here is the descrip

Re: [PATCH v1] RISC-V: Fix one potential test failure for RVV vsetvl

OK for this patch, and I am thinking we should adjust rvv.exp to just exclude -O0, -Os and -Oz for some testcases run to simplify many testcases. On Mon, Jun 12, 2023 at 8:20 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > The test will fail on below command with multi-thread like below.

Re: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization

We have two style predictor for those define_insn_and_split patterns, "TARGET_VECTOR"/"&& can_create_pseudo_p ()" and "TARGET_VECTOR && can_create_pseudo_p ()"/"&& 1", could you unify all to later form? I feel that would be safer since those patterns are really only valid before RA(can_create_pseud

Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hi Yan-Zhang: OK with one minor, go ahead IF the regression is clean. Hi Pan: Could you help to verify this patch and commit if the regression is clean? thanks :) > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > index 5e69235a268..ad79

Re: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization

Yes, change all define_insn_and_split to that style, "TARGET_VECTOR && can_create_pseudo_p ()"/ "&& 1", my understanding is all those patterns should only work before RA, so all using "TARGET_VECTOR && can_create_pseudo_p ()" is more reasonable. On Mon, Jun 12, 2023 at 8:41 PM juzhe.zh...@rivai.a

Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API

lgtm On Mon, Jun 12, 2023 at 3:43 PM juzhe.zh...@rivai.ai wrote: > > LGTM > > > > juzhe.zh...@rivai.ai > > From: pan2.li > Date: 2023-06-12 15:40 > To: gcc-patches > CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng > Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vge

Re: [PATCH v5] RISC-V: Add vector psabi checking.

How about appending to DEFAULT_CFLAGS? On Mon, Jun 12, 2023 at 9:38 PM Wang, Yanzhang via Gcc-patches wrote: > > I found that add the -Wno-psabi to CFLAGS will be overrode by > dg-options. It seems we can only add this option to the third > arg of dg-runtest. Attach the dg-runtest comments, > > #

Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hmmm, yeah, I think let's add it case by case...I assume we should get it rid before GCC 14, it is mostly used for the transition period before we settle down the ABI and for GCC 13. On Mon, Jun 12, 2023 at 10:34 PM Jeff Law wrote: > > > > On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote: >

Re: Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation

I didn't take a close review yet, (and I suspect I can't find time before I start my vacation :P), but I am thinking we may adding selftests for expand_const_vector in *future*, again, not blocker for this patch :) On Mon, Jun 12, 2023 at 10:51 PM 钟居哲 wrote: > > No. Such pattern you pointed I alr

Re: [PATCH 3/4] [RISC-V] resolve confilct between zcmp multi push/pop and shrink-wrap-separate

I would suggest breaking this patch into two parts: RISC-V part and the rest part (shrink-wrap.h / shrink-wrap.cc). On Wed, Jun 7, 2023 at 1:55 PM Fei Gao wrote: > > Disable zcmp multi push/pop if shrink-wrap-separate is active. > > So in -Os that prefers smaller code size, by default shrink-wra

Re: [PATCH 1/1] riscv: thead: Fix ICE when enable XTheadMemPair ISA extension.

Hi Xianmiao: > Hi Christoph and Kito, > > That's great that this bug has been resolved. If you merge this patch, > it would be best to also merge it to the gcc-13 branch. Yeah, that sounds reasonable, and the convention for backport is waiting 1 week to make sure it's stable, so will backport th

Re: [PATCH 1/1] riscv: thead: Fix ICE when enable XTheadMemPair ISA extension.

Yeah, I've applied patches on my local tree and running the testsuite. On Wed, Jul 12, 2023 at 3:11 PM Philipp Tomsich wrote: > > Looks like I missed the OK on this one. > I can pick it up today, unless you Kito already has it in flight? > > Thanks, > Philipp. > > On Tue, 11 Jul 2023 at 17:51, Ki

Re: [PATCH] RISC-V: Support integer mult highpart auto-vectorization

LGTM, thanks:) 於 2023年7月12日 週三 16:40 寫道： > From: Ju-Zhe Zhong > > This patch is adding an obvious missing mult_high auto-vectorization > pattern. > > Consider this following case: > #define DEF_LOOP(TYPE) \ > void __attribute__ ((noipa))\ > mod_##TYP

Re: [PATCH] riscv: thead: Fix failing XTheadCondMov tests (indirect-rv[32|64])

Ok Philipp Tomsich 於 2023年7月12日 週三，22:08寫道： > On Wed, 12 Jul 2023 at 16:05, Jeff Law wrote: > > > > > > > On 7/12/23 06:48, Christoph Müllner wrote: > > > On Wed, Jul 12, 2023 at 4:05 AM Jeff Law > wrote: > > >> > > >> > > >> > > >> On 7/10/23 22:44, Christoph Muellner wrote: > > >>> From: Chri

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Li, Pan2 via Gcc-patches 於 2023年7月12日 週三，15:07寫道： > Thank Juzhe for review. Sure, let me hold the v3 for kito's comments. > > Pan > > From: juzhe.zh...@rivai.ai > Sent: Wednesday, July 12, 2023 2:11 PM > To: Li, Pan2 ; gcc-patches > Cc: Robin Dapp ; jeffreyalaw ; > Li, Pan2 ; Wang, Yanzhang ; >

Re: [PATCH v1] RISC-V: Add more tests for RVV floating-point FRM.

Pan Li via Gcc-patches 於 2023年7月12日 週三，23:07寫道： > From: Pan Li > > Add more test cases include both the asm check and run for RVV FRM. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. > * gcc.target/risc

Re: [PATCH] RISC-V: Throw compilation error for unknown sub-extension or supervisor extension

That's intentional before, since some time binutils may have supported that but the compiler doesn't, so GCC just bypasses that to binutils to let binutils reject those unknown extensions. But I am considering rejecting those extensions or adding more checks on the GCC side recently too, because a

Re: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM.

LGTM 於 2023年7月13日 週四 13:10 寫道： > From: Pan Li > > Add more test cases include both the asm check and run for RVV FRM. > > Signed-off-by: Pan Li > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. > * gcc.target/riscv/rvv/base/floa

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Hmmm? I didn't get that error on selftest? my diff with your v2: $ git diff diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 12655f7fdc65..466e1aed91c7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8058,8 +8058,9 @@ asm_insn_p (rtx_insn *insn)

Re: [PATCH] Add VXRM enum

Those enum values have been defined via `#pragma riscv intrinsic "vector"` :) https://github.com/gcc-mirror/gcc/commit/01d62e9b6c3e9fd3132f1616843103ccf81778ed On Thu, Jul 13, 2023 at 2:55 PM Robin Dapp via Gcc-patches wrote: > > > +enum __RISCV_VXRM { > > + __RISCV_VXRM_RNU = 0, > > + __RISCV

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

oh, I know why you failed on that, you need to put it within the function, not global static, function static variable will construct when first invoked rather than construct at program start. Could you try to apply my diff in the last mail and try again? On Thu, Jul 13, 2023 at 3:29 PM Li, Pan2

Re: [PATCH 4/4] [RISC-V] support cm.mva01s cm.mvsa01 in zcmp

LGTM, thanks, just like other zc* patches, I would like to defer this until the binutils part landed :) On Wed, Jun 7, 2023 at 1:54 PM Fei Gao wrote: > > From: Die Li > > Signed-off-by: Die Li > Co-Authored-By: Fei Gao > > gcc/ChangeLog: > > * config/riscv/peephole.md: New pattern. >

Re: [PATCH 2/4] [RISC-V] support cm.popretz in zcmp

I was thinking does it possible to using peephole2 to optimize this case, but I realized their is several barrier, like stack tie and note...so it seems hard to just leverage peephole2. And the patch is LGTM, only a few minor coding format issues, but you don't need to send new patch, I can fix th

Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM

Hmmm, anyway, I guess it's not worth spending any more of your time, LGTM for v3 :) On Thu, Jul 13, 2023 at 5:10 PM Li, Pan2 via Gcc-patches wrote: > > It can pass the selftest with below diff based on v3, but got ICE when build > newlib. > > /home/pli/repos/gcc/222/riscv-gnu-toolchain/newlib/n

Re: Re: [PATCH] RISC-V: Enable COND_LEN_FMA auto-vectorization

I didn’t try on local yet, but it sounds like …the code size might larger than normal case? juzhe.zh...@rivai.ai 於 2023年7月13日 週四，19:50寫道： > Could you tell me how to add the comment? > I am not familiar with link/binutils stuff. > > -- > juzhe.zh...@rivai.ai > > > *From

Re: [PATCH] RISC-V: Remove the redundant expressions in the and3.

Expanding without DONE or FAIL will leave the pattern as well, so this patch is fine IMO, so this patch LGTM, but anyway I will test this and commit if passed :) On Fri, Jul 14, 2023 at 10:34 AM Palmer Dabbelt wrote: > > On Thu, 13 Jul 2023 19:02:05 PDT (-0700), li...@eswincomputing.com wrote: >

Re: [PATCH 1/2] RISC-V: Recognized zihintntl extensions

Committed, thanks :) On Thu, Jul 13, 2023 at 1:39 PM Monk Chiang via Gcc-patches wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: > (riscv_implied_info): Add zihintntl item. > (riscv_ext_version_table): Ditto. > (riscv_ext_fl

Re: [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch

Corresponding PR on c-api-doc under discussion, so defer this until that settles down :) https://github.com/riscv-non-isa/riscv-c-api-doc/pull/46 On Thu, Jul 13, 2023 at 1:40 PM Monk Chiang via Gcc-patches wrote: > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_print_operand

Re: [PATCH] RISC-V: Remove the redundant expressions in the and3.

Committed :) Jeff Law via Gcc-patches 於 2023年7月14日 週五 10:52 寫道： > > > On 7/13/23 20:41, Kito Cheng via Gcc-patches wrote: > > Expanding without DONE or FAIL will leave the pattern as well, so this > > patch is fine IMO, so this patch LGTM, but anyway I will test this and

Re: [PATCH V2] RISC-V: Enable COND_LEN_FMA auto-vectorization

LGTM Robin Dapp via Gcc-patches 於 2023年7月14日 週五 15:05 寫道： > Hi Juzhe, > > thanks, looks good to me now - did before already actually ;). > > Regards > Robin >

Re: [PATCH] RISC-V: Support non-SLP unordered reduction

於 2023年7月14日 週五 20:31 寫道： > From: Ju-Zhe Zhong > > This patch add reduc_*_scal to support reduction auto-vectorization. > > Use COND_LEN_* + reduc_*_scal to support unordered non-SLP > auto-vectorization. > > Consider this following case: > int __attribute__((noipa)) > and_loop (int32_t * __rest

Re: [PATCH] RISC-V: Add TARGET_MIN_VLEN > 4096 check

On Mon, Jul 17, 2023 at 2:05 PM Juzhe-Zhong wrote: > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_option_override): Report ERROR for > TARGET_MIN_VLEN > 4096 > > --- > gcc/config/riscv/riscv.cc | 8 > 1 file changed, 8 insertions(+) > > diff --git a/gcc/config/riscv/riscv

Re: [PATCH] RISC-V: Support non-SLP unordered reduction

> @@ -247,6 +248,7 @@ void emit_vlmax_cmp_mu_insn (unsigned, rtx *); > void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); > void emit_scalar_move_insn (unsigned, rtx *); > void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); > +//void emit_vlmax_reduction_insn (unsigned, rtx *); Plz

Re: [PATCH] riscv: Fix warning in riscv_regno_ok_for_index_p

pushed, thanks :) On Mon, Jul 17, 2023 at 4:59 PM Christoph Muellner wrote: > > From: Christoph Müllner > > The variable `regno` is currently not used in riscv_regno_ok_for_index_p(), > which triggers a compiler warning. Let's address this. > > Fixes: 423604278ed5 ("riscv: Prepare backend for in

Re: [PATCH V2] RISC-V: Support non-SLP unordered reduction

LGTM, thanks :) On Mon, Jul 17, 2023 at 4:20 PM Juzhe-Zhong wrote: > > This patch add reduc_*_scal to support reduction auto-vectorization. > > Use COND_LEN_* + reduc_*_scal to support unordered non-SLP auto-vectorization. > > Consider this following case: > int __attribute__((noipa)) > and_loop

Re: [PATCH] RISC-V: Ensure all implied extensions are included[PR110696]

LGTM, thanks for the patch :) On Mon, Jul 17, 2023 at 5:53 PM Lehua Ding wrote: > > Hi, > > This patch fix target/PR110696, recursively add all implied extensions. > > Best, > Lehua > > PR target/110696 > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc > (riscv_subset_

Re: [PATCH] RISC-V: Dynamic adjust size of VLA vector according to TARGET_MIN_VLEN

LGTM, thanks:) Juzhe-Zhong 於 2023年7月18日 週二 14:28 寫道： > This patch is to dynamic adjust size of VLA vectors according to > TARGET_MIN_VLEN (-march=*zvl*b). > > Currently, VNx16QImode is always [16,16] when TARGET_MINV_LEN >= 128. > > We are going to add a bunch of VLS modes (V16QI,V32QI,etc),

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