> diff --git a/gcc/config/riscv/vector-iterators.md > b/gcc/config/riscv/vector-iterators.md > index e4f2ba90799..c338e3c9003 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [ > ]) > (define_mode_iterator VWF [ > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16") > + (VNx8HF "TARGET_VECTOR_ELEN_FP_16") > + (VNx16HF "TARGET_VECTOR_ELEN_FP_16") > + (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > + (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
I am little concern about using TARGET_VECTOR_ELEN_FP_16 as predictor here, zvfhmin also set TARGET_VECTOR_ELEN_FP_16 flag, so it means zvfhmin also enabled reduction? and also has the same concern for V and VF in the last patch[1] too. [1] https://patchwork.sourceware.org/project/gcc/patch/20230605082043.1707158-1-pan2...@intel.com/ Give a more practical example to explain my concern: We've using V and VF iterators in autovec.md, and zvfhmin will set MASK_VECTOR_ELEN_FP_16 which means zvfhmin WILL enable most autovec patterns with fp16, that should not what we expected to do I think?
