OK for landing this patch first, and fix by follow up patches.
On Tue, Jun 6, 2023 at 9:41 AM juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> wrote: > > I think we should split instructions pattern which belongs to ZVFHMIN. > And add ZVFH gating into all original iterator for example: VF VWF....etc. > > ________________________________ > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2023-06-06 09:32 > To: juzhe.zh...@rivai.ai > CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang > Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction > floating-point intrinsic API > > diff --git a/gcc/config/riscv/vector-iterators.md > > b/gcc/config/riscv/vector-iterators.md > > index e4f2ba90799..c338e3c9003 100644 > > --- a/gcc/config/riscv/vector-iterators.md > > +++ b/gcc/config/riscv/vector-iterators.md > > @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [ > > ]) > > (define_mode_iterator VWF [ > > + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") > > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx4HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx8HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx16HF "TARGET_VECTOR_ELEN_FP_16") > > + (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") > > + (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") > > I am little concern about using TARGET_VECTOR_ELEN_FP_16 as predictor here, > zvfhmin also set TARGET_VECTOR_ELEN_FP_16 flag, > so it means zvfhmin also enabled reduction? > > and also has the same concern for V and VF in the last patch[1] too. > > [1] > https://patchwork.sourceware.org/project/gcc/patch/20230605082043.1707158-1-pan2...@intel.com/ > > Give a more practical example to explain my concern: > > We've using V and VF iterators in autovec.md, and zvfhmin will set > MASK_VECTOR_ELEN_FP_16 > which means zvfhmin WILL enable most autovec patterns with fp16, > that should not what we expected to do I think? >
