Re: [PATCH] Extend nops num in "maybe_gen_insn" for RISC-V Vector intrinsics

Committed to trunk, thanks :) On Wed, Mar 8, 2023 at 3:49 PM Richard Biener wrote: > > On Wed, 8 Mar 2023, juzhe.zh...@rivai.ai wrote: > > > From: Ju-Zhe Zhong > > > > Hi, current maybe_gen_insn can only expand 9 nops. > > For RVV intrinsics, I need to extend it as 10, otherwise I should use >

Re: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics.

IIRC the canonical form of (plus (op) (mult (op) (op))) is (plus (mult (op) (op) (op)), so using the first form might not friendly for the combine pass. On Tue, Mar 14, 2023 at 10:24 AM wrote: > > From: Ju-Zhe Zhong > > Co-authored-by: kito-cheng > Co-authored-by: kito-cheng

Re: [PATCH v4 1/2] RISC-V: Avoid calloc() poisoning on musl

committed to trunk, thanks :) On Tue, Mar 14, 2023 at 9:44 PM Kito Cheng wrote: > > RISC-V part is ok, and I assume you didn't have write access so I'm > gonna push that since the system.h change also got approved :) > > On Tue, Mar 14, 2023 at 5:07 PM Richard Biener

Re: [PATCH v4 1/2] RISC-V: Avoid calloc() poisoning on musl

RISC-V part is ok, and I assume you didn't have write access so I'm gonna push that since the system.h change also got approved :) On Tue, Mar 14, 2023 at 5:07 PM Richard Biener via Gcc-patches wrote: > > On Tue, Mar 14, 2023 at 1:24 AM Sam James via Gcc-patches > wrote: > > > > This fixes error

Re: [PATCH v4 2/2] gcc: Drop obsolete INCLUDE_PTHREAD_H

Can you take a look at this? > > > juzhe.zh...@rivai.ai > > From: Sam James > Date: 2023-03-14 08:23 > To: gcc-patches > CC: Kito Cheng; Palmer Dabbelt; Andrew Waterman; Jim Wilson; Ju-Zhe Zhong; > Sam James > Subject: [PATCH v4 2/2] gcc: Drop obsolet

Re: [PATCH] RISC-V: Fix reg order of RVV registers.

...@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > Co-authored-by: kito-cheng > > Co-authored-by: kito-cheng > > > > Consider this case: > > void f19 (void *base,void *base2,void *out,size_t vl, int n) > > { > > vuint64m8_t bindex = __riscv

Re: Re: [PATCH V2] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT

stcases the reason I added -fno-vect-cost-model > here is > because we don't have enough patterns to enable some auto-vectorizations. > I add -fno-vect-cost-model to force enable auto-vectorizations for such > cases for testing. > > > > juzhe.zh...@rivai.ai > >

Re: [PATCH] RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]

Thanks, pushed to trunk. On Tue, May 9, 2023 at 10:20 AM wrote: > > From: Juzhe-Zhong > > This patch is fix dead loop in vsetvl intrinsic avl checking. > > vsetvli->get_def () has vsetvli->get_def () has vsetvli. > Then it will keep looping in the vsetvli avl checking which is a dead loop. >

Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.

Committed, thanks for catching this issue :) On Wed, May 10, 2023 at 12:08 PM juzhe.zh...@rivai.ai wrote: > > LGTM. Let's wait for kito's feedback. > Thanks :) > > > > juzhe.zh...@rivai.ai > > From: Li Xu > Date: 2023-05-10 12:02 > To: gcc-patches > CC: kito.cheng; palmer; juzhe.zhong; Li Xu > Su

Re: [PATCH] RISC-V: Support const series vector for RVV auto-vectorization

O > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index c0293a306f9..e8a728ae226 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -219,6 +219,7 @@ rtx gen_avl_for_scalar_move (rtx); > void expand_tuple_move (machine_mode

Re: [PATCH] riscv: Add autovectorization tests for binary integer

Don't forgot to add Michael to co-author, you can added by following line: Co-authored-by: Michael Collison And GCC's changelog generating script will recognize that and generate the right thing for that :)

Re: [PATCH] riscv: Clarify vlmax and length handling.

LGTM, and just one nit, use RISC-V in the title would be better since Palmer's patchwork filter is set to "RISC-V", so using "riscv:" might be missed during patchwork review meeting :P On Thu, May 11, 2023 at 2:54 AM Palmer Dabbelt wrote: > > On Wed, 10 May 2023 11:50:32 PDT (-0700), rdapp@g

[committed v2] RISC-V: Support const series vector for RVV auto-vectorization

From: Juzhe-Zhong Off line discussed with Ju-Zhe, and send and committed by me because he got some network issue. V2 Changes: - Code restructure and rename emit_indexop to emit_index_op. - Minor comment tweak. -- This patch is the prerequiste patch for more RVV auto-vectorization support. S

Re: [PATCH v2] RISC-V: Add autovectorization tests for binary integer, operations.

LGTM juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:36 寫道： > LGTM. Plz commit it now. Then I can rebase vec_init patch. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:27 > To: Kito Cheng; Palmer Dabbelt > CC: gcc-patches; juzhe.zhong; collison; je

Re: [PATCH v2] RISC-V: Clarify vlmax and length handling.

LGTM juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:36 寫道： > LGTM. Plz commit it now. Then I can rebase vec_init patch. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:29 > To: Kito Cheng; Palmer Dabbelt > CC: gcc-patches; juzhe.zhong; collison; je

Re: Re: [PATCH v2] RISC-V: Add vectorized binops and insn_expander helpers.

LGTM for v2 as well :) juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:39 寫道： > I just saw Kito has LGTM in V1 patch. > Let's wait for Kito LGTM for V2. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:36 > To: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; collison; palmer; > jef

Re: [PATCH v2] RISC-V: Split off shift patterns for autovectorization.

Thanks, LGTM juzhe.zh...@rivai.ai 於 2023年5月11日 週四 18:37 寫道： > LGTM. Plz commit it now. Then I can rebase vec_init patch. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-11 18:33 > To: Palmer Dabbelt > CC: gcc-patches; juzhe.zhong; Kito Cheng; co

Re: [PATCH v2] RISC-V: Allow vector constants in riscv_const_insns.

LGTM, thanks :) On Thu, May 11, 2023 at 8:47 PM Robin Dapp wrote: > > > OK, you can go ahead commit patch. I am gonna send another patch to > > fix this. > I agree that we should handle more constants but I'd still rather go > ahead now and fix things later. The patch is more about the test > ra

Re: [PATCH v2] RISC-V: Add vector_scalar_shift_operand

LGTM, thanks :) Palmer Dabbelt 於 2023年5月12日 週五 06:32 寫道： > The vector shift immediates happen to have the same constraints as some > of the CSR-related operands, but it's a different usage. This adds a > name for them, so I don't get confused again next time. > > gcc/ChangeLog: > > * co

Re: [PATCH] RISC-V: Reorganize binary autovec testcases

OK On Fri, May 12, 2023 at 9:03 AM wrote: > > From: Juzhe-Zhong > > 1. This patch is moving binary autovec testcases into binop directory to make > it > easier to maintain. > > 2. Current binary autovec only tested in LMUL = 1, enable testing in LMUL = > 2/4/8. > > Tested on both rv32/rv64, wi

Re: [PATCH] RISC-V: Fix RVV binary auto-vectorizaiton test fails

ok, thanks :) On Fri, May 12, 2023 at 9:04 AM juzhe.zh...@rivai.ai wrote: > > This patch has tested on both RV32/RV64, and all fails in RVV are cleaned up. > Ok for trunk? > > > > juzhe.zh...@rivai.ai > > From: juzhe.zhong > Date: 2023-05-12 07:29 > To: gcc-patches > CC: kito.cheng; palmer; jeffr

Re: [PATCH V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization

> This patch makes vec_init support common init vector handling (using > vslide1down to insert element) > which can handle any cases of initialization vec but it's not optimal for > cases. > > And support Case 1 optimizaiton: > https://godbolt.org/z/Yb9PK9jsz Don't use godbolt link in comment, b

Re: [PATCH V3] RISC-V: Add basic vec_init for VLS RVV auto-vectorization

Ok 於 2023年5月12日 週五 10:57 寫道： > From: Juzhe-Zhong > > #include > > typedef int8_t vnx16qi __attribute__((vector_size (16))); > > #include > > typedef int8_t vnx16qi __attribute__ ((vector_size (16))); > typedef int8_t vnx32qi __attribute__ ((vector_size (32))); > typedef int8_t vnx64qi __attri

Re: [PATCH] RISC-V: Fix fail of vmv-imm-rv64.c in rv32

ok On Fri, May 12, 2023 at 11:11 AM wrote: > > From: Juzhe-Zhong > > After update local codebase to the trunk. I realize there is one more fail in > RV32. > After this patch, all fails of RVV are cleaned up. > Thanks. > > FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize (t

Re: [PATCH] RISC-V: Fix RVV binary auto-vectorizaiton test fails

We would like users to explicitly set that, so that implication rule won't screw anything up or unexpect -mabi, that's kind of the conclusion of most RISC-V GCC maintainers (Palmer/Jim Willsom/me). Also the behavior is there for years, we don't want to make surprise to user for the behavior change

[committed] RISC-V: Suppress unused parameter warning in riscv-common.cc

gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): Drop unused parameter. (riscv_select_multilib): Ditto. (riscv_compute_multilib): Update call site of riscv_select_multilib_by_abi and riscv_select_multilib_by_abi. --- gcc/

Re: [PATCH v2] RISC-V: Handle multi-lib path correclty for linux

Apologize for that... fixed on top of trunk: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=7a7f6b26259d22115ee4813ce130622ad1073d16 On Fri, May 12, 2023 at 4:36 PM Andreas Schwab wrote: > > WTF? > > ../../gcc/common/config/riscv/riscv-common.cc: In function 'const char* > riscv_select_multilib_

[committed v4] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743]

V4 Changes: - Use different approach of V3. - Rewrite local_eliminate_vsetvl_insn to unify the optimization flow. - Also improve few more case. Off list discussed and reviewed by Ju-Zhe. --- This issue happens is because we are currently very conservative in opti

[PATCH] RISC-V: Improve vector_insn_info::dump for LMUL and policy

Convert vlmul and policy to human readable string, some example below: Before: [VALID,Demand field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)} AVL=(reg:DI 0 zero) SEW=16,VLMUL=3,RATIO=2,TAIL_POLICY=1,MASK_POLICY=1] ^

Re: [PATCH V2] RISC-V: Using merge approach to optimize repeating sequence in vec_init

two minor comments: > + void add_ta_policy_operand (enum tail_policy vta) > + void add_ma_policy_operand (enum mask_policy vma) You could just named as add_policy_operand since the arugment type is already sufficient to distinguish. > @@ -84,40 +92,52 @@ public: > add_input_operand (gen_i

Re: [PATCH V4] RISC-V: Using merge approach to optimize repeating sequence in vec_init

> +/* Get the mask for merge approach. > + > + Consider such following case: > + {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b} > + To merge "a", the mask should be 1010 > + To merge "b", the mask should be 0101 > +*/ > +rtx > +rvv_builder::get_merge_mask_bitfield (unsig

Re: [PATCH] RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization

Hmmm here is alternative approach for this: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index b8dc333f54e1..c88056024e7d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -50,6 +50,21 @@ using namespace riscv_vector; namespace riscv_vector {

[committed] RISC-V: Pull out function call with side effect from gcc_assert.

It will broken when release mode. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns): Pull out function call from the gcc_assert. --- gcc/config/riscv/riscv-vsetvl.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/ri

Re: [PATCH] RISC-V: Improve vector_insn_info::dump for LMUL and policy

committed to trunk. On Sat, May 13, 2023 at 1:13 AM Jeff Law via Gcc-patches wrote: > > > > On 5/12/23 07:32, Kito Cheng via Gcc-patches wrote: > > Convert vlmul and policy to human readable string, some example below: > > > > Before: > > [VALID,Demand >

Re: [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits

Hi Pan: Tried this patch and I ran into some issues, some variables are using unsigned char to hold machine mode and will have problems when the number of modes is larger than 255... And here is the fix: diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc index 715787b8f483..55ac2adb5596 100644 ---

Re: [PATCH] RISC-V: Refactor the or pattern to switch cases

OK, thanks :) On Sun, May 14, 2023 at 4:22 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch refactor the pattern A or B or C or D, to the switch case for > easy add/remove new types, as well as human reading friendly. > > Before this patch: > return A || B || C || D; > > After th

Re: [PATCH] RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of RVV auto-vectorization

> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index de578b5b899..a5776a550b2 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -7499,6 +7499,24 @@ riscv_preferred_simd_mode (scalar_mode mode) >return word_mode; > } > +/* Implement target ho

Re: Re: [PATCH] RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of RVV auto-vectorization

On Mon, May 15, 2023 at 10:48 AM juzhe.zh...@rivai.ai wrote: > > Oh, I see. I try this way: > static poly_uint64 > riscv_vectorize_preferred_vector_alignment (const_tree type) > { > if (riscv_v_ext_vector_mode_p (TYPE_MODE (type))) > return TYPE_ALIGN (TREE_TYPE (type)); > return TYPE_ALIG

Re: [PATCH V2] RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of both VLA && VLS auto-vectorization.

LGTM 於 2023年5月15日 週一 11:16 寫道： > From: Juzhe-Zhong > > This patch optimizes both RVV VLA && VLS vectorization. > > Consider this following case: > void __attribute__((noinline, noclone)) > f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int > count) > { > for (int i = 0;

Re: [PATCH] RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of RVV auto-vectorization

> we need to discern what we want to achieve here. The goal might > be to prevent the vectorizer from performing peeling or versioning > for alignment. I realize the peeling code looks ugly but it's > actually for a good cause when the target does not support > misaligned vector access or only wi

Re: [PATCH v2] RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization

vse8.v v1,0(a2) > ret > > After this patch: > f_vnx2qi: > vsetivlizero,2,e8,mf8,ta,ma > vmv.v.x v1,a0 > vslide1down.vx v1,v1,a1 > vse8.v v1,0(a2) > ret > > Signed-off-by: Pan Li > Co-authored-b

Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions

LGTM 於 2023年5月15日 週一，19:50寫道： > From: Juzhe-Zhong > > This patch is adding rounding mode operand and FRM_REGNUM dependency > into floating-point instructions. > > The floating-point instructions we added FRM and rounding mode operand: > 1. vfadd/vfsub > 2. vfwadd/vfwsub > 3. vfmul > 4. vfdiv > 5

Re: Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions

Oh, Craig says vfrsqrt7.v not have frm but vsqrt.v have frm, and checked spike that match that. On Mon, May 15, 2023 at 9:55 PM 钟居哲 wrote: > > I don't know why we should not add frm vfsqrt.v since I saw topper (LLVM > maintainer) said we should > not add frm into vsqrt.v. Maybe kito knows the re

Re: Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions

nd V2 :) On Mon, May 15, 2023 at 10:12 PM 钟居哲 wrote: > > Oh, do you mean vfsqrt7/vfrec7 doesn't have frm, but vfsqrt/vfneg should have > frm. > Is that rigth? If yes, I am gonna send a patch to fix it immediately. > > > > juzhe.zh...@rivai.ai > > From: Kito C

Re: Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions

j/vfsgnjx > vfneg.v vd,vs = vfsgnjn.vv vd,vs,vs > vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs > > That's all questions I have, plz double check for me. > Thanks. > > > juzhe.zh...@rivai.ai > > From: Kito Cheng > Date: 2023-05-15 22:22 > To: 钟居哲 > CC: Jeff Law; g

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

zfa requires/depend f, it means zfa implies f in current toolchain implementation, could you add that into riscv-common.cc? Also that means zfa is exclusive with Z[FDH]INX. Ref: https://github.com/riscv/riscv-isa-manual/issues/1020 On Tue, May 16, 2023 at 3:06 PM jinma wrote: > > On 5/15/23 07:

[committed] RISC-V: Fix wrong select_kind in riscv_compute_multilib

Seems like I screw up bare-metal toolchian multi lib selection during finxing linux multi-lib selction... gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix wrong select_kind... --- gcc/common/config/riscv/riscv-common.cc | 6 +++--- 1 file changed

Re: Re: RISC-V Test Errors and Failures

Currently we are highly rely on simulator can setup correctly by ELF attribute or -march setting, but seems not true for everyone, for longer term we need something like check_effective_target_aarch64_sve_hw, but as Palmer point out, we might need...bunch of that for different extensions On We

Re: Re: RISC-V Test Errors and Failures

Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 On Wed, May 17, 2023 at 10:20 AM Kito Cheng wrote: > > Currently we are highly rely on simulator can setup correctly by ELF > attribute or -march setting, but

Re: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics

I would like to defer this until the PR has updated. On Wed, May 17, 2023 at 9:52 AM wrote: > > From: Juzhe-Zhong > > Hi, since fixed-point with modeling rounding mode intrinsics are coming: > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 > > I am adding vxrm rounding mode enum to

Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

> + > +/* Get the mask for merge approach. > + > + Consider such following case: > + {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b} > + To merge "a", the mask should be 1010 > + To merge "b", the mask should be 0101 > +*/ > +rtx > +rvv_builder::get_merge_mask_bitfield (u

Re: RISC-V Test Errors and Failures

> diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > index 94d6ec5..efc3a80 100755 > --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > @@ -12,4 +12,4 @@ done >

Re: Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

On Wed, May 17, 2023 at 11:36 AM juzhe.zh...@rivai.ai wrote: > > >> Does it means we assume inner_int_mode is DImode? (because sizeof > >> (uint64_t)) > >> or it should be something like `for (unsigned int i = 0; i < > >> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ? > No, sizeof

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

RISC-V glibc will require corresponding muilti-lib has built there, otherwise will report something like: /usr/include/gnu/stubs.h:11:11: fatal error: gnu/stubs-ilp32d.h: No such file or directory But actually we only require those fixed length types to compile and scan assembly or dump, So we

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool1_t

ok, and also ok for those small API test in testsuite. On Tue, May 16, 2023 at 9:10 AM Li, Pan2 via Gcc-patches wrote: > > Kindly ping for this PATCH, 😉. > > Pan > > From: Li, Pan2 > Sent: Monday, May 15, 2023 11:25 AM > To: juzhe.zh...@rivai.ai; gcc-patches > Cc: Kito.cheng ; Wang, Yanzhang >

Re: [PATCH] RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions

LGTM, it's really awesome, I know it's kind of blocking due to enum stuff, so feel free to commit this once it unblock :) On Wed, May 17, 2023 at 5:58 PM wrote: > > From: Juzhe-Zhong > > Hi, this patch support the new coming fixed-point intrinsics: > https://github.com/riscv-non-isa/rvv-intrinsi

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

> > RISC-V glibc will require corresponding muilti-lib has built there, > > otherwise will report something like: > > > > /usr/include/gnu/stubs.h:11:11: fatal error: gnu/stubs-ilp32d.h: No > > such file or directory > > > > But actually we only require those fixed length types to compile and > >

Re: [PATCH] RISC-V: Introduce rounding mode operand into fixed-point intrinsics

LGTM, thanks! 钟居哲 於 2023年5月17日 週三，23:02寫道： > Ping this patch which is the prerequisite of this patch: > > https://patchwork.sourceware.org/project/gcc/patch/20230517095818.1285188-1-juzhe.zh...@rivai.ai/ > > which has been approved by kito. > > Is this patch also ok for trunk ? > > Thanks. >

Re: [RFC V2] RISC-V : Support rv64 ilp32

I am concern about we didn't define POINTERS_EXTEND_UNSIGNED here, and also concern about the code model stuffs, I know currently Guo-Ren's implementation is rely on some MMU trick, but I am not sure does it also applicable on embedded applications. > diff --git a/gcc/config/riscv/linux.h b/gcc/c

Re: [PATCH] RISC-V: testsuite: Remove empty *-run-template.h.

LGTM Robin Dapp via Gcc-patches 於 2023年5月19日 週五 19:10 寫道： > Hi, > > this obvious patch removes empty run template files and one redundant > stdio.h include. > > Regards > Robin > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Do not include > .

Re: [PATCH] RISC-V: Allow more loading of const vectors.

LGTM Robin Dapp via Gcc-patches 於 2023年5月19日 週五 19:07 寫道： > Hi, > > this fixes a rebase oversight regarding the loading > of vector constants. Added another test to properly > catch that in the future. > > Regards > Robin > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insn

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool[2-64]_t

Lgtm 於 2023年5月17日 週三，16:14寫道： > From: Pan Li > > This patch support the RVV VREINTERPRET from the int to the > vbool[2|4|8|16|32|64]_t. Aka: > > vbool[2|4|8|16|32|64]_t __riscv_vreinterpret_x_x(v{u}int[8|16|32|64]_t); > > These APIs help the users to convert vector LMUL=1 integer to > vbool[2-6

[PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp

Hi Vineet: Could you help to test this patch, this could resolve that issue on our machine, but I would like to also work for other env. Thanks :) --- We got bunch of following error message for multi-lib run: ERROR: torture-init: torture_without_loops is not empty as expected ERROR: tcl error

Re: [PATCH] RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc

LGTM On Mon, May 22, 2023 at 3:20 PM wrote: > > From: Juzhe-Zhong > > Since satisfies_constraint_vi (x) belongs to RVV region. > We make this condition inside riscv_v_ext_vector_mode_p to make codes > more reasonable. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_const_insns): Re

Re: [PATCH] RISC-V: Implement autovec abs, vneg, vnot.

So I expect you will also apply those refactor on Juzhe's new changes? If so I would like to have a separated NFC refactor patch if possible. e.g. Juzhe's vec_cmp/vcond -> NFC refactor patch -> abs, vneg, vnot On Mon, May 22, 2023 at 4:59 PM Robin Dapp wrote: > > As discussed with Juzhe off-list

Re: [PATCH] RISC-V: Add missing torture-init and torture-finish for rvv.exp

Ooops, seems still some issue around here, but I found something might related this issue: https://github.com/gcc-mirror/gcc/commit/d6654a4be3ba44c0d57be7c8a51d76d9721345e1 https://github.com/gcc-mirror/gcc/commit/23c49bb8d09bc3bfce9a08be637cf32ac014de56 On Mon, May 22, 2023 at 2:42 PM Kito

Re: [PATCH] RISC-V: Implement autovec abs, vneg, vnot.

> > So I expect you will also apply those refactor on Juzhe's new changes? > > If so I would like to have a separated NFC refactor patch if possible. > > What's NFC? :) Do you mean to just have the refactor part as a separate > patch? If yes, I agree. NFC: non-functional-change, that's a term us

Re: [PATCH] RISC-V: Fix typo of multiple_rgroup-2.h

ok On Mon, May 22, 2023 at 6:02 PM wrote: > > From: Juzhe-Zhong > > Just notice this following fail in the regression: > FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c (test for > excess errors) > FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c (test for > ex

Re: [PATCH] RISC-V: Add "m_" prefix for private member

LGTM On Mon, May 22, 2023 at 8:10 PM wrote: > > From: Juzhe-Zhong > > Since the current framework is hard to maintain and > hard to be used in the future possible auto-vectorization patterns. > > We will need to keep adding more helpers and arguments during the > auto-vectorization supporting. W

Re: Re: [PATCH] RISC-V: Refactor the framework of RVV auto-vectorization

> ARM uses rtx operands[] in many places and I personally prefer this way since > it will make codes much cleaner. > I dislike the way making the function argument with multiple operand ,like > this: > void func(rtx dest, rtx src1, rtx src2, ) > If we are doing this, we will need to add helper

Re: Re: [PATCH V2] RISC-V: Refactor the framework of RVV auto-vectorization

Lgtm, we can always improve later, I am not intend to block things too :) juzhe.zh...@rivai.ai 於 2023年5月23日 週二 17:46 寫道： > Oh， Thanks. > Let's wait for Kito's final approved. > > > > juzhe.zh...@rivai.ai > > From: Robin Dapp > Date: 2023-05-23 17:44 > To: juzhe.zhong; gcc-patches > CC: rdapp.gcc

Re: [PATCH] RISC-V: Fix incorrect code of touching inaccessible memory address

I am a little hesitant about that, since I feel the vl and normal op should be put in separately, otherwise the means of m_op_num is kind of unclear, we have comments there but I think it's not ideal since it is really context sensitive and hard to determine. And I suspect gcc_assert (ops[m_op_num

Re: [PATCH V2] RISC-V: Fix incorrect code of reaching inaccessible memory address

Lgtm, thanks 於 2023年5月24日 週三，10:39寫道： > From: Juzhe-Zhong > > To fix this issue, we seperate Vl operand and normal operands. > > gcc/ChangeLog: > > * config/riscv/autovec.md: Adjust for new interface. > * config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand. > (e

Re: [PATCH V2] RISC-V: Add RVV comparison autovectorization

> +void > +expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0, > + rtx op1) > ... > + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); > + rtx ops[RVV_CMP_OP + 2] = {target, mask, maskoff, cmp, op0, op1}; > + emit_vlmax_cmp_insn (icode, RVV_CMP_OP + 2, o

Re: [PATCH] RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t

ok On Thu, May 18, 2023 at 2:32 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch support the RVV VREINTERPRET from the vbool*_t to the > vuint*m1_t. Aka: > > vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t); > > These APIs help the users to convert vector the vbool*_t to the LMUL=1

Re: [PATCH v2] RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t

LGTM On Thu, May 18, 2023 at 2:37 PM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch support the RVV VREINTERPRET from the vbool*_t to the > vint*m1_t. Aka: > > vint*m1_t __riscv_vreinterpret_x_x(vbool*_t); > > These APIs help the users to convert vector the vbool*_t to the LMUL=1

Re: [PATCH V5] RISC-V: Add RVV comparison autovectorization

LGTM On Wed, May 24, 2023 at 11:29 AM wrote: > > From: Juzhe-Zhong > > This patch enable RVV auto-vectorization including floating-point > unorder and order comparison. > > The testcases are leveraged from Richard. > So include Richard as co-author. > > And this patch is the prerequisite patch f

Re: [PATCH] RISC-V: Add RVV mask logic auto-vectorization

Just one comment: define_insn_and_split should be used in this scenario rather than define_insn_and_rewrite since you are not really rewriting. You can commit after updating to define_insn_and_split :) On Wed, May 24, 2023 at 3:04 PM wrote: > > From: Juzhe-Zhong > > This patch is adding mask lo

Re: [V2 COMMITTED] RISC-V: Add RVV mask logic auto-vectorization

LGTM, just one comment in git comment, no need v3, just commit with the fix is fine :) On Wed, May 24, 2023 at 3:28 PM wrote: > > From: Juzhe-Zhong > > This patch is adding mask logic auto-vectorization. > define the pattern as "define_insn_and_split" to allow don't forgot to update here ^

Re: Re: [V2 COMMITTED] RISC-V: Add RVV mask logic auto-vectorization

sk logic auto-vectorization. > > define the pattern as "define_insn_and_split" to allow > > >don't forgot to update here ^ > > I notice I missed changeLog here. Is that you want me to fix in the > commit log? > > > > > juzhe.zh...@rivai.ai

Re: [PATCH] RISC-V: Add FRM_ prefix to dynamic rounding mode enum

ok On Wed, May 24, 2023 at 7:20 PM wrote: > > From: Juzhe-Zhong > > An obvious fix to make all enum naming consistent. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (enum frm_field_enum): Add FRM_ prefix. > > --- > gcc/config/riscv/riscv-protos.h | 2 +- > 1 file changed, 1 inser

Re: Re: RISC-V Bootstrap problems

1:43 > To: Palmer Dabbelt; Vineet Gupta > CC: kito.cheng; gcc-patches; Kito Cheng; Patrick O'Neill; Jeff Law; macro; > juzhe.zh...@rivai.ai > Subject: Re: RISC-V Bootstrap problems > > > On 5/24/23 17:13, Palmer Dabbelt wrote: > > On Wed, 24 May 2023 16:12:20 PDT (-

Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions

LGTM, thanks :) On Wed, May 24, 2023 at 7:26 PM wrote: > > From: Juzhe-Zhong > > According to RVV ISA: > The conversions use the dynamic rounding mode in frm, except for the rtz > variants, which round towards zero. > > So rtz conversion patterns should not have FRM dependency. > > We can't sup

Re: RISC-V Bootstrap problems

Yeah, JoJo still working on toolchain stuff, but just not active on upstream GCC cc. jojo On Thu, May 25, 2023 at 12:06 PM Jeff Law wrote: > > > > On 5/24/23 21:53, Kito Cheng wrote: > > Jojo has a patch to try to split those things that should help this, > > but seems n

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

> When testing a extension, it is often necessary for a certain program not to > need some kind of extension, such as the bitmanip extension, to evaluate the > performance or codesize of the extension. However, the current multilib rules > will report an error when it is not a superset of the MULTI

Re: [PATCH] RISC-V: Fix zero-scratch-regs-3.c fail

Lgtm with a minor comment 於 2023年5月26日 週五 07:18 寫道： > From: Juzhe-Zhong > > Fix ICE of zero-scratch-regs-3.c: > bug.c:7:1: internal compiler error: Segmentation fault > 7 | } > | ^ > 0x1647b23 crash_signal > ../../../riscv-gcc/gcc/toplev.cc:314 > 0x147053f maybe_legitimize_ope

Re: [PATCH] RISC-V: Optimize TARGET_XTHEADCONDMOV

I would defer this to vrull or t-head folks :) Die Li 於 2023年5月26日 週五 08:53 寫道： > This patch allows less instructions to be used when TARGET_XTHEADCONDMOV > is enabled. > > Provide an example from the existing testcases. > > Testcase: > int ConEmv_imm_imm_reg(int x, int y){ > if (x == 1000) re

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Hi Xing: Thanks for your patch, but I would like to know did you have the copyright assignment for FSF? or your employee/company has signed that? On Thu, Jan 21, 2021 at 8:48 PM Xing GUO via Gcc-patches wrote: > > This patch fixes -march option parsing when `p` extension exists, > e.g., -march=r

Re: [PATCH 0/2] RISC-V big endian support

Hi Marcus: Let you know reviewing this patch is on my TODO list, and I definitely want this included in GCC 11, but I am working on other urgent work this week, so I might not be able to give any review comment or testing at this moment. Thanks for your awesome work for big-endian support! On Tu

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Thanks! committed to master :) On Wed, Jan 27, 2021 at 1:58 PM Xing GUO via Gcc-patches wrote: > > Sorry, I forgot to remove the line '*explicit_version_p = true;' in my > previous patch. > > This is an updated patch. > > Thanks! > > --- > gcc/ChangeLog: > > * common/config/riscv/riscv-co

Re: [PATCH] RISC-V: Always define MULTILIB_DEFAULTS

Hi Sebastian: Thank for report this issue, I can reproduce that, I'll investigate what happened today :) Sebastian Huber 於 2021年1月26日 週二 14:13 寫道： > Hello Kito, > > On 20/11/2020 09:33, Kito Cheng wrote: > > - Define MULTILIB_DEFAULTS can reduce the total number of mul

Re: [PATCH 0/2] RISC-V big endian support

Hi Marcus: > * Implicitly pass default endianness as -mbig-endian / -mlittle-endian > to gas, since older binutils targeting little endian will not understand > -mlittle-endian. Instead assume gas has the same default as gcc. > If -mbig-endian or -mlittle-endian is explicitly given, it is p

Re: [PATCH 1/2] RISC-V: Support -mlittle-endian and -mbig-endian

Could you document -mbig-endian and -mlittle-endian in gcc/doc/invoke.texi? On Tue, Jan 26, 2021 at 2:16 AM Marcus Comstedt wrote: > > gcc/ > * config/riscv/elf.h (LINK_SPEC): Pass linker endianness flag. > * config/riscv/freebsd.h (LINK_SPEC): Likewise. > * config/riscv/l

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

> diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h > index 973efdaed7b..7e65e499031 100644 > --- a/gcc/config/riscv/elf.h > +++ b/gcc/config/riscv/elf.h > @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see > . */ > > #define LINK_SPEC "

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

Pushed, thanks :) On Mon, Feb 1, 2021 at 4:58 PM Xing GUO wrote: > > Hi, > > I've reproduced the failure. It's because my gcc is configured as a > bare-metal toolchain and built with binutils that supports RISC-V > attribute. That is to say, my gcc emits RISC-V attributes by default. > Below is t

Re: [PATCH] PR target/98743: Fix ICE in convert_move for RISC-V

On Mon, Feb 1, 2021 at 6:10 PM Jakub Jelinek wrote: > > On Mon, Feb 01, 2021 at 05:57:28PM +0800, Kito Cheng wrote: > > > > - Check `TO` mode is not BLMmode before call store_expr, calling > > > > store_expr > > > >with BLKmode will cause

Re: [PATCH 2/2] RISC-V: Add riscv{32, 64}be with big endian as default

> > Could you extract the endian related LINK_SPEC change to > > ENDIAN_LINK_SPEC to riscv.h, so that we can prevent > > duplicate this several times. > > You mean a define which expands to > > "-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" Yeah, but I'd like to include following 2 lines too: %{

Re: [PATCH] PR target/98878 - Incorrect multilib list for riscv*-rtems

Thanks Jim, committed with your revision of comment :) On Fri, Feb 5, 2021 at 11:28 AM Jim Wilson wrote: > > On Thu, Feb 4, 2021 at 2:02 AM Kito Cheng wrote: >> >> * gcc.c (print_multilib_info): Check all required argument is >> provided >> by de

Re: [PATCH 0/2] RISC-V big endian support

d $ ../configure --prefix=`pwd`/install --with-arch=rv64gc --with-multilib-generator="rv64gc-lp64--" $ make report SIM=spike -j`nproc` On Sat, Jan 30, 2021 at 3:54 AM Marcus Comstedt wrote: > > > Hi Kito, > > Kito Cheng writes: > > > You can add a check in config

Re: [PATCH v2 0/5] RISC-V big endian support

Hi Marcus: Thanks for the quick update, I am testing your V2 patch now, the result seems really great now, some of fail case seems like not cause by big-endian patch, I am reviewing and comparing the fail case with the little-endian build. > Should I make a PR against riscv-newlib on GitHub, or w

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