This patch fixes ICE mentioned on PR112851 and PR112852.
Actually these ICEs happens many times in full coverage testing.
The ICE happens on:
bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187
84 | }
| ^
0x11a7271 partial_subreg_p(machine_mode, machine_mode)
As PR112855 mentioned, the VSETVL PASS insert vsetvli in unexpected location.
Due to 2 reasons:
1. incorrect transparant computation LCM data. We need to check VL operand defs
and uses.
2. incorrect fusion of unrelated edge which is the edge never reach the vsetvl
expression.
PR target/
As PR112855 mentioned, the VSETVL PASS insert vsetvli in unexpected location.
Due to 2 reasons:
1. incorrect transparant computation LCM data. We need to check VL operand defs
and uses.
2. incorrect fusion of unrelated edge which is the edge never reach the vsetvl
expression.
PR target/
Committed as it is ovbious.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (extract_single_source): new function.
(pre_vsetvl::compute_lcm_local_properties): Fix ICE.
---
gcc/config/riscv/riscv-vsetvl.cc | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --g
This patch fixes 400 ICEs in full coverage testing since they happens due to
same reason.
Before this patch:
internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-v.cc:4597
appears 400 times in full coverage testing report.
The root cause is we didn't support interleave v
This patch fixes 64 ICEs in full coverage testing since they happens due to
same reason.
Before this patch:
internal compiler error: in expand_const_vector, at config/riscv/riscv-v.cc:1270
appears 400 times in full coverage testing report.
The root cause is we didn't support interleave vector
This patch fixes 400 ICEs in full coverage testing:
internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-v.cc:4597
The root cause is each operand is used in vleff/vlsegff twice:
(define_insn "@pred_fault_load"
[(set (match_operand:V 0 "register_operand" "=vd
This patch fixes 64 ICEs in full coverage testing since they happens due to
same reason.
Before this patch:
internal compiler error: in expand_const_vector, at config/riscv/riscv-v.cc:1270
appears 400 times in full coverage testing report.
The root cause is we didn't support interleave vector
Since loop vectorizer won't call better_main_loop_than_p if
!flag_vect_cost_model.
Committed as it is obvious.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p):
Remove redundant check.
---
gcc/config/riscv/riscv-vector-costs.cc | 3 ---
1 file chan
According to RVV ISA, we can allow vwadd.wv v2, v2, v3 overlap.
Before this patch:
nop
vsetivlizero,4,e8,m4,tu,ma
vle16.v v8,0(a0)
vmv8r.v v0,v8
vwsub.wvv0,v8,v12
nop
addia4,a0,100
vle16.v v8,0(a4)
vmv8r.v
PR112932 let me notice there is a bug of current VLS mode misalign pattern.
Adapt it same as VLA mode.
Commited as it is obvious fix.
PR target/112932
gcc/ChangeLog:
* config/riscv/vector.md (movmisalign): Fix VLSmode bugs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/r
This patch fixes multiple ICEs in full coverage testing:
cc1: internal compiler error: in riscv_legitimize_poly_move, at
config/riscv/riscv.cc:2456^M
0x1fd8d78 riscv_legitimize_poly_move^M
../../../../gcc/gcc/config/riscv/riscv.cc:2456^M
0x1fd9518 riscv_legitimize_move(machine_mode, rtx_d
This patch fixes the following ICE in VSETVL PASS:
bug.c:39:1: internal compiler error: Segmentation fault
39 | }
| ^
0x1ad5a08 crash_signal
../../../../gcc/gcc/toplev.cc:316
0x7f7f55feb90f ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x218d7c7 extract_
Hi, Richard. This patch fixes an ICE on record_use during RTL_SSA
initialization RISC-V backend VSETVL PASS.
This is the ICE:
0x11a8603 partial_subreg_p(machine_mode, machine_mode)
../../../../gcc/gcc/rtl.h:3187
0x3b695eb
rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_
Notice there are some regression FAILs:
FAIL: gcc.target/riscv/rvv/autovec/pr110950.c -O3 -ftree-vectorize
scan-assembler-times vslide1up\\.vx 1
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c -std=c99 -O3
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax
scan-assembler-times
This patch fixes an ICE on record_use during RTL_SSA initialization RISC-V
backend VSETVL PASS.
This is the ICE:
0x11a8603 partial_subreg_p(machine_mode, machine_mode)
../../../../gcc/gcc/rtl.h:3187
0x3b695eb
rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_info&,
rtl_s
This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for
future better maintain like other target hook implementation.
Committed as it is obviously a code refinement.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (estimated_poly_value): New function.
* config/ris
This patch refactor dynamic LMUL to remove this following variable:
static hash_map loop_autovec_infos;
which will keep growing on-the-fly.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (get_current_lmul): Remove it.
(compute_estimated_lmul): New function.
(costs::c
This patch apply vla vs. vls mode heuristic which can fixes the following FAILs:
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize
scan-assembler-not vset
FAIL: gcc.target/riscv/rvv/autovec/pr111751.c -O3 -ftree-vectorize
scan-assembler-times li\\s+[a-x0-9]+,0\\s+ret 2
The root ca
Fix VSETVL BUG that AVL is polluted
.L15:
li a3,9
lui a4,%hi(s)
sw a3,%lo(j)(t2)
sh a5,%lo(s)(a4) <--a4 is hold the address of s
beq t0,zero,.L42
sw t5,8(t4)
vsetvli zero,a4,e8,m8,ta,ma <<--- a4 as avl
Actually,
From: Ju-Zhe Zhong
This patch is to fix RVV mask modes size. Since mask mode size are adjust
as a whole RVV register size LMUL = 1 which not only make each mask type for
example vbool32_t tied to vint8m1_t but also increase memory consuming.
I notice this issue during development of VSETVL PASS.
From: Ju-Zhe Zhong
This patch is preparing patch for the following patch (VSETVL PASS)
support since the current vlmul printing rule is not appropriate
information for VSETVL PASS. I split this fix in a single patch.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass thr
From: Ju-Zhe Zhong
The attribute configuration of each machine mode are support in the previous
patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Correct attrib
VSETVL pass for RISC-V 'V' Extension for GNU compiler.
+ Copyright(C) 2022-2022 Free Software Foundation, Inc.
+ Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it unde
L pass for RISC-V 'V' Extension for GNU compiler.
+ Copyright(C) 2022-2022 Free Software Foundation, Inc.
+ Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it unde
L pass for RISC-V 'V' Extension for GNU compiler.
+ Copyright(C) 2022-2022 Free Software Foundation, Inc.
+ Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it unde
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL PASS.
* gcc.target/riscv/rvv/vsetvl/dump-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlma
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: New tes
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: New test.
* gcc.target/riscv/rvv/vse
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Fix annotation.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c602426b542..3ca3fc15e5a
From: Ju-Zhe Zhong
I found that I forgot to remove these redundant attributes.
Sorry about that.
gcc/ChangeLog:
* config/riscv/vector.md (): Remove redundant attributes.
---
gcc/config/riscv/vector.md | 20
1 file changed, 20 deletions(-)
diff --git a/gcc/config/
From: Ju-Zhe Zhong
Since store instructions doesn't care about tail policy, we remove
vste from "ta" attribute. Hence, we could have more fusion chances
and better optimization.
gcc/ChangeLog:
* config/riscv/vector.md: Remove vste.
---
gcc/config/riscv/vector.md | 2 +-
1 file change
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Simplify ASM checks.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Di
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vlmax_avl_insn_p): Fix multi-line
conditional.
(vsetvl_insn_p): Ditto.
(same_bb_and_before_p): Ditto.
(same_bb_and_after_or_equal_p): Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 16
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix
incorrect annotations.
(available_occurrence_p): Ditto.
(backward_propagate_worthwhile_p): Ditto.
(can_backward_propagate_p): Ditto.
---
gcc/config/riscv/riscv-vs
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove side effects.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 5 -
1 file changed, 5 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-ve
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Change it to no side
effects.
* config/riscv/vector.md (@vsetvl_no_side_effects): New pattern.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 +-
gcc/config/riscv/vector.md
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct vsetvl_def): Add
"__riscv_" prefix.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsetvl-1.c: Add "__riscv_" prefix.
---
.../riscv/riscv-vector-builtins-shapes.cc | 1 +
...
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_avl_type_rtx): New function.
* config/riscv/riscv-v.cc (get_avl_type_rtx): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore): New
class.
(BASE): Ditto.
* config/risc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix contraints.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-constraint-1.c: New test.
---
gcc/config/riscv/vector.md| 16 +--
.../riscv/rvv/base/vle-constraint-1.c | 109
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_insn): Remove pp_print.
(avl_info::avl_info): Add copy function.
(vector_insn_info::dump): Remove pp_print.
* config/riscv/riscv-vsetvl.h: Add copy function.
---
gcc/config/riscv/riscv-vset
From: Ju-Zhe Zhong
This patch is to fix issue of visiting non-existing block of CFG.
Since blocks index of CFG in GCC are not always contiguous, we will potentially
visit a gap block which is no existing in the current CFG.
This patch can avoid visiting non existing block in CFG.
I noticed such
From: Ju-Zhe Zhong
For store intrinsic,
the function type should be void store (T *...) instead of void store (const T
*...)
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc: Change to scalar pointer.
---
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
1 file changed, 1 inse
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::compute_global_backward_infos): Change iterator form.
(pass_vsetvl::prune_expressions): Change iterator form.
---
gcc/config/riscv/riscv-vsetvl.cc | 18 ++
1 file changed, 10 inserti
From: Ju-Zhe Zhong
Currently we use pred_mov to to do the codegen for vse intrinsics. However, it
generates inferior codegen when I am testing AVL model of VSETVL PASS using vse
intrinsics.
Consider this following code:
void f2 (int * restrict in, int * restrict out, void * restrict mask_in, in
From: Ju-Zhe Zhong
Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
for IMM AVL (0 ~ 31) according to RVV ISA.
This patch fix vsetivli instruction asm bug.
gcc/ChangeLog:
* config/riscv/vector.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-co
From: Ju-Zhe Zhong
Currently we support this optimization:
bb 0:
vsetvli a5,zero,e32,mf2
bb 1:
vsetvli a5,zero,e64,m1 --> vsetvli zero,zero,e64,m1
According RVV ISA, we can do this optimization only if both RATIO and AVL are
equal.
However, current VSETVL PASS missed the check of AVL. This p
From: Ju-Zhe Zhong
Since we only change insn which is not in group. The flag currently is not
correct.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_insn): Adjust in_group in
validate_change.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed, 1 insertion(+), 1 dele
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (loop_basic_block_p): Adjust function.
(backward_propagate_worthwhile_p): Fix non-worthwhile.
---
gcc/config/riscv/riscv-vsetvl.cc | 91 +---
1 file changed, 71 insertions(+), 20 deleti
From: Ju-Zhe Zhong
This patch is NFC patch. I move these code as a function since we will
reuse it in the following patch (Refine phase 3 of VSETVL PASS)
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_vsetvl_insn): New function.
(pass_vsetvl::compute_global_backward_infos
From: Ju-Zhe Zhong
Suppose there are 2 demand infos:
Demand 1: demand TAIL.
Demand 2: not demand TAIL.
If a block is demand 1, we should adjust this block is available both for
demand 1 && 2.
However, if a block is demand 2, we should only adjust this block is available
for demand 2 only.
gc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (can_backward_propagate_p): Fix for null
iter_bb.
(vector_insn_info::set_demand_info): New function.
(pass_vsetvl::emit_local_forward_vsetvls): Adjust for refinement of
Phase 3.
(pass_vsetvl::merge
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c:
From: Ju-Zhe Zhong
This patch is a NFC patch to move the codes into a wrapper function so that
they can be reused. I will reuse them in the following patches.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::create_bitmap_vectors): New function.
(vector_info
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::forward_demand_fusion):
Add pre-check for redundant flow.
---
gcc/config/riscv/riscv-vsetvl.cc | 8
1 file changed, 8 insertions(+)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv
From: Ju-Zhe Zhong
This NFC patch is preparing for the following patches.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion):
Refine codes.
---
gcc/config/riscv/riscv-vsetvl.cc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion):
Add pre-check to avoid redundant flow.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv
From: Ju-Zhe Zhong
Since the PASS is implemented base on RTL_SSA framework.
According to rtl_ssa, they name insn_info * as insn and
name rtx_insn * rinsn. I follow this rule in this pass but I missed
this function. So rename it to make codes be consistent to RTL_SSA
framework.
gcc/ChangeLog:
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Remove
dirty_pat.
(vector_insn_info::merge): Ditto.
(vector_insn_info::dump): Ditto.
(pass_vsetvl::merge_successors): Ditto.
(pass_vsetvl::backward_demand_fus
From: Ju-Zhe Zhong
Notice that the PASS is just simpily pick the probability >= 50%
to do the backward fusion which will create endless loop on Phase 3.
Adding this probability to fix this bug.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager):
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::done): Add DCE.
* config/riscv/t-riscv: Add DCE.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 ++
gcc/config/riscv/t-riscv | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gc
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (same_bb_and_before_p): Remove it.
(real_insn_and_same_bb_p): New function.
(same_bb_and_after_or_equal_p): Remove it.
(before_p): New function.
(reg_killed_by_bb_p): Ditto.
(has_vset
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Adjust testcase.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c:
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-20.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-22.c: New
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-12.c: New
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect attributes.
---
gcc/config/riscv/vector.md | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 4e93b7fea
From: Ju-Zhe Zhong
Since LCM will destroy CFG, we are going to reorder the location of VSETVL PASS
at least before bbro (block-reorder PASS) which is before split3 PASS. We need
to call it in VSETVL PASS to get final RVV instructions patterns.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::done): Remove DCE.
* config/riscv/t-riscv: Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 --
gcc/config/riscv/t-riscv | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/g
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Clang-format.
---
gcc/config/riscv/riscv-vsetvl.cc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c2a8b44584d..26d096ea9
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL
PASS.
---
gcc/config/riscv/riscv-passes.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-passes.def
b/gcc/config/riscv/riscv-passes.def
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.h: Change it into public.
---
gcc/config/riscv/riscv-vsetvl.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
index f24ad981f65..3b
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (before_p): Fix bug.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 26d096ea939..728a32da
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Refine function args.
(emit_vsetvl_insn): Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/
From: Ju-Zhe Zhong
Since we have same function in class and static function calling get_avl.
Adding :: to avoid codes confusing.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_backward_fusion_type):
Add ::.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed,
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vsetvl_insn_p): Add condition to avoid
ICE.
(vsetvl_discard_result_insn_p): New function.
(reg_killed_by_bb_p): rename to find_reg_killed_by.
(find_reg_killed_by): New name.
(get_vl): allow
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm
support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlm): New define.
(vsm): Ditto.
* config/
From: Ju-Zhe Zhong
The original constraint is incorrect in pred_mov pattern.
Take a look at Alternative 2, the operands[0] is "vr",
operands[1] which is mask operand can be "vm".
Such alternative matching will give the wrong codegen (vle.v v0,0(a5),v0.t)
This is illegal according to RVV ISA.
To
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vse-1.c: New test.
* gcc.target/riscv/rvv/base/vse-2.c: New test.
* gcc.target/riscv/rvv/base/vse-3.c: New test.
* gcc.target/riscv/rvv/base/vse_m-1.c: New test.
* gcc.target/riscv/rvv
From: Ju-Zhe Zhong
According to https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/
For "vop_m" intrinsics, C++ overloaded API does not have "_m" suffix.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def):
Remove _m suffix for "vop_m" C++ o
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vle-1.C: New test.
* g++.target/riscv/rvv/base/vle_tu-1.C: New test.
* g++.target/riscv/rvv/base/vle_tum-1.C: New test.
* g++.target/riscv/rvv/base/vle_tumu-1.C: New test.
* g++.target
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore): Add
vlse/vsse intrinsic support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h:
From: Ju-Zhe Zhong
According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
---
gcc/config/r
Hi, Richard and Richi.
This is the last autovec pattern I want to add for RVV (length loop control).
This patch is supposed to handled this following case:
int __attribute__ ((noinline, noclone))
condition_reduction (int *a, int min_v, int n)
{
int last = 66; /* High start value. */
for (i
This patch will be backport to GCC 13 and commit to trunk.
gcc/ChangeLog:
* config/riscv/t-riscv: Add riscv-vsetvl.def
---
gcc/config/riscv/t-riscv | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 1252d6f851a.
Commited.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (change_insn): Clang format.
(vector_infos_manager::all_same_ratio_p): Ditto.
(vector_infos_manager::all_same_avl_p): Ditto.
(pass_vsetvl::refine_vsetvls): Ditto.
(pass_vsetvl::cleanup_vsetvls): Ditto.
Commited.
Fix failures:
FAIL: gcc.target/riscv/rvv/autovec/partial/live-1.c scan-tree-dump-times
optimized ".VEC_EXTRACT" 10
FAIL: gcc.target/riscv/rvv/autovec/partial/live-1.c scan-tree-dump-times
optimized ".VEC_EXTRACT" 10
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/par
This patch is prepare patch for VSETVL PASS.
Commited.
gcc/ChangeLog:
* config/riscv/vector.md: Add attribute.
---
gcc/config/riscv/vector.md | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index e772e7905
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Add
vsetvli asm.
---
.../riscv/rvv/autovec/gather-scatter/gather_load_run-12.c | 6 ++
1 file changed, 6 insertions(
This bug is exposed after refactor patch.
Separate it and commited.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (ge_sew_ratio_unavailable_p): Fix fuse
rule bug.
* config/riscv/riscv-vsetvl.def (DEF_SEW_LMUL_FUSE_RULE): Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 10 +++
Committed for following VSETVL refactor patch to make V2 patch easier to review.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::global_eliminate_vsetvl_insn): Fix potential ICE.
---
gcc/config/riscv/riscv-vsetvl.cc | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-
This patch refactors the Phase 3 (Demand fusion) and rename it into Earliest
fusion.
I do the refactor for the following reasons:
1. Current implementation of phase 3 is doing too many things which makes the
code quality
quite messy and not easy to maintain.
2. The demand fusion I do
Hi.
This patch is apply LEN_FOLD_EXTRACT_LAST into loop vectorizer.
Consider this following case:
#include
#define N 32
/* Simple condition reduction. */
int __attribute__ ((noinline, noclone))
condition_reduction (int *a, int min_v)
{
int last = 66; /* High start value. */
for (int i
Consider this following case:
int __attribute__ ((noinline, noclone))
condition_reduction (int *a, int min_v)
{
int last = 66; /* High start value. */
for (int i = 0; i < 4; i++)
if (a[i] < min_v)
last = i;
return last;
}
--param=riscv-autovec-preference=fixed-vlmax --param=risc
Consider this following case:
int __attribute__ ((noinline, noclone))
condition_reduction (int *a, int min_v)
{
int last = 66; /* High start value. */
for (int i = 0; i < 4; i++)
if (a[i] < min_v)
last = i;
return last;
}
--param=riscv-autovec-preference=fixed-vlmax --param=risc
Committed.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_local_properties):
Add early continue.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f75
This patch refactors the Phase 3 (Demand fusion) and rename it into Earliest
fusion.
I do the refactor for the following reasons:
1. Current implementation of phase 3 is doing too many things which makes the
code quality
quite messy and not easy to maintain.
2. The demand fusion I do
Committed.
Fix failures:
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2
scan-assembler-times
add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\)
1
FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2
sca
Hi, this patch is enabling vec_init for RVV VLA vectorization since we have
almost
support all RVV-related features to the middle-end loop vectorizer.
Test report:
FAIL: gcc.dg/vect/bb-slp-10.c -flto -ffat-lto-objects scan-tree-dump slp2
"unsupported unaligned access"
FAIL: gcc.dg/vect/bb-slp-1
Hi, this patch is enabling vec_int for RVV VLA vectorization since we have
almost
support all RVV-related features to the middle-end loop vectorizer.
Test report:
FAIL: gcc.dg/vect/bb-slp-10.c -flto -ffat-lto-objects scan-tree-dump slp2
"unsupported unaligned access"
FAIL: gcc.dg/vect/bb-slp-10
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