PR112932 let me notice there is a bug of current VLS mode misalign pattern.
Adapt it same as VLA mode.
Commited as it is obvious fix.
PR target/112932
gcc/ChangeLog:
* config/riscv/vector.md (movmisalign<mode>): Fix VLSmode bugs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/pr112932.c: New test.
---
gcc/config/riscv/vector.md | 23 +------
.../gcc.target/riscv/rvv/autovec/pr112932.c | 66 +++++++++++++++++++
.../riscv/rvv/autovec/vls/misalign-1.c | 6 +-
3 files changed, 70 insertions(+), 25 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 31c13a6dcca..a1284fd3251 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1334,31 +1334,12 @@
[(set_attr "type" "vmov")
(set_attr "mode" "<MODE>")])
-(define_expand "movmisalign<mode>"
- [(set (match_operand:VLS 0 "nonimmediate_operand")
- (match_operand:VLS 1 "general_operand"))]
- "TARGET_VECTOR"
- {
- /* To support misalign data movement, we should use
- minimum element alignment load/store. */
- unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
- poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
- machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require
();
- operands[0] = gen_lowpart (mode, operands[0]);
- operands[1] = gen_lowpart (mode, operands[1]);
- if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
- operands[1] = force_reg (mode, operands[1]);
- riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
riscv_vector::UNARY_OP, operands);
- DONE;
- }
-)
-
;; According to RVV ISA:
;; If an element accessed by a vector memory instruction is not naturally
aligned to the size of the element,
;; either the element is transferred successfully or an address misaligned
exception is raised on that element.
(define_expand "movmisalign<mode>"
- [(set (match_operand:V 0 "nonimmediate_operand")
- (match_operand:V 1 "general_operand"))]
+ [(set (match_operand:V_VLS 0 "nonimmediate_operand")
+ (match_operand:V_VLS 1 "general_operand"))]
"TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
{
emit_move_insn (operands[0], operands[1]);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c
new file mode 100644
index 00000000000..4ae6ec02817
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+/* { dg-require-effective-target riscv_v } */
+
+#include <assert.h>
+int a, j, n, b, c, o, d, g, h;
+int e[8];
+long f[8][6];
+void l() {
+ o = -27;
+ for (; o; o++) {
+ *e = 1;
+ if (a >= n) {
+ d = 0;
+ for (; d <= 7; d++)
+ e[d] = c;
+ }
+ }
+ j = 0;
+ for (; j < 8; j++) {
+ g = 0;
+ for (; g < 2; g++) {
+ h = 1;
+ for (; h < 3; h++)
+ f[j][g * 2 + h] = 1;
+ }
+ }
+ unsigned long *m = &f[1][1];
+ *m = 0;
+}
+int main() {
+ l();
+ assert (f[0][1] == 1);
+ assert (f[0][2] == 1);
+ assert (f[0][3] == 1);
+ assert (f[0][4] == 1);
+ assert (f[1][1] == 0);
+ assert (f[1][2] == 1);
+ assert (f[1][3] == 1);
+ assert (f[1][4] == 1);
+ assert (f[2][1] == 1);
+ assert (f[2][2] == 1);
+ assert (f[2][3] == 1);
+ assert (f[2][4] == 1);
+ assert (f[3][1] == 1);
+ assert (f[3][2] == 1);
+ assert (f[3][3] == 1);
+ assert (f[3][4] == 1);
+ assert (f[4][1] == 1);
+ assert (f[4][2] == 1);
+ assert (f[4][3] == 1);
+ assert (f[4][4] == 1);
+ assert (f[5][1] == 1);
+ assert (f[5][2] == 1);
+ assert (f[5][3] == 1);
+ assert (f[5][4] == 1);
+ assert (f[6][1] == 1);
+ assert (f[6][2] == 1);
+ assert (f[6][3] == 1);
+ assert (f[6][4] == 1);
+ assert (f[7][1] == 1);
+ assert (f[7][2] == 1);
+ assert (f[7][3] == 1);
+ assert (f[7][4] == 1);
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
index b602ffd69bb..6e08f77921a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
@@ -21,7 +21,5 @@ foo ()
abort ();
}
-/* { dg-final { scan-assembler-times {vle8\.v} 1 } } */
-/* { dg-final { scan-assembler-times {vle8\.v} 1 } } */
-/* { dg-final { scan-assembler-not {vle16\.v} } } */
-/* { dg-final { scan-assembler-not {vle16\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 } } */
+
--
2.36.3
