On Thu, May 29, 2025 at 7:42 AM Andrew Pinski wrote:
>
> On Mon, May 26, 2025 at 1:40 PM Andrew Pinski wrote:
> > > Note this is redundant store removal - I'm not sure operand_equal_p
> > > is good enough to catch all cases of effective type changes done?
> > > Esp. as infering the old effective
On Mon, Jun 2, 2025 at 8:31 AM Andrew Pinski wrote:
>
> This implements a simple copy propagation for aggregates in the similar
> fashion as we already do for copy prop of zeroing.
>
> Right now this only looks at the previous vdef statement but this allows us
> to catch a lot of cases that show u
> This line seems wrongly indented, should be only two spaces more
> than the if line:
>
> if (check_for_bare_parameter_packs (expression))
>expression = error_mark_node;
>
>
> The patch LGTM otherwise, thanks.
Thanks for your reply! The wrongly indented line has been fixed.
Please check the
On Tue, May 27, 2025 at 6:04 PM Robin Dapp wrote:
>
> From: Robin Dapp
>
> This patch enables strided loads for VMAT_STRIDED_SLP. Instead of
> building vectors from scalars or other vectors we can use strided loads
> directly when applicable.
>
> The current implementation limits strided loads t
On 6/3/25 5:24 PM, Vineet Gupta wrote:
So as of tip of tree, even w/o the patch we no longer see the pattern "beq
, 0, .L12 "
They are replaced with reg anyways, so the test won't even show issue, even w/o
the fix.
beq a1,a5,.L12
beq a6,t0,.L12
beq a7,t3,.L12
I thi
On 6/4/25 3:56 AM, Jiawei wrote:
This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-mcpu=xiangshan-kunminghu` option.
XiangShan-KunMingHu is the third-generation open-source high-performance
RISC-V processor.[1] You can find the corresponding ISA extensi
On Thu, May 29, 2025 at 10:04 AM wrote:
>
> From: Dhruv Chawla
>
> This patch folds the following patterns:
> - max (a, add (a, b)) -> [sum, ovf] = addo (a, b); !ovf ? sum : a
> - max (a, sub (a, b)) -> [sum, ovf] = subo (a, b); !ovf ? a : sum
> - min (a, add (a, b)) -> [sum, ovf] = addo (a, b);
On Wed, Jun 4, 2025 at 2:19 PM Tomasz Kaminski wrote:
>
>
> On Wed, Jun 4, 2025 at 2:05 PM Luc Grosheintz
> wrote:
>
>>
>>
>> On 6/4/25 13:19, Tomasz Kaminski wrote:
>> > Ah, sorry I got confused in the review suggestions, and latter when
>> > checking the code.
>> > What I meant is:
>> >
>> > B
On 6/3/25 9:35 AM, Richard Sandiford wrote:
Sorry, I cannot provide test results for other primary targets. I'm
struggling to setup a cross-linux toolchain build and qemu dejagnu testing.
But if the PR has already been fixed, then I supose there's not much
incentive to rework such a sen
On 28/05/25 15:20 -0400, Patrick Palka wrote:
Change in this version:
* Add test using an integer-class distance type, based on views::iota.
OK for trunk, thank you both for all the work on this!
-- >8 --
This implements ranges::starts_with and ranges::ends_with from the C++23
paper P1659R
On 6/2/25 7:20 PM, Dongyan Chen wrote:
This patch support svbare extension, which is an extension in RVA23 profile.
To enable GCC to recognize and process svbare extension correctly at compile
time.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/ri
On 5/29/25 7:24 AM, Dongyan Chen wrote:
This patch implies zicsr for svade and svadu extensions.
According to the riscv-privileged spec, the svade and svadu extensions
are privileged instructions, so they should imply zicsr.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Imply zicsr.
On 6/3/25 03:33, Jakub Jelinek wrote:
Hi!
When reading the code, I've noticed various function definitions
with misaligned parameters, they should IMHO always align below the first
character after opening ( and in most cases they do, but in some
cases they were indented more or less. Perhaps th
Fine with me. I don't think Aldy got to many of the cast conversions.
Andrew
On 6/3/25 03:31, Jakub Jelinek wrote:
Hi!
I've noticed we don't even support say float -> double and other
scalar floating point to scalar floating point conversions in the
ranger, we just end up with VARYING for tho
On 04/06/25 13:06 +0200, Tomasz Kamiński wrote:
Adding a tests for behavior of the ostream operator and the formatting
with empty chronio-spec for the chrono types. Current coverage is:
* time point, zoned_time and local_time_format in this commit,
* duration and hh_mm_ss in r16-1099-gac0a04b7a25
This came up when looking at some context selectors that use 'target_device',
but is largely unrelated to it. (target_device has its own special casing).
Namely, it makes omp_get_initial_device and omp_get_num_devices PURE,
which attributes don't permit for Fortran - based on the state that
the n
On Tue, May 27, 2025 at 8:37 AM Tomasz Kamiński wrote:
>
> From: Jonathan Wakely
>
> This patch implements C++26 std::polymorphic as specified in P3019 with
> amendment to move assignment from LWG 4251.
>
> The implementation always allocate stored object on the heap. The manager
> function (_M_m
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a (possibly negated) minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfnmadd.vv v2,v6,v4
After, we get only one:
vfnmadd.vf
On Wed, Jun 4, 2025 at 4:04 PM Jonathan Wakely wrote:
> On 04/06/25 13:06 +0200, Tomasz Kamiński wrote:
> >Adding a tests for behavior of the ostream operator and the formatting
> >with empty chronio-spec for the chrono types. Current coverage is:
> > * time point, zoned_time and local_time_forma
PR libstdc++/119152
libstdc++-v3/ChangeLog:
* src/c++23/std.cc.in (std::indirect) [__cpp_lib_indirect]
(std::polymorphic) [__cpp_lib_polymorphic]: Export.
---
OK for trunk?
libstdc++-v3/src/c++23/std.cc.in | 6 ++
1 file changed, 6 insertions(+)
diff --git a/libstdc
On 5/27/25 5:06 AM, Umesh Kalappa wrote:
The P8700 is a high-performance processor from MIPS by extending RISCV with
the MIPS custom instruction and the following changes are added to enable the
conditional move support from mips
No regressions are found for "runtest --tool gcc
--target_boa
On Wed, 4 Jun 2025 at 15:44, Tomasz Kamiński wrote:
>
> PR libstdc++/119152
>
> libstdc++-v3/ChangeLog:
>
> * src/c++23/std.cc.in (std::indirect) [__cpp_lib_indirect]
> (std::polymorphic) [__cpp_lib_polymorphic]: Export.
> ---
> OK for trunk?
OK thanks
>
> libstdc++-v3/
On 5/29/25 6:46 AM, Alfie Richards wrote:
This is a reimplementation of get_target_clone_attr_len,
get_attr_str, and separate_attrs using string_slice and auto_vec to make
memory management and use simpler.
Adds get_target_version helper function to get the target_version string
from a decl.
On Wed, 4 Jun 2025 at 15:35, Tomasz Kaminski wrote:
>
>
>
> On Wed, Jun 4, 2025 at 4:04 PM Jonathan Wakely wrote:
>>
>> On 04/06/25 13:06 +0200, Tomasz Kamiński wrote:
>> >Adding a tests for behavior of the ostream operator and the formatting
>> >with empty chronio-spec for the chrono types. Curr
Adds tests for layout_right and for the parts of layout_left that depend
on layout_right.
libstdc++-v3/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_right.
* testsuite/23_containers/mdspan/layouts/ctors.cc: Add tests for
Implement the parts of layout_left that depend on layout_right; and the
parts of layout_right that don't depend on layout_stride.
libstdc++-v3/ChangeLog:
* include/std/mdspan (layout_right): New class.
* src/c++23/std.cc.in: Add layout_right.
Signed-off-by: Luc Grosheintz
---
l
Implements the parts of layout_left that don't depend on any of the
other layouts.
libstdc++-v3/ChangeLog:
* include/std/mdspan (layout_left): New class.
* src/c++23/std.cc.in: Add layout_left.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 303 +++
The previous iteration can be found here:
https://gcc.gnu.org/pipermail/libstdc++/2025-May/061781.html
Changes since v5:
* Fixed tests on 32-bit systems.
* Expand tests to check absense of UB while multiplying dynamic
extents.
* Formatting (several places).
* static_assert for size of
Implements the remaining parts of layout_left and layout_right; and all
of layout_stride.
The implementation of layout_stride::mapping::is_exhaustive applies
the following change to the standard:
4266. layout_stride::mapping should treat empty mappings as exhaustive
https://cplusplus.github.io
I think we also need to export the ::pmr version?
On Wed, Jun 4, 2025 at 10:44 AM Tomasz Kamiński wrote:
>
> PR libstdc++/119152
>
> libstdc++-v3/ChangeLog:
>
> * src/c++23/std.cc.in (std::indirect) [__cpp_lib_indirect]
> (std::polymorphic) [__cpp_lib_polymorphic]: Export.
On 5/29/25 6:46 AM, Alfie Richards wrote:
Add the assembler_name member to cgraph_function_version_info to store
the base assembler name of the funciton set, before FMV mangling. This is
Just a typo in the patch description. Should be "function".
used in later patches for refactoring FMV ma
On Wed, Jun 04, 2025 at 05:02:45PM +0200, Stefan Schulze Frielinghaus wrote:
> Building a subreg in case of
>
> else if (GET_CODE (x) == CONST)
> {
> /* Extract the symbol ref from:
> (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
>
Implements the tests for layout_stride and for the features of the other
two layouts that depend on layout_stride.
libstdc++-v3/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_stride.
* testsuite/23_containers/mdspan/layouts/c
[mdspan.layout.left.cons] of N4950 states that this ctor is not
noexcept. Since, all other ctors of layout_left, layout_right or
layout_stride are noexcept, the choice was made, based on
[res.on.exception.handling], to make this ctor noexcept.
Two other major standard library implementations make
GCS (Guarded Control Stack, an Armv9.4-a extension) requires some
caution at runtime. The runtime linker needs to reason about the
compatibility of a set of relocable object files that might not
have been compiled with the same compiler.
Up until now, those metadata, used for the previously mention
GCS (Guarded Control Stack, an Armv9.4-a extension) requires some caution at
runtime. The runtime linker needs to reason about the compatibility of a set of
relocable object files that might not have been compiled with the same
compiler. Up until now, those metadata, used for the previously ment
On Wed, 21 May 2025, Jason Merrill wrote:
> On 5/20/25 11:28 AM, Patrick Palka wrote:
> > On Mon, 19 May 2025, Patrick Palka wrote:
> >
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look
> > > OK for trunk/15/14?
> >
> > Whoops, CI reports I missed a testsuite adjustment exp
libstdc++-v3/ChangeLog:
* include/std/mdspan(__mdspan::_ExtentsStorage): Change name
of private member _M_dynamic_extens to _M_dyn_exts.
* include/std/mdspan(extents): Change name of private member
from _M_dynamic_extents to _M_exts.
* include/std/mdspan: Fi
On 5/29/25 6:46 AM, Alfie Richards wrote:
These are needed to correctly mangle FMV declarations.
gcc/ChangeLog:
* cgraph.h (struct cgraph_node): Add dispatcher_resolver_function and
is_target_clone.
OK
jeff
On Wed, Jun 04, 2025 at 05:07:13PM +0200, Jakub Jelinek wrote:
> On Wed, Jun 04, 2025 at 05:02:45PM +0200, Stefan Schulze Frielinghaus wrote:
> > Building a subreg in case of
> >
> > else if (GET_CODE (x) == CONST)
> > {
> > /* Extract the symbol ref from:
> > (mem:QI (const:DI
GNU properties are emitted to provide some information about the features
used in the generated code like BTI, GCS, or PAC. However, no debug
comment are emitted in the generated assembly even if -dA is provided.
It makes understanding the information stored in the .note.gnu.property
section more d
The code emitting the GNU properties was moved to a separate file to
improve modularity and "releave" the 31000-lines long aarch64.cc file
from a few lines.
It introduces a new namespace "aarch64::" for AArch64 backend which
reduce the length of function names by not prepending 'aarch64_' to
each
On 6/4/25 15:38, Tomasz Kaminski wrote:
On Wed, Jun 4, 2025 at 2:19 PM Tomasz Kaminski wrote:
On Wed, Jun 4, 2025 at 2:05 PM Luc Grosheintz
wrote:
On 6/4/25 13:19, Tomasz Kaminski wrote:
Ah, sorry I got confused in the review suggestions, and latter when
checking the code.
What I me
Hi,
This fixes the FMV powerpc tests I recently committed, and hopefully makes them
work on a wider range of target configurations.
I plan to commit this on Monday if no one has any objections.
Thanks,
Alfie
--- >8 ---
As discussed on the BZ page, this removes the tests on the symbols in the
r
Implements a suite of tests for the currently implemented parts of
layout_left. The individual tests are templated over the layout type, to
allow reuse as more layouts are added.
libstdc++-v3/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: New test.
* tes
PR libstdc++/119152
libstdc++-v3/ChangeLog:
* src/c++23/std.cc.in (std::indirect, pmr::indirect)
[__cpp_lib_indirect]
(std::polymorphic, pmr::polymorphic) [__cpp_lib_polymorphic]: Export.
---
v2 adds missing pmr versions. Thanks to Patrick, for noticing that.
OK fo
On Wed, Jun 4, 2025 at 5:45 PM Luc Grosheintz
wrote:
>
>
> On 6/4/25 15:38, Tomasz Kaminski wrote:
> > On Wed, Jun 4, 2025 at 2:19 PM Tomasz Kaminski
> wrote:
> >
> >>
> >>
> >> On Wed, Jun 4, 2025 at 2:05 PM Luc Grosheintz >
> >> wrote:
> >>
> >>>
> >>>
> >>> On 6/4/25 13:19, Tomasz Kaminski w
On Wed, 2025-05-28 at 18:17 +0100, Richard Sandiford wrote:
> Sorry for the slow reply, had a few days off.
>
> Xi Ruoyao writes:
> > If we see a promoted subreg and TRULY_NOOP_TRUNCATION says the
> > truncation is not a noop, then all bits of the inner reg are live. We
> > cannot reduce the liv
On Wed, Jun 04, 2025 at 09:12:58AM +0100, Richard Sandiford wrote:
> Richard Biener writes:
> > On Wed, Jun 4, 2025 at 7:28 AM H.J. Lu wrote:
> >>
> >> On s390x, for input:
> >>
> >> (call_insn/u 7 6 11 2 (parallel [
> >> (set (reg:SI 2 %r2)
> >> (call (subreg:QI (symb
On Wed, 4 Jun 2025 at 17:04, Tomasz Kamiński wrote:
>
> PR libstdc++/119152
>
> libstdc++-v3/ChangeLog:
>
> * src/c++23/std.cc.in (std::indirect, pmr::indirect)
> [__cpp_lib_indirect]
> (std::polymorphic, pmr::polymorphic) [__cpp_lib_polymorphic]: Export.
> ---
> v2
In commit 50be486dff4ea2676ed022e9524ef190b92ae2b1
"nvptx: libgomp+mkoffload.cc: Prepare for reverse offload fn lookup", some
additional tracking of the PTX code was added, and this assumes that
potentially every single character of PTX code needs to be tracked as a new
chunk of PTX code. That's p
On 5/9/25 2:27 PM, Vineet Gupta wrote:
FRM mode switching state machine has DYN as default state which it also
fallsback to after transitioning to other states such as DYN_CALL.
Currently TARGET_MODE_EMIT generates a FRM restore on any transition to
DYN leading to spurious/extraneous FRM resto
On 5/23/25 12:22 PM, Vineet Gupta wrote:
3. NOK: We loose the ability to instrument local RM writes - especially in the
testsuite.
e.g.
a. instrinsic setting a static RM
b. get_frm() to ensure that happened (inline asm to read out frm)
The tightly coupled restore kicks in be
On Wed, Jun 4, 2025 at 6:27 AM Richard Biener
wrote:
>
> On Thu, May 29, 2025 at 10:04 AM wrote:
> >
> > From: Dhruv Chawla
> >
> > This patch folds the following patterns:
> > - max (a, add (a, b)) -> [sum, ovf] = addo (a, b); !ovf ? sum : a
> > - max (a, sub (a, b)) -> [sum, ovf] = subo (a, b)
On 6/4/25 20:30, H.J. Lu wrote:
On Wed, Jun 4, 2025 at 8:02 PM Jonathan Wakely wrote:
On Thu, 29 May 2025 at 20:30, Nathan Myers wrote:
Change in V4:
* Rename tests to string_view.cc
* Adapt tests to cons/wchar_t directories
* Define symbol __cpp_lib_sstream_from_string_view as 202406
From: Pan Li
The div of rvv has not such insn v2 = div (vec_dup (x), v1), thus
the generated rtl like that hit the unreachable assert when
expand insn. This patch would like to remove op div from
the binary op form (vec_dup (x), v) to avoid pattern matching
by mistake.
No new test introduced as
> Am 04.06.2025 um 23:04 schrieb Jakub Jelinek :
>
> Hi!
>
> The function has 2 problems, one is _BitInt specific and the other is
> most likely also reproduceable only with it.
>
> The first issue is that I've missed updating the function for _BitInt,
> maxbitlen as MAX_BITSIZE_MODE_ANY_INT
like r16-105-g599bca27dc37b3, the patch handles redunduant clean up of
upper-bits for maskload.
.i.e
Successfully matched this instruction:
(set (reg:V4DF 175)
(vec_merge:V4DF (unspec:V4DF [
(mem:V4DF (plus:DI (reg/v/f:DI 155 [ b ])
(reg:DI 143 [ ivtmp.56
On 04/06/25 23:14, Andrew Pinski wrote:
External email: Use caution opening links or attachments
On Wed, Jun 4, 2025 at 6:27 AM Richard Biener
wrote:
On Thu, May 29, 2025 at 10:04 AM wrote:
From: Dhruv Chawla
This patch folds the following patterns:
- max (a, add (a, b)) -> [sum, ovf] =
Previously GCC would zero extend a DImode value in memory to a TImode target in
a vector register by firt zero extending the DImode value into a GPR TImode
register pair, and then do a MTVSRDD to move this value to a VSX register.
For example, consider the following code:
#ifndef TYPE
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2025-06-05 13:01
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; ken.chen; hongtao.liu; Pan
Li
Subject: [PATCH v1] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
From: Pan Li
The div of rvv has not such insn v2
Am Mi., 4. Juni 2025 um 17:18 Uhr schrieb Luc Grosheintz <
luc.groshei...@gmail.com>:
> Implements the remaining parts of layout_left and layout_right; and all
> of layout_stride.
>
> The implementation of layout_stride::mapping::is_exhaustive applies
> the following change to the standard:
>
>
Before this patch GCC would zero extend a DImode GPR value to TImode by first
zero extending the DImode value into a GPR TImode register pair, and then do a
MTVSRDD to move this value to a VSX register.
For example, consider the following code:
#ifndef TYPE
#define TYPE unsigned l
On 30/05/25 13:35, Andrew Pinski wrote:
External email: Use caution opening links or attachments
On Thu, May 29, 2025 at 1:05 AM wrote:
From: Dhruv Chawla
This patch folds the following patterns:
- max (a, add (a, b)) -> [sum, ovf] = addo (a, b); !ovf ? sum : a
- max (a, sub (a, b)) -> [su
Ping patch for PR target/99293
https://gcc.gnu.org/pipermail/gcc-patches/2025-May/683038.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Andrew MacLeod writes:
> Fine with me. I don't think Aldy got to many of the cast conversions.
None is the right answer :).
Thanks Jakub.
Aldy
Support the Smrnmi extension, which provides new CSRs
for Machine mode Non-Maskable Interrupts.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/t
These patches add support for several privileged RISC-V extensions, including
Sm/scsrind, Smrnmi, Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl.
The CSRs definition in Binutils part, and gcc part just let the compiler and
user know these extensions are supported.
Jiawei (7):
RISC-V: Supp
Support the Sscounterenw extension, which allows writeable enables for any
supported counter.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
Support the Ssu64xl extension, which requires UXLEN to be 64.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/testsuite/ChangeLog:
* gcc
Support the Sm/scsrind extensions, which provide indirect access to
machine-level CSRs.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/testsuite
Support the Sstvala extension, which provides all needed values in
Supervisor Trap Value register (stval).
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extens
Support the Ssccptr extension, which allows the main memory to support
page table reads.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/testsuit
Support the Sstvecd extension, which allows Supervisor Trap Vector
Base Address register (stvec) to support Direct mode.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document
On Thu, Jun 5, 2025 at 3:29 AM Hu, Lin1 wrote:
>
> Hi,
>
> Some vmovvdup pattern's type attribute is sselog1 and then mem attribute is
> both. Modify type attribute according to other patterns about vmovvdup.
>
> Bootstrapped and regtested on x86_64-linux-pc-gnu, OK for trunk?
OK.
Thanks,
Uros.
On Wed, Jun 4, 2025 at 7:44 PM Andrew Pinski wrote:
>
> On Wed, Jun 4, 2025 at 6:27 AM Richard Biener
> wrote:
> >
> > On Thu, May 29, 2025 at 10:04 AM wrote:
> > >
> > > From: Dhruv Chawla
> > >
> > > This patch folds the following patterns:
> > > - max (a, add (a, b)) -> [sum, ovf] = addo (a,
LGTM :)
On Thu, Jun 5, 2025 at 2:21 PM Jiawei wrote:
>
> These patches add support for several privileged RISC-V extensions, including
> Sm/scsrind, Smrnmi, Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl.
>
> The CSRs definition in Binutils part, and gcc part just let the compiler and
> use
101 - 177 of 177 matches
Mail list logo
