Re: [committed] i386: Generate strict_low_part QImode insn with high input register

On Tue, Nov 14, 2023 at 6:37 PM Uros Bizjak wrote: > PR target/78904 > > gcc/ChangeLog: > > * config/i386/i386.md (*addqi_ext_1_slp): > New define_insn_and_split pattern. > (*subqi_ext_1_slp): Ditto. > (*qi_ext_1_slp): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i

Re: [PATCH] rs6000: Only enable PCREL on supported ABIs [PR111045]

Hi, on 2023/11/15 11:01, Peter Bergner wrote: > PCREL data accesses are only officially supported on ELFv2. We currently > incorrectly enable PCREL on all Power10 compiles in which prefix instructions > are also enabled. Rework the option override code so we only enable PCREL > for those ABIs th

Re: [PATCH] Clean up by_pieces_ninsns

Hi, on 2023/11/15 10:26, HAO CHEN GUI wrote: > Hi, > This patch cleans up by_pieces_ninsns and does following things. > 1. Do the length and alignment adjustment for by pieces compare when > overlap operation is enabled. > 2. Remove unnecessary mov_optab checks. > > Bootstrapped and tested on

Re: [PATCH] RISC-V: Support trailing vec_init optimization

Hi Juzhe, thanks, LGTM as it is just a refinement of what we already have. Regards Robin

[PATCH] sched: Remove debug counter sched_block

Hi, on 2023/11/10 01:40, Alexander Monakov wrote: > I agree with the concern. I hoped that solving the problem by skipping the BB > like the (bit-rotted) debug code needs to would be a minor surgery. As things > look now, it may be better to remove the non-working sched_block debug counter > enti

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

Hi Alexander/Richard/Jeff, Thanks for the insightful comments! on 2023/11/10 22:41, Alexander Monakov wrote: > > On Fri, 10 Nov 2023, Richard Biener wrote: > >> On Fri, Nov 10, 2023 at 3:18 PM Alexander Monakov wrote: >>> >>> >>> On Fri, 10 Nov 2023, Richard Biener wrote: >>> > I'm afraid

[PATCH] rs6000: New pass to mitigate SP float load perf issue on Power10

Hi, As Power ISA defines, when loading a scalar single precision (SP) floating point from memory, we have the double precision (DP) format in target register converted from SP, it's unlike some other architectures which supports SP and DP in registers with their separated formats. The scalar SP i

[PATCH] [i386] APX: Fix EGPR usage in several patterns.

Hi, For vextract/insert{if}128 they cannot adopt EGPR in their memory operand, all related pattern should be adjusted to disable EGPR usage on them. Also fix a wrong gpr16 attr for insertps. Bootstrapped/regtested on x86-64-pc-linux-gnu{-m32,} Ok for master? gcc/ChangeLog: * config/i38

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

On Wed, 15 Nov 2023, Kewen.Lin wrote: > >> And I suppose it would be OK to do that. Empty BBs are usually removed by > >> CFG cleanup so the situation should only happen in rare corner cases where > >> the fix would be to actually run CFG cleanup ... > > > > Yeah, sel-sched invokes 'cfg_cleanu

[PATCH 02/16] [APX NDD] Restrict TImode register usage when NDD enabled

Under APX NDD, previous TImode allocation will have issue that it was originally allocated using continuous pair, like rax:rdi, rdi:rdx. This will cause issue for all TImode NDD patterns. For NDD we will not assume the arithmetic operations like add have dependency between dest and src1, then writ

[PATCH 00/16] Support Intel APX NDD

Hi, Intel APX NDD feature has been released in [1]. NDD means New data destination. In such forms, NDD is the new destination register receiving the result of the computation and all other operands (including the original destination operand) become read-only source operands. This feature, i.e.

[PATCH 04/16] [APX NDD] Disable seg_prefixed memory usage for NDD add

NDD uses evex prefix, so when segment prefix is also applied, the instruction could excceed its 15byte limit, especially adding immediates. This could happen when "e" constraint accepts any UNSPEC_TPOFF/UNSPEC_NTPOFF constant and it will add the offset to segment register, which will be encoded usi

[PATCH 06/16] [APX NDD] Support APX NDD for sub insns

From: Kong Lingling gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_fixup_binary_operands_no_copy): Add use_ndd parameter. (ix86_can_use_ndd_p): ADD MINUS. * config/i386/i386-protos.h (ix86_fixup_binary_operands_no_copy): Change define. * config/

[PATCH 01/16] [APX NDD] Support Intel APX NDD for legacy add insn

From: Kong Lingling APX NDD provides an extra destination register operand for several gpr related legacy insns, so a new alternative can be adopted to operand1 with "r" constraint. This first patch supports NDD for add instruction, and keeps to use lea when all operands are registers since lea

[PATCH 08/16] [APX NDD] Support APX NDD for neg insn

From: Kong Lingling gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add NEG support. (ix86_expand_unary_operator): Add use_ndd parameter and adjust for NDD. * config/i386/i386-protos.h : Add use_ndd parameter for ix86_unary_operator_ok an

[PATCH 14/16] [APX NDD] Support APX NDD for rotate insns

gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add ROTATE and ROTATERT. * config/i386/i386.md (*3_1): Extend with a new alternative to support NDD for SI/DI rotate, and adjust output template. (*si3_1_zext): Likewise. (*3_1

[PATCH 03/16] [APX NDD] Support APX NDD for optimization patterns of add

From: Kong Lingling gcc/ChangeLog: * config/i386/i386.md: (addsi_1_zext): Add new alternatives for NDD and adjust output templates. (*add_2): Likewise. (*addsi_2_zext): Likewise. (*add_3): Likewise. (*addsi_3_zext): Likewise. (*adddi_4): Li

[PATCH 09/16] [APX NDD] Support APX NDD for not insn

From: Kong Lingling gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add NOT support. * config/i386/i386.md (one_cmpl2): Add NDD constraints, adjust output template. (*one_cmpl2_1): Likewise. (*one_cmplqi2_1): Likewise. (*o

[PATCH 12/16] [APX NDD] Support APX NDD for left shift insns

For left shift, there is an optimization TARGET_DOUBLE_WITH_ADD that shl 1 can be optimized to add. As NDD form of add requires src operand to be register since NDD cannot take 2 memory src, we currently just keep using NDD form shift instead of add. The optimization TARGET_SHIFT1 will try to remo

[PATCH 05/16] [APX NDD] Support APX NDD for adc insns

From: Kong Lingling Legacy adc patterns are commonly adopted to TImode add, when extending TImode add to NDD version, operands[0] and operands[1] can be different, so extra move should be emitted if those patterns have optimization when adding const0_rtx. gcc/ChangeLog: * config/i386/i3

[PATCH 07/16] [APX NDD] Support APX NDD for sbb insn

From: Kong Lingling Similar to *add3_doubleword, operands[1] may not equal to operands[0] so extra move is required. gcc/ChangeLog: * config/i386/i386.md (*sub3_doubleword): Add ndd constraints, and emit move when operands[0] not equal to operands[1]. (*sub3_doubleword_z

[PATCH 16/16] [APX NDD] Support APX NDD for cmove insns

gcc/ChangeLog: * config/i386/i386.md (*movcc_noc): Extend with new constraints to support NDD. (*movsicc_noc_zext): Likewise. (*movsicc_noc_zext_1): Likewise. (*movqicc_noc): Likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-ndd-cmov.c: New

[PATCH 10/16] [APX NDD] Support APX NDD for and insn

From: Kong Lingling For NDD form AND insn, there are three splitter fixes after extending legacy patterns. 1. APX NDD does not support high QImode registers like ah, bh, ch, dh, so for some optimization splitters that generates highpart zero_extract for QImode need to be prohibited under NDD pat

[PATCH 11/16] [APX NDD] Support APX NDD for or/xor insn

From: Kong Lingling Similar to AND insn, two splitters need to be adjusted to prevent misoptimizaiton for NDD OR/XOR. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add IOR/XOR support. * config/i386/i386.md (3): Add NDD alternative and adjust

[PATCH 15/16] [APX NDD] Support APX NDD for shld/shrd insns

For shld/shrd insns, the old pattern use match_dup 0 as its shift src and use +r*m as its constraint. To support NDD we added new define_insns to handle NDD form pattern with extra input and dest operand to be fixed in register. gcc/ChangeLog: * config/i386/i386.md (x86_64_shld_ndd): New

[PATCH 13/16] [APX NDD] Support APX NDD for right shift insns

Similar to LSHIFT, rshift should also emit $1 for NDD form with CX_REG as operands[1]. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add LSHIFTRT and RSHIFTRT. * config/i386/i386.md (ashr3_cvt): Extend with new alternatives to support NDD, and a

Re: [PATCH v2] LoongArch: Remove redundant barrier instructions before LL-SC loops

在 2023/11/15 上午5:52, Xi Ruoyao 写道: This is isomorphic to the LLVM changes [1-2]. On LoongArch, the LL and SC instructions has memory barrier semantics: - LL: + - SC: + But the compare and swap operation is allowed to fail, and if it fails the SC instruction is not executed, thus the guar

Re: [RFC PATCH] Detecting lifetime-dse issues via Valgrind [PR66487]

On 2023-11-13 02:53, Sam James wrote: Sam James writes: Alexander Monakov writes: [...] I'm very curious what you mean by "this has come up with LLVM [] too": ttbomk, LLVM doesn't do such lifetime-based optimization yet, which is why compiling LLVM with LLVM doesn't break it. Can you shar

RE: [PATCH] RISC-V: Support trailing vec_init optimization

Committed, thanks Robin.. Pan -Original Message- From: Robin Dapp Sent: Wednesday, November 15, 2023 4:59 PM To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com; jeffreya...@gmail.com Subject: Re: [PATCH] RISC-V: Support traili

Re: gfortran.dg/dg.exp debug messages pollute test output

> FX submitted the patch series, I can find the reference if you need it. Patch was submitted in this thread: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630096.html >> Besides, >> it's unclear if those messages can just be removed (they are pretty >> cryptic as is) or at least cha

Re: Re: [PATCH] RISC-V: testsuite: Fix 32-bit FAILs.

Hi, Kito. Could you take a look at this issue? -march parser is consistent between non-linux and linux. You can simplify verify it with these cases: FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test fo

[committed] arm: testsuite: fix test for armv6t2 hardware

My previous patch series added a new function to check for armv6t2 compatible hardware. But the test was not correctly implemented and also did not follow the standard naming convention for Arm hw compatibility tests. Fix both of these issues. gcc/testsuite: * lib/target-supports.exp (

[PATCH 2/4] libsanitizer: Apply local patches

Hi! This patch just reapplies local patches (will be noted in LOCAL_PATCHES). diff --git a/libsanitizer/asan/asan_globals.cpp b/libsanitizer/asan/asan_globals.cpp index 4d391cb2a88..01a243927ca 100644 --- a/libsanitizer/asan/asan_globals.cpp +++ b/libsanitizer/asan/asan_globals.cpp @@ -158,23 +1

[PATCH 3/4] libsanitizer: Adjust the asan/sanity-check-pure-c-1.c test

Hi! The updated libasan doesn't print __interceptor_free (or __interceptor_malloc) but free (or malloc), the following patch adjusts the testcase so that it accepts it. 2023-11-15 Jakub Jelinek * c-c++-common/asan/sanity-check-pure-c-1.c: Adjust for interceptor_ or wrap_ subst

[PATCH 4/4] libsanitizer: Readd __ubsan_handle_function_type_mismatch_v1{,_abort}

Hi! So that we don't have to bump libubsan.so.1 SONAME, the following patch reverts part of the changes which removed two handlers. While we don't actually use them from GCC, we shouldn't remove supported entrypoints unless SONAME is changed (removal of __interceptor_* or ___interceptor_* is fine

[PING] [PATCH v2] A new copy propagation and PHI elimination pass

- Forwarded message from Filip Kastl - From: Filip Kastl To: gcc-patches@gcc.gnu.org Cc: rguent...@suse.de, hubi...@ucw.cz Subject: [PATCH v2] A new copy propagation and PHI elimination pass Date: Thu, 2 Nov 2023 14:00:02 +0100 Message-ID: > Hi, > > this is a patch that I submitted tw

Re: [PATCH 1/4] libsanitizer: merge from upstream (c425db2eb558c263)

Jakub Jelinek writes: > Hi! > > The following patch is result of libsanitizer/merge.sh > from c425db2eb558c263 (yesterday evening). > > Bootstrapped/regtested on x86_64-linux and i686-linux (together with > the follow-up 3 patches I'm about to post). > > Iain, could you please check Darwin? > >

[committed] libstdc++: std::stacktrace tweaks

Tested x86_64-linux. Pushed to trunk. Backports to follow. The new hash.cc test was failing for armv8l-unknown-linux-gnueabihf according to Linaro CI. This should fix it (but there are still other failures for std::stacktrace, so I opened PR 112541). -- >8 -- Fix a typo in a string literal and m

[committed] libstdc++: Fix std::deque::operator[] Xmethod [PR112491]

Tested x86_64-linux. Pushed to trunk. Backports to follow. -- >8 -- The Xmethod for std::deque::operator[] has the same bug that I recently fixed for the std::deque::size() Xmethod. The first node might have unused capacity at the start, which needs to be accounted for when indexing into the dequ

Re: [PATCH v2] LoongArch: Remove redundant barrier instructions before LL-SC loops

Pushed r14-5486. /* snip */ > > * gcc.target/loongarch/cas-acquire.c: New test. This test fails with GCC 12/13 on LA664, and it indicates a correctness issue. May I backport this patch to 12/13 as well? -- Xi Ruoyao School of Aerospace Science and Technology, Xidian University

Re: [PATCH 1/4] libsanitizer: merge from upstream (c425db2eb558c263)

On Wed, 15 Nov 2023, Jakub Jelinek wrote: > Hi! > > The following patch is result of libsanitizer/merge.sh > from c425db2eb558c263 (yesterday evening). > > Bootstrapped/regtested on x86_64-linux and i686-linux (together with > the follow-up 3 patches I'm about to post). > > Iain, could you plea

Re: [PATCH] Only allow (copysign x, NEG_CONST) -> (fneg (fabs x)) simplification for constant folding [PR112483]

On Tue, Nov 14, 2023 at 10:14 PM Xi Ruoyao wrote: > > On Tue, 2023-11-14 at 11:44 +0100, Richard Biener wrote: > > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > > > index 2d2e5a3c1ca..f3745d86aea 100644 > > > --- a/gcc/simplify-rtx.cc > > > +++ b/gcc/simplify-rtx.cc > > > @@ -4392,7 +

Re: [PATCH v4] gcc: Introduce -fhardened

On Tue, Nov 14, 2023 at 5:00 PM Marek Polacek wrote: > > On Tue, Nov 14, 2023 at 08:46:16AM +0100, Richard Biener wrote: > > On Fri, Nov 3, 2023 at 11:51 PM Marek Polacek wrote: > > > > > > On Thu, Oct 26, 2023 at 05:55:56PM +0200, Richard Biener wrote: > > > > > > > > > > > > > Am 24.10.2023 um

Re: gfortran.dg/dg.exp debug messages pollute test output

Hi FX, >> FX submitted the patch series, I can find the reference if you need it. > > Patch was submitted in this thread: > https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630096.html ah, I see. I'd been looking for the patch summary and Iain's name in my searches; that's why I came up

[PATCH] Fix ICE with SLP and -fdbg-cnt

We have to clear the visited flag on stmts. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. * tree-vect-slp.cc (vect_slp_region): Also clear visited flag when we skipped an instance due to -fdbg-cnt. --- gcc/tree-vect-slp.cc | 9 ++--- 1 file changed, 6 insertion

[PATCH] tree-optimization/112282 - wrong-code with ifcvt hoisting

The following avoids hoisting of invariants from conditionally executed parts of an if-converted loop. That now makes a difference since we perform bitfield lowering even when we do not actually if-convert the loop. if-conversion deals with resetting flow-sensitive info when necessary already. B

RE: [PATCH 5/21]middle-end: update vectorizer's control update to support picking an exit other than loop latch

On Tue, 14 Nov 2023, Tamar Christina wrote: > > > OK, but then I think the fix is to not use > > > standard_iv_increment_position (it's a weird API anyway). Instead insert > > before the main exit condition. > > > > I figured as much, Almost done respinning it with the vectorizer's own > > simp

[PATCH] c++/modules: Allow exporting const-qualified namespace-scope variables [PR99232]

Bootstrapped and regtested on x86_64-pc-linux-gnu. I don't have write access. -- >8 -- By [basic.link] p3.2.1, a non-template non-volatile const-qualified variable is not necessarily internal linkage in a module declaration, and rather may have module linkage (or external linkage if it is exporte

Re: [PATCH v4] gcc: Introduce -fhardened

On Fri, Nov 03, 2023 at 06:51:16PM -0400, Marek Polacek wrote: > + if (flag_hardened) > + { > + if (!fortify_seen_p && optimize > 0) > + { > + if (TARGET_GLIBC_MAJOR == 2 && TARGET_GLIBC_MINOR >= 35) > + cpp_define (parse_in, "_FORTIFY_SOURCE=3"); > +

Re: building GNU gettext on AIX

[CCing bug-gettext] David Edelsohn wrote in : > The current gettext-0.22.3 fails to build for me on AIX. Here are some hints to get a successful build of GNU gettext on AIX: 1. Set the recommended environment variables before r

RE: [PATCH 4/21]middle-end: update loop peeling code to maintain LCSSA form for early breaks

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to latest trunk, > > This splits the part of the function that does peeling for loops at exits to > a different function. In this new function we also peel for early breaks. > > Peeling for early breaks works by redirecting all early b

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to latest trunk: > > Hi All, > > This changes the PHI node updates to support early breaks. > It has to support both the case where the loop's exit matches the normal loop > exit and one where the early exit is "inverted", i.e. it's an

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:01 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early > breaks and arbitrary exits > > On Wed,

[PATCH] s390: Fix ICE in testcase pr89233

When using GNU vector extensions, an access outside of the vector size caused an ICE on s390. Fix this by aligning with the vec_extract builtin, i.e., computing constant index modulo number of lanes. Fixes testcase gcc.target/s390/pr89233.c. Bootstrapped and tested on s390. OK for mainline? gc

[PATCH] s390: split int128 load

Issue two loads when using GPRs instead of one load-multiple. Bootstrapped and tested on s390. OK for mainline? gcc/ChangeLog: * config/s390/s390.md: Split TImode loads. gcc/testsuite/ChangeLog: * gcc.target/s390/int128load.c: New test. Signed-off-by: Juergen Christ --- gcc

[PATCH] s390: implement flags output

Implement flags output for inline assemblies. Only use one output constraint that captures the whole condition code. No breakout into different condition codes is allowed. Also, only one condition code variable is allowed. Add further logic to canonicalize various cases where we combine differe

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, November 15, 2023 1:01 PM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > > Subject: RE: [PATCH 7/21]middle-end: update IV update code to

[PATCH] s390: Fix generation of s390-gen-builtins.h

By default the preprocessed output includes linemarkers. This leads to an error if -pedantic is used as e.g. during bootstrap: s390-gen-builtins.h:1:3: error: style of line directive is a GCC extension [-Werror] Fixed by omitting linemarkers while generating s390-gen-builtins.h. gcc/ChangeLog:

Re: [PATCH] s390: Fix generation of s390-gen-builtins.h

On 11/15/23 14:29, Stefan Schulze Frielinghaus wrote: > By default the preprocessed output includes linemarkers. This leads to > an error if -pedantic is used as e.g. during bootstrap: > > s390-gen-builtins.h:1:3: error: style of line directive is a GCC extension > [-Werror] > > Fixed by omitti

RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction with support for multiple exits and different exits

On Wed, 15 Nov 2023, Tamar Christina wrote: > Patch updated to trunk. > > This adds support to vectorizable_live_reduction to handle multiple exits by vectorizable_live_operation, but I do wonder how you handle reductions? > doing a search for which exit the live value should be materialized in

[committed] amdgcn: simplify secondary reload patterns

This patch makes no functional changes, but cleans up the code a little to make way for my next patch. The confusung "reload_in" and "reload_out" define_expand were used solely for secondary reload and were nothing more than aliases for the "sgprbase" instructions. I've now learned that the c

[committed] amdgcn: Add Accelerator VGPR registers

AMD GPUs since CDNA1 have had a new register file with an additional 256 32-bit-by-64-lane vector registers. This doubles the number of vector registers on the device, compared to previous models. The way the hardware works is that the register file is divided between all the running threads,

RE: [PATCH 7/21]middle-end: update IV update code to support early breaks and arbitrary exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:23 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 7/21]middle-end: update IV update code to support early > breaks and arbitrary exits > > On Wed,

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

David Edelsohn writes: > GCC had been working on AIX with NLS, using "--with-included-gettext". > --disable-nls gets past the breakage, but GCC does not build for me on AIX > with NLS enabled. That should still work with gettext 0.22+ extracted in-tree (it should be fetched by download_prerequi

RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction with support for multiple exits and different exits

> -Original Message- > From: Richard Biener > Sent: Wednesday, November 15, 2023 1:42 PM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; j...@ventanamicro.com > Subject: RE: [PATCH 8/21]middle-end: update vectorizable_live_reduction > with support for multiple exits and diffe

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

> Looks wrong. Recover back. When we demote we use two elements where there was one before. Therefore the vector needs to be able to hold twice as many elements. We adjust vl correctly but the mode is not here. Regards Robin

nvptx: Extend 'brev' test cases (was: [PATCH] nvptx: Add suppport for __builtin_nvptx_brev instrinsic)

Hi! On 2023-05-06T17:04:57+0100, "Roger Sayle" wrote: > This patch adds support for (a pair of) bit reversal intrinsics > __builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit > and 64-bit bit reversal (using nvptx's brev instruction) matching > the __brev and __brevll instrinsics

Re: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

Could you show me the example ? It's used by handling SEW = 64 on RV32. I don't know why this patch touch this code. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-15 22:27 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: Disallow 64-bit inde

Re: [nvptx PATCH] Update nvptx's bitrev2 pattern to use BITREVERSE rtx.

Hi! On 2023-06-08T00:09:00+0100, "Roger Sayle" wrote: > This minor tweak to the nvptx backend switches the representation of > of the brev instruction from an UNSPEC to instead use the new BITREVERSE > rtx. ACK. > This allows various RTL optimizations including evaluation (constant > folding) o

nvptx: Fix copy'n'paste-o in '__builtin_nvptx_brev' description (was: [PATCH] nvptx: Add suppport for __builtin_nvptx_brev instrinsic)

Hi! On 2023-05-06T17:04:57+0100, "Roger Sayle" wrote: > This patch adds support for (a pair of) bit reversal intrinsics > __builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit > and 64-bit bit reversal (using nvptx's brev instruction) matching > the __brev and __brevll instrinsics

[PATCH]middle-end: skip checking loop exits if loop malformed [PR111878]

Hi All, Before my refactoring if the loop->latch was incorrect then find_loop_location skipped checking the edges and would eventually return a dummy location. It turns out that a loop can have loops_state_satisfies_p (LOOPS_HAVE_RECORDED_EXITS) but also not have a latch in which case get_loop_ex

[PATCH]AArch64 Add pattern for unsigned widenings (uxtl) to zip{1,2}

Hi All, This changes unpack instructions to use zip{1,2} when doing a zero-extending widening operation. Permutes generally have a higher throughput than the widening operations. Zeros are shuffled into the top half of the registers. The testcase void d2 (unsigned * restrict a, unsigned short *

[committed] i386: Fix strict_low_part QImode insn with high input register patterns [PR112540]

PR target/112540 gcc/ChangeLog: * config/i386/i386.md (*addqi_ext_1_slp): Correct operand numbers in split pattern. Replace !Q constraint of operand 1 with !qm. Add insn constrain. (*subqi_ext_1_slp): Ditto. (*qi_ext_1_slp): Ditto. Bootstrapped and regression tested on

Re: PR111754

On Wed, 8 Nov 2023 at 21:57, Prathamesh Kulkarni wrote: > > On Thu, 26 Oct 2023 at 09:43, Prathamesh Kulkarni > wrote: > > > > On Thu, 26 Oct 2023 at 04:09, Richard Sandiford > > wrote: > > > > > > Prathamesh Kulkarni writes: > > > > On Wed, 25 Oct 2023 at 02:58, Richard Sandiford > > > > wrot

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, 2023-11-15 at 15:14 +0100, Arsen Arsenović wrote: > That is interesting.  They should be using the same checks.  I've > checked trunk and regenerated files on it, and saw no significant diff > (some whitespace changes only).  Could you post the config.log of > both? You did not regenerate

[PATCH] Fortran: fix reallocation on assignment of polymorphic variables [PR110415]

This patch adds the testcase from PR110415 and fixes the bug. The problem is that in a couple of places in trans_class_assignment in trans-expr.cc, we need to get the run-time size of the polymorphic object from the vtbl, but we are currently getting that vtbl from the lhs of the assignment ra

[PATCH] Add support for function attributes and variable attributes

Hi, This patch adds the (incomplete) support for function and variable attributes. The added attributes are the ones we're using in rustc_codegen_gcc but all the groundwork is done to add more (and we will very likely add more as we didn't add all the ones we use in rustc_codegen_gcc yet). The on

Re: [PATCH] Add support for function attributes and variable attributes

David: another thing I remember you mentioned when you reviewed an earlier version of this patch is the usage of `std::pair`. I can't find where you said that, but I remember you mentioned that we should use a struct instead. Can you please elaborate again? Thanks. On Wed, 2023-11-15 at 17:53 +010

[PATCH]AArch64: only discount MLA for vector and scalar statements

Hi All, In testcases gcc.dg/tree-ssa/slsr-19.c and gcc.dg/tree-ssa/slsr-20.c we have a fairly simple computation. On the current generic costing we generate: f: add w0, w0, 2 maddw1, w0, w1, w1 lsl w0, w1, 1 ret but on any other cost model but generi

[PATCH 2/6]AArch64: Remove special handling of generic cpu.

Hi All, In anticipation of adding new generic turning values this removes the hardcoding of the "generic" CPU and instead just specifies it as a normal CPU. No change in behavior is expected. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/Chan

[PATCH 3/6]AArch64: Add new generic-armv8-a CPU and make it the default.

Hi All, This patch adds a new generic scheduling model "generic-armv8-a" and makes it the default for all Armv8 architectures. -mcpu=generic and -mtune=generic is kept around for those that really want the deprecated cost model. This shows on SPECCPU 2017 the following: generic: SPECINT 1.0% i

[PATCH 6/6]AArch64: only emit mismatch error when features would be disabled.

Hi All, At the moment we emit a warning whenever you specify both -march and -mcpu and the architecture of them differ. The idea originally was that the user may not be aware of this change. However this has a few problems: 1. Architecture revisions is not an observable part of the architectur

[PATCH 4/6]AArch64: Add new generic-armv9-a CPU and make it the default for Armv9

Hi All, This patch adds a new generic scheduling model "generic-armv9-a" and makes it the default for all Armv9 architectures. -mcpu=generic and -mtune=generic is kept around for those that really want the deprecated cost model. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote: > > David Edelsohn writes: > > > GCC had been working on AIX with NLS, using "--with-included-gettext". > > --disable-nls gets past the breakage, but GCC does not build for me on > AIX > > with NLS enabled. > > That should still work with ge

[Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming function args which ABI/ISA guarantee to be sign-extended already (this is true for SI, HI, QI operands) And subsequentl

[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447]

From: Juzhe-Zhong Fixes: f0e28d8c1371 ("RISC-V: Fix failed hoist in LICM of vmv.v.x instruction") Since above commit, we have following failure: FAIL: gcc.c-torture/execute/memset-3.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test FAIL: gc

Re: [PATCH 04/14] c++: use _P() defines from tree.h

On Tue, 8 Aug 2023 16:31:39 -0400 Jason Merrill wrote: > On 8/2/23 12:51, Patrick Palka via Gcc-patches wrote: > > On Thu, Jun 1, 2023 at 2:11 PM Bernhard Reutner-Fischer > > wrote: > >> > >> Hi David, Patrick, > >> > >> On Thu, 1 Jun 2023 18:33:46 +0200 > >> Bernhard Reutner-Fischer wrote: >

[PATCH] c++: constantness of call to function pointer [PR111703]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk/13/12 (to match the PR107939 / r13-6525-ge09bc034d1b4d6 backports)? -- >8 -- potential_constant_expression for a CALL_EXPR to a non-overload tests FUNCTION_POINTER_TYPE_P on the callee rather than on the type of the ca

[Committed] RISC-V: Fix ICE in non-canonical march parsing

Updated testcase names and committed. Thanks, Patrick --- Passing in a base extension in non-canonical order (i, e, g) causes GCC to ICE: xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e' xgcc: internal compiler error: in add, at common/config/riscv/riscv-common.cc:671 ...

Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

Does relax mean no longer enforcing the canonical order of extensions? Patrick On 11/14/23 17:52, Kito Cheng wrote: LGTM, and BTW...I am thinking we could relax the canonical order during parsing, did you have interesting and time working on that item? On Wed, Nov 15, 2023 at 9:35 AM Patrick

Re: building GNU gettext on AIX

When I try to configure gettext-0.22.3, I receive the following error: checking for socklen_t equivalent... configure: error: Cannot find a type to use in place of socklen_t configure: error: /nasfarm/edelsohn/src/gettext-0.22.3/libtextstyle/configure failed for libtextstyle configure:43943: /n

Re: [PATCH v3 0/2] Replace intl/ with out-of-tree GNU gettext

On Wed, Nov 15, 2023 at 9:22 AM Arsen Arsenović wrote: > > David Edelsohn writes: > > > GCC had been working on AIX with NLS, using "--with-included-gettext". > > --disable-nls gets past the breakage, but GCC does not build for me on > AIX > > with NLS enabled. > > That should still work with ge

Re: Darwin: Replace environment runpath with embedded [PR88590]

Hi! On 2023-10-30T19:08:18+, Iain Sandoe wrote: >> On 30 Oct 2023, at 16:31, FX Coudert wrote: >> >>> +enable_darwin_at_rpath_$1=no >> >> I actually don’t understand why this one would have $1 in the name, unlike >> all other regenerated configure files. What value do we expect for $1 at >

[COMMITTED] Regenerate libiberty/aclocal.m4 with aclocal 1.15.1

There is a new buildbot check that all autotool files are generated with the correct versions (automake 1.15.1 and autoconf 2.69). https://builder.sourceware.org/buildbot/#/builders/gcc-autoregen Correct one file that was generated with the wrong version. libiberty/ * aclocal.m4: Rebuild.

Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

On 11/15/23 15:29, 钟居哲 wrote: > Could you show me the example ? > > It's used by handling SEW = 64 on RV32. I don't know why this patch touch > this code. Use gather_load_run-1.c with the 64-bit index patterns disabled on rv32. We insert (mem:DI (reg:SI)) into a vector so use the SEW = 64 demot

Re: Darwin: Replace environment runpath with embedded [PR88590]

> So I currently see the following in my build logs: > >[...] >mkdir -p -- ./fixincludes >Configuring in ./fixincludes >configure: creating cache ./config.cache >[...]/source-gcc/fixincludes/configure: line 3030: > enable_darwin_at_rpath_--srcdir=[...]/source-gcc/fixincludes=n

Re: building GNU gettext on AIX

David Edelsohn wrote: > When I try to configure gettext-0.22.3, I receive the following error: > > checking for socklen_t equivalent... configure: error: Cannot find a type > to use in place of socklen_t > > configure: error: > /nasfarm/edelsohn/src/gettext-0.22.3/libtextstyle/configure failed fo

[committed] i386: Optimize strict_low_part QImode insn with high input registers

Following testcase: struct S1 { unsigned char val; unsigned char pad1; unsigned short pad2; }; struct S2 { unsigned char pad1; unsigned char val; unsigned short pad2; }; struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) { a.val = b.val + c.val; return a; } compiles wit

Re: building GNU gettext on AIX

On Wed, Nov 15, 2023 at 4:22 PM Bruno Haible wrote: > David Edelsohn wrote: > > When I try to configure gettext-0.22.3, I receive the following error: > > > > checking for socklen_t equivalent... configure: error: Cannot find a type > > to use in place of socklen_t > > > > configure: error: > > /

Re: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

OK. Make sense。 LGTM as long as you remove all GET_MODE_BITSIZE (GET_MODE_INNER (mode)) <= GET_MODE_BITSIZE (Pmode) juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-16 04:30 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: Disallow 64-bit indexe

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