Following testcase:
struct S1
{
unsigned char val;
unsigned char pad1;
unsigned short pad2;
};
struct S2
{
unsigned char pad1;
unsigned char val;
unsigned short pad2;
};
struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
{
a.val = b.val + c.val;
return a;
}
compiles with -O2 to:
movl %edi, %eax
movzbl %dh, %edx
movl %esi, %ecx
movb %dl, %al
addb %ch, %al
The insert to %al can go directly from %dh:
movl %edi, %eax
movl %esi, %ecx
movb %dh, %al
addb %ch, %al
Patch introduces strict_low_part QImode insn patterns with both of
their input arguments extracted from high register. This invalid
insn is split after reload to a lowpart insert from the high register
and <insn>qi_ext<mode>_1_slp instruction.
PR target/78904
gcc/ChangeLog:
* config/i386/i386.md (*movstrictqi_ext<mode>_1): New insn pattern.
(*addqi_ext<mode>_2_slp): New define_insn_and_split pattern.
(*subqi_ext<mode>_2_slp): Ditto.
(*<any_logic:code>qi_ext<mode>_2_slp): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr78904-8.c: New test.
* gcc.target/i386/pr78904-8a.c: New test.
* gcc.target/i386/pr78904-8b.c: New test.
* gcc.target/i386/pr78904-9.c: New test.
* gcc.target/i386/pr78904-9a.c: New test.
* gcc.target/i386/pr78904-9b.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 32535621db4..26cdb21d3c0 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3335,6 +3335,19 @@ (define_insn "*movstrict<mode>_xor"
(set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
+(define_insn "*movstrictqi_ext<mode>_1"
+ [(set (strict_low_part
+ (match_operand:QI 0 "register_operand" "+Q"))
+ (subreg:QI
+ (match_operator:SWI248 2 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0))]
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
+ "mov{b}\t{%h1, %0|%0, %h1}"
+ [(set_attr "type" "imov")
+ (set_attr "mode" "QI")])
+
(define_expand "extv<mode>"
[(set (match_operand:SWI24 0 "register_operand")
(sign_extract:SWI24 (match_operand:SWI24 1 "register_operand")
@@ -6645,6 +6658,39 @@ (define_insn_and_split "*addqi_ext<mode>_1_slp"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
+(define_insn_and_split "*addqi_ext<mode>_2_slp"
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
+ (plus:QI
+ (subreg:QI
+ (match_operator:SWI248 3 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)
+ (subreg:QI
+ (match_operator:SWI248 4 "extract_operator"
+ [(match_operand 2 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(set (strict_low_part (match_dup 0))
+ (subreg:QI
+ (match_op_dup 4
+ [(match_dup 2) (const_int 8) (const_int 8)]) 0))
+ (parallel
+ [(set (strict_low_part (match_dup 0))
+ (plus:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 1) (const_int 8) (const_int 8)]) 0)
+ (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI")])
+
;; Split non destructive adds if we cannot use lea.
(define_split
[(set (match_operand:SWI48 0 "register_operand")
@@ -7688,6 +7734,39 @@ (define_insn_and_split "*subqi_ext<mode>_1_slp"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
+(define_insn_and_split "*subqi_ext<mode>_2_slp"
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
+ (minus:QI
+ (subreg:QI
+ (match_operator:SWI248 3 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)
+ (subreg:QI
+ (match_operator:SWI248 4 "extract_operator"
+ [(match_operand 2 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(set (strict_low_part (match_dup 0))
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 1) (const_int 8) (const_int 8)]) 0))
+ (parallel
+ [(set (strict_low_part (match_dup 0))
+ (minus:QI
+ (match_dup 0)
+ (subreg:QI
+ (match_op_dup 4
+ [(match_dup 2) (const_int 8) (const_int 8)]) 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI")])
+
(define_insn "*sub<mode>_2"
[(set (reg FLAGS_REG)
(compare
@@ -11513,6 +11592,39 @@ (define_insn_and_split "*<code>qi_ext<mode>_1_slp"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
+(define_insn_and_split "*<code>qi_ext<mode>_2_slp"
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q"))
+ (any_logic:QI
+ (subreg:QI
+ (match_operator:SWI248 3 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)
+ (subreg:QI
+ (match_operator:SWI248 4 "extract_operator"
+ [(match_operand 2 "int248_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)]) 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(set (strict_low_part (match_dup 0))
+ (subreg:QI
+ (match_op_dup 4
+ [(match_dup 2) (const_int 8) (const_int 8)]) 0))
+ (parallel
+ [(set (strict_low_part (match_dup 0))
+ (any_logic:QI
+ (subreg:QI
+ (match_op_dup 3
+ [(match_dup 1) (const_int 8) (const_int 8)]) 0)
+ (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
+ [(set_attr "type" "alu")
+ (set_attr "mode" "QI")])
+
(define_split
[(set (match_operand:SWI248 0 "register_operand")
(and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8.c
b/gcc/testsuite/gcc.target/i386/pr78904-8.c
new file mode 100644
index 00000000000..3ca1d424c7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-8.c
@@ -0,0 +1,25 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+ unsigned short pad2;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+ unsigned short pad2;
+};
+
+struct S1 test (struct S1 a, struct S2 b)
+{
+ a.val = b.val;
+
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8a.c
b/gcc/testsuite/gcc.target/i386/pr78904-8a.c
new file mode 100644
index 00000000000..fe484a79a39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-8a.c
@@ -0,0 +1,23 @@
+/* PR target/78904 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+};
+
+struct S1 test (struct S1 a, struct S2 b)
+{
+ a.val = b.val;
+
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8b.c
b/gcc/testsuite/gcc.target/i386/pr78904-8b.c
new file mode 100644
index 00000000000..cfed7c18b09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-8b.c
@@ -0,0 +1,27 @@
+/* PR target/78904 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+ unsigned short pad2;
+ unsigned int pad3;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+ unsigned short pad2;
+ unsigned int pad3;
+};
+
+struct S1 test (struct S1 a, struct S2 b)
+{
+ a.val = b.val;
+
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9.c
b/gcc/testsuite/gcc.target/i386/pr78904-9.c
new file mode 100644
index 00000000000..aa80be4c8b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-9.c
@@ -0,0 +1,63 @@
+/* PR target/78904 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+ unsigned short pad2;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+ unsigned short pad2;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val & c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val | c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val ^ c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val + c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val - c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9a.c
b/gcc/testsuite/gcc.target/i386/pr78904-9a.c
new file mode 100644
index 00000000000..009ae241199
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-9a.c
@@ -0,0 +1,61 @@
+/* PR target/78904 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val & c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val | c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val ^ c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val + c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val - c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9b.c
b/gcc/testsuite/gcc.target/i386/pr78904-9b.c
new file mode 100644
index 00000000000..bf68f8bef20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr78904-9b.c
@@ -0,0 +1,65 @@
+/* PR target/78904 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -masm=att" } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+
+struct S1
+{
+ unsigned char val;
+ unsigned char pad1;
+ unsigned short pad2;
+ unsigned int pad3;
+};
+
+struct S2
+{
+ unsigned char pad1;
+ unsigned char val;
+ unsigned short pad2;
+ unsigned int pad3;
+};
+
+struct S1 test_and (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val & c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]andb" } } */
+
+struct S1 test_or (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val | c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]orb" } } */
+
+struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val ^ c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]xorb" } } */
+
+struct S1 test_add (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val + c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]addb" } } */
+
+struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c)
+{
+ a.val = b.val - c.val;
+
+ return a;
+}
+
+/* { dg-final { scan-assembler "\[ \t\]subb" } } */
