[PATCH v11 01/40] c++: Sort built-in identifiers alphabetically

This patch sorts built-in identifiers alphabetically for better code readability. gcc/cp/ChangeLog: * constraint.cc (diagnose_trait_expr): Sort built-in identifiers alphabetically. * cp-trait.def: Likewise. * semantics.cc (trait_expr_value): Likewise. (fini

[PATCH v11 09/40] libstdc++: Optimize is_unbounded_array trait performance

This patch optimizes the performance of the is_unbounded_array trait by dispatching to the new __is_unbounded_array built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_unbounded_array_v): Use __is_unbounded_array built-in trait. Signed-off-by: Ken Matsui --- l

[PATCH v11 04/40] c++: Implement __is_volatile built-in trait

This patch implements built-in trait for std::is_volatile. gcc/cp/ChangeLog: * cp-trait.def: Define __is_volatile. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_VOLATILE. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/tests

[PATCH v11 11/40] libstdc++: Optimize is_bounded_array trait performance

This patch optimizes the performance of the is_bounded_array trait by dispatching to the new __is_bounded_array built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_bounded_array_v): Use __is_bounded_array built-in trait. Signed-off-by: Ken Matsui --- libstdc++

[PATCH v11 08/40] c++: Implement __is_unbounded_array built-in trait

This patch implements built-in trait for std::is_unbounded_array. gcc/cp/ChangeLog: * cp-trait.def: Define __is_unbounded_array. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_UNBOUNDED_ARRAY. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr):

[PATCH v11 05/40] libstdc++: Optimize is_volatile trait performance

This patch optimizes the performance of the is_volatile trait by dispatching to the new __is_volatile built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_volatile): Use __is_volatile built-in trait. (is_volatile_v): Likewise. Signed-off-by: Ken Matsui -

[PATCH v11 27/40] c++: Implement __remove_pointer built-in trait

This patch implements built-in trait for std::remove_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __remove_pointer. * semantics.cc (finish_trait_type): Handle CPTK_REMOVE_POINTER. gcc/testsuite/ChangeLog: * g++.dg/ext/has-builtin-1.C: Test existence of __remove_poin

[PATCH v11 16/40] c, c++: Use 16 bits for all use of enum rid for more keyword space

Now that RID_MAX has reached 255, we need to update the bit sizes of every use of the enum rid from 8 to 16 to support more keywords. gcc/c-family/ChangeLog: * c-indentation.h (struct token_indent_info): Make keyword 16 bits and move this upward to minimize memory fragmentation.

[PATCH v11 07/40] libstdc++: Optimize is_array trait performance

This patch optimizes the performance of the is_array trait by dispatching to the new __is_array built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_array): Use __is_array built-in trait. (is_array_v): Likewise. Signed-off-by: Ken Matsui --- libstdc++-v3/includ

[PATCH v11 28/40] libstdc++: Optimize remove_pointer trait performance

This patch optimizes the performance of the remove_pointer trait by dispatching to the new remove_pointer built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (remove_pointer): Use __remove_pointer built-in trait. Signed-off-by: Ken Matsui --- libstdc++-v3/include/

[PATCH v11 06/40] c++: Implement __is_array built-in trait

This patch implements built-in trait for std::is_array. gcc/cp/ChangeLog: * cp-trait.def: Define __is_array. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_ARRAY. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise. gcc/testsuite/Chan

[PATCH v11 30/40] libstdc++: Optimize is_pointer trait performance

This patch optimizes the performance of the is_pointer trait by dispatching to the new __is_pointer built-in trait. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h (__is_ptr): Use __is_pointer built-in trait. * include/std/type_traits (is_pointer): Likewise. Optim

[PATCH v11 25/40] libstdc++: Optimize is_function trait performance

This patch optimizes the performance of the is_function trait by dispatching to the new __is_function built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_function): Use __is_function built-in trait. (is_function_v): Likewise. Optimize its implementation.

[PATCH v11 14/40] c++: Implement __is_member_pointer built-in trait

This patch implements built-in trait for std::is_member_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __is_member_pointer. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_MEMBER_POINTER. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Li

[PATCH v11 40/40] libstdc++: Optimize is_scalar trait performance

This patch optimizes the performance of the is_scalar trait by dispatching to the new __is_scalar built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_scalar): Use __is_scalar built-in trait. (is_scalar_v): Likewise. Signed-off-by: Ken Matsui --- libstd

[PATCH v11 23/40] libstdc++: Optimize is_reference trait performance

This patch optimizes the performance of the is_reference trait by dispatching to the new __is_reference built-in trait. libstdc++-v3/ChangeLog: * include/std/type_traits (is_reference): Use __is_reference built-in trait. (is_reference_v): Likewise. Signed-off-by: Ken Mats

[PATCH v11 20/40] c++: Implement __is_member_object_pointer built-in trait

This patch implements built-in trait for std::is_member_object_pointer. gcc/cp/ChangeLog: * cp-trait.def: Define __is_member_object_pointer. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_MEMBER_OBJECT_POINTER. * semantics.cc (trait_expr_value): Likewise.

[PATCH v11 12/40] c++: Implement __is_scoped_enum built-in trait

This patch implements built-in trait for std::is_scoped_enum. gcc/cp/ChangeLog: * cp-trait.def: Define __is_scoped_enum. * constraint.cc (diagnose_trait_expr): Handle CPTK_IS_SCOPED_ENUM. * semantics.cc (trait_expr_value): Likewise. (finish_trait_expr): Likewise.

Re: gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

Hi Mark! On 2023-09-13T17:02:05+0100, Iain Sandoe wrote: >> On 12 Sep 2023, at 16:00, Mark Wielaard wrote: >> Adding Jeff to CC who is the official gcc-patches mailinglist admin. >> >> On Tue, 2023-09-12 at 11:08 +0400, Maxim Kuvyrkov wrote: >>> Normally, notifications from Linaro TCWG precommit

Re: [pushed][PATCH] LoongArch: Change the value of branch_cost from 2 to 6.

Pushed to r14-3977. 在 2023/9/13 上午11:11, Lulu Cheng 写道: gcc/ChangeLog: * config/loongarch/loongarch-def.c: Modify the default value of branch_cost. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmov_ii.c: New test. --- gcc/config/loongarch/loongarch-def.c |

[PATCH V2] RISC-V: Fix ICE in get_avl_or_vl_reg

update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp. This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE PR target/111395 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE. (vector_insn_info::global_merge

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

Hi, On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely wrote: > Tested x86_64-linux and aarch64-linux. I intend to push this to trunk. > > -- >8 -- > > These atomics cause linker errors on arm4t where __sync_synchronize is > not defined. For single-threaded targets we don't need the atomics. > > I

Re: [PATCH V2] RISC-V: Fix ICE in get_avl_or_vl_reg

LGTM with a minor comment. > @@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const > bb_info *bb) const > } > >/* Step1: Reshape the VL/VTYPE status to make sure everything compatible. > */ > - auto_vec pred_cfg_bbs = get_dominated_by > (CDI_POST_DOMINATORS, cfg_bb);

[PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp. This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE update v2 -> v3: Remove redundant format. PR target/111395 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix

[Committed] RISC-V: Format VSETVL PASS code

gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Format it. --- gcc/config/riscv/riscv-vsetvl.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 8ec5

Re: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

lgtm On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong wrote: > > update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp. > > This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE > > update v2 -> v3: Remove redundant format. > > PR target/111395 > > gcc/Chang

RE: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, September 14, 2023 3:56 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH V3] RIS

[PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 I notice that previous patch (V2 patch) cause additional execution fail of pr69719.c This FAIL is because of the latent BUG of VSETVL PASS. So this patch includes VSETVL PASS fix even though it's not related to the PR111391.

Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong wrote: > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 > > I notice that previous patch (V2 patch) cause additional execution fail of > pr69719.c > This FAIL is because of the latent BUG of VSETVL PASS. > > So this patch include

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

>> Why remove this? I saw this change was introduced in v3? The "@" was introduced by this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630184.html At the first time, I thought I need to explicitly call emit_insn (gen_vec_extract (mode, mode, ) That's why I added in the

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

On Thu, 14 Sept 2023 at 08:44, Christophe Lyon wrote: > > Hi, > > > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely wrote: >> >> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk. >> >> -- >8 -- >> >> These atomics cause linker errors on arm4t where __sync_synchronize is >> not

RE: [PATCH v4] libgfortran: Replace mutex with rwlock

> Hi Thomas, > > > > > Hi Lipeng, > > > > > May I know any comment or concern on this patch, thanks for your > > > time > > > 😄 > > > > Thanks for your patience in getting this reviewed. > > > > A few remarks / questions. > > > > Which strategy is used in this implementation, read-preferring or >

Re: [PATCH-1v2, rs6000] Enable SImode in FP registers on P7 [PR88558]

Hi Kewen, 在 2023/9/12 17:33, Kewen.Lin 写道: > Ok, at least regression testing doesn't expose any needs to do disparaging > for this. Could you also test this patch with SPEC2017 for P7 and P8 > separately at options like -O2 or -O3, to see if there is any assembly > change, and if yes filtering ou

Re: [PATCH] Improve error message for if with an else part while in switch

On Thu, Sep 14, 2023 at 12:30 AM Andrew Pinski via Gcc-patches wrote: > > While writing some match.pd code, I was trying to figure > out why I was getting an `expected ), got (` error message > while writing an if statement with an else clause. For switch > statements, the if statements cannot hav

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely wrote: > On Thu, 14 Sept 2023 at 08:44, Christophe Lyon > wrote: > > > > Hi, > > > > > > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely > wrote: > >> > >> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk. > >> > >> -- >8 -- > >

Re: [PATCH] MATCH: Support `(a != (CST+1)) & (a > CST)` optimizations

On Thu, Sep 14, 2023 at 7:34 AM Andrew Pinski via Gcc-patches wrote: > > Even though this is done via reassocation, match can support > these with a simple change to detect that the difference is just > one. This allows to optimize these earlier and even during phiopt > for an example. > > This pa

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

On Thu, 14 Sept 2023 at 09:41, Christophe Lyon wrote: > > > > On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely wrote: >> >> On Thu, 14 Sept 2023 at 08:44, Christophe Lyon >> wrote: >> > >> > Hi, >> > >> > >> > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely wrote: >> >> >> >> Tested x86_64-linux a

Re: gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

On Tue, Sep 12, 2023 at 5:00 PM Mark Wielaard wrote: > > Hi Maxim, > > Adding Jeff to CC who is the official gcc-patches mailinglist admin. > > On Tue, 2023-09-12 at 11:08 +0400, Maxim Kuvyrkov wrote: > > Normally, notifications from Linaro TCWG precommit CI are sent only to > > patch author and p

[PATCH v2 2/2] libstdc++: Add dg-require-thread-fence in several tests

Some targets like arm-eabi with newlib and default settings rely on __sync_synchronize() to ensure synchronization. Newlib does not implement it by default, to make users aware they have to take special care. This makes a few tests fail to link. This patch requires the missing thread-fence effec

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

On Thu, 14 Sept 2023 at 11:06, Jonathan Wakely wrote: > On Thu, 14 Sept 2023 at 09:41, Christophe Lyon > wrote: > > > > > > > > On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely > wrote: > >> > >> On Thu, 14 Sept 2023 at 08:44, Christophe Lyon > >> wrote: > >> > > >> > Hi, > >> > > >> > > >> > On

Re: [PATCH] testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c

ping? On Fri, 8 Sept 2023 at 10:43, Christophe Lyon wrote: > The test was declaring 'int *carry;' and wrote to '*carry' without > initializing 'carry' first, leading to an attempt to write at address > zero, and a crash. > > Fix by declaring 'int carry;' and passing '&carrry' instead of 'carry'

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in vec_extract optab ? juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-09-14 16:11 To: Juzhe-Zhong CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[P

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Could you check if it work correctly for rv64gcv_zve32x? add testcase no matter if it works or not :) On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai wrote: > > Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in > vec_extract optab ? > > > > juzhe.zh...@rivai.ai > >

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

You mean try pr111391.c that I added with rv64gcv_zve32x ? juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-09-14 17:20 To: juzhe.zh...@rivai.ai CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391] Could you ch

Re: [PATCH v2 2/2] libstdc++: Add dg-require-thread-fence in several tests

On Thu, 14 Sept 2023 at 10:10, Christophe Lyon wrote: > > Some targets like arm-eabi with newlib and default settings rely on > __sync_synchronize() to ensure synchronization. Newlib does not > implement it by default, to make users aware they have to take special > care. > > This makes a few tes

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Oh I see. It ICE: during RTL pass: expand bug.c:26:9: internal compiler error: in require, at machmode.h:313 26 | i (a); | ^ 0x1032253 opt_mode::require() const ../../../../gcc/gcc/machmode.h:313 0x1c47877 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail :P), maybe add a testcase pr111391-zve32x.c that just include pr111391.c and set dg option to rv64gc_zve32x On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai wrote: > > You mean try pr111391.c > that I added with rv64gcv_z

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

Hi. Kito. Could you review this code ? Regression is running /* Expand (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0)) Expand this data movement instead of simply forbid it since we can improve the code generation for this following scenario by RVV auto-vectorization

Re: [PATCHSET] Reintroduce targetrustm hooks

On Wed, Sep 13, 2023 at 10:14 PM Iain Buclaw via Gcc-patches wrote: > > Excerpts from Arthur Cohen's message of September 7, 2023 3:41 pm: > > Alright, was not expecting to mess up this patchset so bad so here we go: > > > > This patchset reintroduces proper targetrustm hooks without the old > > p

Re: [PATCH] core: Support heap-based trampolines

On Wed, Sep 6, 2023 at 5:44 PM FX Coudert wrote: > > Hi, > > ping**2 on the revised patch, for Richard or another global reviewer. So far > all review feedback is that it’s a step forward, and it’s been widely used > for both aarch64-darwin and x86_64-darwin distributions for almost three > yea

[PATCH] aarch64: Coerce addresses to be suitable for LD1RQ

In the following test: svuint8_t ld(uint8_t *ptr) { return svld1rq(svptrue_b8(), ptr + 2); } ptr + 2 is a valid address for an Advanced SIMD load, but not for an SVE load. We therefore ended up generating: ldr q0, [x0, 2] dup z0.q, z0.q[0] This patch makes us generate

[PATCH] ira: Consider save/restore costs of callee-save registers [PR110071]

ira: Consider save/restore costs of callee-save registers [PR110071] In improve_allocation() routine, IRA checks for each allocno if spilling any conflicting allocnos can improve the allocation of this allocno. This routine computes the cost improvement for usage of each profitable hard register f

[PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391 PR target/111391 gcc/ChangeLog: * config/riscv/autovec.md (@vec_extract): Remove @. (vec_extract): Ditto. * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug. (pass_vsetvl::local_e

[PATCH] tree-optimization/111294 - better DCE after forwprop

The following adds more aggressive DCE to forwprop to clean up dead stmts when folding a stmt leaves some operands unused. The patch uses simple_dce_from_worklist for this purpose, queueing original operands before substitution and folding, but only if we folded the stmt. This removes one dead st

[PATCH] LoongArch: gcc: Modify gas uleb128 support test.

From: mengqinggang Add "ld conftest.o -o conftest" process, then the "objdump -dr" contents is right. Because gas write zero to objdec file and generate R_LARCH_ADD_ULEB128/R_LARCH_SUB_ULEB128 reloc pair to calcualte uleb128 format symbol subtraction after ld relaxation. gcc/ChangeLog:

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

On Thu, 2023-09-14 at 19:21 +0800, Lulu Cheng wrote: > diff --git a/gcc/configure.ac b/gcc/configure.ac > index 09082e8ccae..072fe1d2b48 100644 > --- a/gcc/configure.ac > +++ b/gcc/configure.ac > @@ -3226,6 +3226,19 @@ L2: > .uleb128 0x8000 >  ], >  [[ > +case "$target" in > + 

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

Sorry, it's my problem. We will modify it as soon as possible. Thanks! 在 2023/9/14 下午7:45, Xi Ruoyao 写道: On Thu, 2023-09-14 at 19:21 +0800, Lulu Cheng wrote: diff --git a/gcc/configure.ac b/gcc/configure.ac index 09082e8ccae..072fe1d2b48 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@

RE: [PING][PATCH 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

Hi Stam, > -Original Message- > From: Stam Markianos-Wright > Sent: Wednesday, September 6, 2023 6:19 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > > Subject: [PING][PATCH 1/2] arm: Add define_attr to to create a mapping > between MVE predicated and unpredica

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

On Thu, 2023-09-14 at 19:54 +0800, chenglulu wrote: > Sorry, it's my problem. We will modify it as soon as possible. Try this: diff --git a/gcc/configure.ac b/gcc/configure.ac index cb4be11facd..10027a4 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3229,10 +3229,18 @@ AC_MSG_RESULT

Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class

On 9/10/23 00:49, Hongyu Wang wrote: Vladimir Makarov via Gcc-patches 于2023年9月9日周六 01:04写道： On 8/31/23 04:20, Hongyu Wang wrote: @@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression (@code{MEM} for the top level of an address, @code{ADDRESS} for something that occurs i

RE: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Hi Stam, > -Original Message- > From: Stam Markianos-Wright > Sent: Wednesday, September 6, 2023 6:19 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > > Subject: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low > Overhead Loops > > Hi all, > > Th

[PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

This is a new version of the patch on "nested FMA". Sorry for updating this after so long, I've been studying and writing micro cases to sort out the cause of the regression. First, following previous discussion: (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629080.html) 1. From testi

[PATCH] RISC-V: Support VLS modes mask operations

This patch support mask operations (comparison and logical). This patch reduce these FAILs of "vect" testsuite: FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects scan-tree-dump dce7 "<=\\s*.+{ 255,.+}" FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"

[COMMITTED] ada: Fix premature finalization in loop over limited iterable container

From: Eric Botcazou This happens when the iterable container is obtained as the result of a call to a function that is a subprogram parameter of a generic construct. gcc/ada/ * exp_util.adb (Initialized_By_Aliased_BIP_Func_Call): Make the name matching more robust. Tested on x8

[COMMITTED] ada: Assertion failure adding extra formals to late overriding subp.

From: Javier Miranda gcc/ada/ * sem_ch6.adb (Parent_Subprogram): Complete assertion. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/sem_ch6.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb index 297371

[COMMITTED] ada: Assertion failure on for-of loop iterating on selected component

From: Javier Miranda gcc/ada/ * sem_util.adb (Is_Dependent_Component_Of_Mutable_Object): Protect access to Entity attribute and add missing code to check function selector in a prefix form call. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/sem_util.a

[COMMITTED] ada: Improve detection of deactivated code for warnings with -gnatwt

From: Yannick Moy Switch -gnatwt is used in GNAT to track deleted code. It can be emitted by GNAT on code that is intentionally deactivated for a given configuration. The current test to suppress spurious warnings is not complex enough to detect all such cases. Now improved, by using the same tes

[COMMITTED] ada: Fix late finalization for function call in delta aggregate

From: Eric Botcazou The problem occurs at library level because the temporary created for the function call lives in the elaboration routine but is finalized only when the package itself is. It turns out that there is no need for this temporary, since the expansion of delta aggregates already cr

[COMMITTED] ada: Assertion failure on calculation of Large_Max_Size_Mutable

From: Javier Miranda gcc/ada/ * sem_util.adb (Large_Max_Size_Mutable): Protect access to attribute Is_Array_Type. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/sem_util.adb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/ada/sem_uti

[COMMITTED] ada: Assertion failure on expansion of record with invariant

From: Javier Miranda gcc/ada/ * exp_util.adb (Process_Record_Component): Adjust assertion on the availablity of the invariant procedure; required because the invariant procedure is built by the expander, and hence it is not available compiling generic units or whe

[PATCH] tree-optimization/111294 - backwards threader PHI costing

This revives an earlier patch since the problematic code applying extra costs to PHIs in copied blocks we couldn't make any sense of prevents a required threading in this case. Instead of coming up with an artificial other costing the following simply removes the bits. As with all threading chang

[PATCH] tree optimization/111407--SSA corruption due to widening_mul opt

on conflict across an abnormal edge This is a bug in tree-ssa-math-opts.cc, when applying the widening mul optimization, the compiler needs to check whether the operand is in a ABNORMAL PHI, if YES, we should avoid the transformation. bootstrapped and regression tested on both aarch64 and x86, no

[committed] libstdc++: Remove some more unconditional uses of atomics

Tested aarch64-linux. Pushed to trunk. -- >8 -- These atomics cause linker errors on arm4t where __sync_synchronize is not defined. For single-threaded targets we don't need the atomics. libstdc++-v3/ChangeLog: * include/experimental/io_context (io_context) [!_GLIBCXX_HAS_GTHREADS]:

[committed] libstdc++: Support dg-additional-files in tests

Tested aarch64-linux. Pushed to trunk. The text files that these tests use are all identical. Now that each test starts with a fresh copy of the file it needs, there's no reason to have different files for each test, so we could remove the duplicates and change the tests to use the same file name.

[committed] libstdc++: Add testcase for std::make_integer_sequence bug [PR111357]

Tested aarch64-linux. Pushed to trunk. I'll backport the test and a library workaround to the release branches. -- >8 -- The compiler bug has been fixed on trunk, but this adds a regression test for the library component. libstdc++-v3/ChangeLog: PR c++/111357 * testsuite/20_uti

Re: [PATCHSET] Reintroduce targetrustm hooks

On 9/14/23 12:12, Richard Biener wrote: On Wed, Sep 13, 2023 at 10:14 PM Iain Buclaw via Gcc-patches wrote: Excerpts from Arthur Cohen's message of September 7, 2023 3:41 pm: Alright, was not expecting to mess up this patchset so bad so here we go: This patchset reintroduces proper target

Question on -fwrapv and -fwrapv-pointer

Hi, I have several questions on these options: 1.are pointers treated as signed integers in general? (I thought that pointers are addresses to the memory, should be treated as unsigned integer…) 2. If Yes, why? 3. why a separate option for pointesr -fwrapv-pointer in addition to -fwrapv if the

Re: Question on -fwrapv and -fwrapv-pointer

On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches wrote: > > Hi, > > I have several questions on these options: > > 1.are pointers treated as signed integers in general? (I thought that > pointers are addresses to the memory, should be treated as unsigned integer…) > 2. If Yes, why? > 3.

Re: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode

Thanks for cleaning up. LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-13 20:31 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode This patch cleanups r

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

LGTM. It's obvious you fixed my previous redundant codes. Thanks. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-13 20:31 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns This patch adj

[PATCH] libstdc++: Use C++20 constraints in

Tested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- By now it's probably safe to assume supported compilers have full concepts support in C++20 mode. And using a requires-clase instead enable_if_t inside the return type greatly reduces the sizes of the corresponding symbol names

Re: [PATCH] RISC-V: Support VLS modes mask operations

LGTM Juzhe-Zhong 於 2023年9月14日 週四 20:44 寫道： > This patch support mask operations (comparison and logical). > > This patch reduce these FAILs of "vect" testsuite: > FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects > scan-tree-dump dce7 "<=\\s*.+{ 255,.+}" > FAIL: gcc.dg/vect/vect-bi

[PATCH] Harmonize headers between both dg-extract-results scripts

Hi, This is a small patch so that both dg-extract-results.py and dg-extract-results.sh share the same header. In particular, it fixes the fact that the regexp r'^Test Run By (\S+) on (.*)$' was never matched in the python file. Thanks, -- Paul Kalray Author: Paul Iannetta Date: Thu Sep 14 1

RE: [PATCH] RISC-V: Support VLS modes mask operations

Committed, thanks Kito. Pan -Original Message- From: Gcc-patches On Behalf Of Kito Cheng via Gcc-patches Sent: Thursday, September 14, 2023 10:23 PM To: Juzhe-Zhong Cc: GCC Patches ; Kito Cheng ; Jeff Law ; Robin Dapp Subject: Re: [PATCH] RISC-V: Support VLS modes mask operations LG

[PATCH] aarch64: Restore SVE WHILE costing

AArch64 previously costed WHILELO instructions on the first call to add_stmt_cost. This was because, at the time, only add_stmt_cost had access to the loop_vec_info. However, after the AVX512 changes, we only calculate the masks later. This patch moves the WHILELO costing to finish_cost, which is

Re: RFC: Introduce -fhardened to enable security-related flags

On Wed, Aug 30, 2023 at 3:42 AM Marek Polacek via Gcc-patches wrote: > > Improving the security of software has been a major trend in the recent > years. Fortunately, GCC offers a wide variety of flags that enable extra > hardening. These flags aren't enabled by default, though. And since > the

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

LGTM too :) On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 wrote: > > LGTM. > It's obvious you fixed my previous redundant codes. > Thanks. > > > > juzhe.zh...@rivai.ai > > From: Lehua Ding > Date: 2023-09-13 20:31 > To: gcc-patches > CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding

Re: Question on -fwrapv and -fwrapv-pointer

Thanks for the info. > On Sep 14, 2023, at 10:06 AM, Richard Biener > wrote: > > On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches > wrote: >> >> Hi, >> >> I have several questions on these options: >> >> 1.are pointers treated as signed integers in general? (I thought that >> poin

Re: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode

Committed, thanks Juzhe. On 2023/9/14 22:10, 钟居哲 wrote: Thanks for cleaning up. LGTM. juzhe.zh...@rivai.ai *From:* Lehua Ding *Date:* 2023-09-13 20:31 *To:* gcc-patches

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

Committed, thanks Kito and Juzhe. On 2023/9/14 22:53, Kito Cheng wrote: LGTM too :) On Thu, Sep 14, 2023 at 10:11 PM 钟居哲 wrote: LGTM. It's obvious you fixed my previous redundant codes. Thanks. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-09-13 20:31 To: gcc-patches CC: juzhe.zhong;

Re: Question on -fwrapv and -fwrapv-pointer

> Am 14.09.2023 um 17:01 schrieb Qing Zhao : > > Thanks for the info. > >> On Sep 14, 2023, at 10:06 AM, Richard Biener >> wrote: >> >>> On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches >>> wrote: >>> >>> Hi, >>> >>> I have several questions on these options: >>> >>> 1.are poi

Re: [PATCH 8/8] OpenMP: Fortran "!$omp declare mapper" support

On Tue, 5 Sep 2023 12:28:28 -0700 Julian Brown wrote: > + static bool > + equal (const omp_name_type &a, > + const omp_name_type &b) > + { > +if (a.name == NULL_TREE && b.name == NULL_TREE) > + return a.type == b.type; I'm curious if (and why) the type comparison above is safe a

[PATCH] AArch64: Improve immediate expansion [PR105928]

Support immediate expansion of immediates which can be created from 2 MOVKs and a shifted ORR or BIC instruction. Change aarch64_split_dimode_const_store to apply if we save one instruction. This reduces the number of 4-instruction immediates in SPECINT/FP by 5%. Passes regress, OK for commit?

[pushed] [RA]: Improve cost calculation of pseudos with equivalences

I've committed the following patch.  The reason for this patch is explained in its commit message. The patch was successfully bootstrapped and tested on x86-64, aarch64, and ppc64le. commit 3c834d85f2ec42c60995c2b678196a06cb744959 Author: Vladimir N. Makarov Date: Thu Sep 14 10:26:48 2023

[PATCH] RISC-V: Support combine extend and reduce sum to widen reduce sum

This patch add combine pattern to combine extend and reduce sum to widen reduce sum. The pattern in autovec.md was adjusted as needed. Note that the current vectorization cannot generate reduce openrand which is LMUL=M8, because this means that we need an LMUL=M16 for the extended openrand, which i

Re: Question on -fwrapv and -fwrapv-pointer

> On Sep 14, 2023, at 11:12 AM, Richard Biener > wrote: > > > >> Am 14.09.2023 um 17:01 schrieb Qing Zhao : >> >> Thanks for the info. >> >>> On Sep 14, 2023, at 10:06 AM, Richard Biener >>> wrote: >>> On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches wrote: >>

Re: [PATCH] RISC-V: Support combine extend and reduce sum to widen reduce sum

LGTM On Thu, Sep 14, 2023 at 11:51 PM Lehua Ding wrote: > > This patch add combine pattern to combine extend and reduce sum > to widen reduce sum. The pattern in autovec.md was adjusted as > needed. Note that the current vectorization cannot generate reduce > openrand which is LMUL=M8, because th

Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

I am thinking what we are doing is something like we are allowing scalar mode within the vector register, so...not sure should we try to implement that within the mov pattern? I guess we need some inputs from Jeff. e.g. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0ec

Re: Question on -fwrapv and -fwrapv-pointer

On Thu, 2023-09-14 at 15:57 +, Qing Zhao via Gcc-patches wrote: > Currently, GCC behaves as following: > > /* True if overflow wraps around for the given integral or pointer type.  That >    is, TYPE_MAX + 1 == TYPE_MIN.  */ > #define TYPE_OVERFLOW_WRAPS(TYPE) \ >   (POINTER_TYPE_P (TYPE) 

[PATCH] aarch64: Ensure const and sign correctness

Be const and sign correct by using a matching CIE augmentation type. Use a builtin instead of relying being included. libgcc/ChangeLog: * config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key): Use const unsigned type and a builtin. Signed-off-by: Pekka Seppänen

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