On Tue, Apr 27, 2021 at 10:22 PM Jeff Law wrote:
>
> This change:
>
> d8e1f1d24179690fd9c0f63c27b12e030010d9ea is the first bad commit
> commit d8e1f1d24179690fd9c0f63c27b12e030010d9ea
> Author: Richard Biener
> Date: Wed Apr 7 12:09:44 2021 +0200
>
> tree-optimization/99912 - schedule DSE
This makes sure to fall into the delete_unreachable_blocks_update_callgraph
handling to remove blocks becoming unreachable when removing EH edges
by open-coding gimple_purge_dead_eh_edges.
This fixes an ICE seen with gfortran.dg/gomp/pr88933.f90 when enhancing
DSE.
Bootstrap & regtest running on
This helps loop-invariant motion to hoist complicated offset computations.
Tested on x86-64/Linux, applied on the mainline.
2021-04-28 Eric Botcazou
* gcc-interface/trans.c (language_function): Add comment.
(loop_info_d): Add fndecl and invariants fields.
(find_loop_f
This makes sure to fall into the delete_unreachable_blocks_update_callgraph
handling to remove blocks becoming unreachable when removing EH edges
by tracking blocks to need EH cleanup and doing that after releasing
dominance info.
This fixes an ICE seen with gfortran.dg/gomp/pr88933.f90 when enhan
This avoids creating a useless temporary for a call to a pure function with
good properties by using the RSO.
Tested on x86-64/Linux, applied on the mainline.
2021-04-28 Eric Botcazou
* gcc-interface/trans.c (is_array_of_scalar_type): New predicate.
(find_decls_r): New functi
On Wed, Apr 28, 2021 at 8:54 AM Andreas Krebbel via Gcc-patches
wrote:
>
> The problem appears to be triggered by two locations in the front-end
> where non-POINTER_SIZE pointers aren't handled right now.
>
> 1. An assertion in strip_typedefs is triggered because the alignment
> of the types don't
On 4/28/21 10:12 AM, Richard Biener wrote:
> On Wed, Apr 28, 2021 at 8:54 AM Andreas Krebbel via Gcc-patches
> wrote:
>>
>> The problem appears to be triggered by two locations in the front-end
>> where non-POINTER_SIZE pointers aren't handled right now.
>>
>> 1. An assertion in strip_typedefs is
This prevents the compiler from creating useless local bounds around calls
that take a parameter of an unconstrained array type when the bounds already
exist somewhere else for the actual parameter.
Tested on x86-64/Linux, applied on the mainline.
2021-04-28 Eric Botcazou
* gcc-inter
On Tue, Apr 27, 2021 at 5:34 PM Alexandre Oliva wrote:
>
>
> Several i386 align tests expect p2align to be used, but not all
> configurations define ASM_OUTPUT_MAX_SKIP_ALIGN, even when
> HAVE_GAS_MAX_SKIP_P2ALIGN.
>
> i386.h has an equivalent ASM_OUTPUT_MAX_SKIP_PAD that is used in
> i386.c, so I
On 4/28/21 10:22 AM, Andreas Krebbel via Gcc-patches wrote:
> On 4/28/21 10:12 AM, Richard Biener wrote:
>> On Wed, Apr 28, 2021 at 8:54 AM Andreas Krebbel via Gcc-patches
>> wrote:
>>>
>>> The problem appears to be triggered by two locations in the front-end
>>> where non-POINTER_SIZE pointers ar
When use multi-lib riscv-tool-chain. A bug is triggered when there are two
'-march' at command line.
riscv64-unknown-elf-gcc -march=rv32gcp -mabi=ilp32f -march=rv32gcpzp64
HelloWorld.c
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld:
/lh
On Tue, Apr 27, 2021 at 5:34 PM Alexandre Oliva wrote:
>
>
> Several i386 align tests expect p2align to be used, but not all
> configurations define ASM_OUTPUT_MAX_SKIP_ALIGN, even when
> HAVE_GAS_MAX_SKIP_P2ALIGN.
>
> i386.h has an equivalent ASM_OUTPUT_MAX_SKIP_PAD that is used in
> i386.c, so I
On Wed, Apr 28, 2021 at 10:50 AM Richard Biener wrote:
>
> This makes sure to fall into the delete_unreachable_blocks_update_callgraph
> handling to remove blocks becoming unreachable when removing EH edges
> by open-coding gimple_purge_dead_eh_edges.
>
> This fixes an ICE seen with gfortran.dg/go
gcc/ChangeLog:
* doc/options.texi (Negative): Fix the discription so that it matches
the code implementation of prune_options().
---
gcc/doc/options.texi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index 205762
We have to avoid folding the condition when building a COND_EXPR
since we no longer gimplify the whole thing. The folding done
at COND_EXPR build time will deal with possible simplifications.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
2021-04-28 Richard Biener
PR
A comment in Analyze_Case_Statement describes an "interesting
optimization" that was applied to all assignable objects. This patch
extends it to all objects, in particular, to formal parameters of mode
IN.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_ch5.adb (Analyze_
This patch fixes a bug where if a private type has a full type that is a
modular type with a Default_Value specified, then creating objects of
that type causes the compiler to incorrectly say, "illegal operand for
numeric conversion".
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
When using 'Valid_Scalars on unconstrained arrays, the expanded code
includes unchecked conversion to the unconstrained base type, which may
lead to incorrect code being generated.
Fixed by replacing Validated_View by Get_Fullest_View except for records
where it is still needed.
We also take this
A reference in the comment about the type resolution described in
Sem_Ch4 refers to description with a header "Handling of Overload
Resolution", but this has been moved to Sem_Type.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_res.ads: Update reference in comment.
Remove dead code found by GNATcoverage:
* Protected objects do not exist in Ada 83.
* The whole last part of Scan_ALI is no longer used.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_ch3.adb (Analyze_Object_Declaration): Remove dead code.
* ali.ads, ali.adb (S
The RM states (A.18-4-18/2, A.18.7-17/2, et al) that "the predefined "="
operator for type Cursor returns True if both cursors are No_Element, or
designate the same element in the same container."
In some cases, GNAT's implementation violates this requirement. This was due
to the component "Positi
It may be surprising to users that a ghost entity is not allowed to
appear in a predicate, which is a kind of assertion. Explain this in a
continuation message, as well as the possible fixes.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* ghost.adb (Check_Ghost_Context): Ad
Compiler aborts on an instance body that has a reference to a selected
component of a local type extension, when the component is inherited
from an ancestor type declared outside of the generic being
instantiated.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* exp_ch3.adb (
When calling an access to a subprogram taking an unconstrained
discriminated record as parameter, we fail to pass the extra constrained
actual parameter, which would lead to spurious or missed discriminant
checks.
At the same time we noticed that GNAT sometimes generates trees of the
form:
(Fie
This is preliminary work to properly handle a declare expression used in
a postcondition. This first part is adding guards against missing types.
The second part will be about setting the proper type when currently
missing.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem
Global variable Sem_Type.Headers, which is used in type resolution, was
initialized twice: by elaboration and by Init_Interp_Tables (called by
Gnat1drv).
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* fmap.ads (Reset_Tables): Remove outdated references to
GNSA/ASIS.
Recent improvements in the handling of discriminants and discriminant
checks made an assert failure appear on complex code.
It appears that the assertions in einfo.adb (Discriminant_Constraint) is
too strict.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* einfo.adb (Discri
When a Pre/Post aspect is conflicting with Static aspect, the error
message now says 'aspect "Pre"' or 'aspect "Post"' and not just "this
aspect".
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_ch13.adb (Analyze_Aspect_Static): Use aspect name in the
error messa
Change the internal data structure that stores the compiler diagnostics
to store spans instead of locations, where a span is a triplet of a main
location, and a first-last pair of locations. Also change the main
procedures for reporting an error in Errout to use spans instead of
locations whenever
AI12-0397 specifies new rules for the resolution of expressions for the
Default_Intial_Condition aspect, based on defining that a reference to
the current instance of a type with DIC is a notional (nonabstract) formal
derived type (making DIC similar to how Postcondition and Type_Invariant
are defi
Check for the expression of the aspect Static were done inside branches
corresponding to inside-a-generic and outside-a-generic. Now this check
occurs only once. Code cleanup; behaviour is unaffected.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_ch13.adb (Analyze_Aspe
This overcomes the lack of fused multiply-add instruction on the x87
FPU by doing an iterated addition with exact error handling for the
last digit taken into account for the mantissa.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* libgnat/s-valrea.adb (Fast2Sum): New funct
Reuse Error_Msg_Ada_2020_Feature for messages that reference the
currently processed aspect using the '%' insertion character. Cleanup
only; behaviour is not affected.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* sem_ch13.adb (Analyze_Aspect_Static): Reuse
Error_M
The counter variable in routine Formal_Is_Used_Once is initialized with
0, then is possibly incremented to 1, and when incremented again, the
traversal is abandoned. This second increment can only make the counter
equal 2; there is no need to explicitly re-assign it.
Code cleanup only; semantics i
System.Interrupt.Install_Restricted_Handlers takes a parameter Prio. It
was defined as Any_Priority when it should be the more narrower
Interrupt_Priority subtype as handlers can only have priorities in the
Interrupt_Priority range. Using the more narrower subtype assists in
unit testing.
Tested o
The data structure for overloaded interpretations included a hash table
with a subtle implementation. It is now replaced with a generic hash
provided by the GNAT.HTable.
This is only a code cleanup; behaviour of the compiler is not affected.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/
The result must be the Small instead of the Tiny in this case.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* libgnat/s-fatgen.adb: Add use clause for Interfaces.Unsigned_16
and Interfaces.Unsigned_32.
(Small16): New constant.
(Small32): Likewise.
As GNATprove uses the AST after semantic analysis without expansion, the
recent optimization in the evaluation of selected components for
aggregates was leading to incorrect AST where possible run-time errors
in the evaluation of the (aggregate) prefix were not taken into account.
Fixed by only ena
The comment for List_Length says "It is an error to call this function
with No_List (No_List is not considered to be the same as an empty
list).". It legitimately happens in practice, so adjust the comment to
allow this.
Tested on x86_64-pc-linux-gnu, committed on trunk
gcc/ada/
* nlist
Hello, gentle maintainer.
This is a message from the Translation Project robot. (If you have
any questions, send them to .)
A new POT file for textual domain 'gcc' has been made available
to the language teams for translation. It is archived as:
https://translationproject.org/POT-files/gcc
Hi Senthil!
> On Mon, Apr 26, 2021 at 9:20 AM Senthil Kumar Selvaraj via Gcc-patches
> wrote:
>>
>> Hi,
>>
>> This is
>> https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html,
>> rebased against latest gcc master. The only change is modification of
>> avr_md_asm_adjust's signature to
This arranges for the x86 AVX and AVX2 masked load builtins to be
pure to enable dead code elimination and more appropriate alias
analysis.
Bootstrapped and tested on x86_64-unknown-linux-gnu. OK for trunk?
Thanks,
Richard.
2021-04-28 Richard Biener
PR target/100312
* config
init_regs_for_mode iterates over all hard regs for the machine to test
if the reg is OK for the mode, but an arithmetic overflow can lead to
testing elements beyond the end of the arrays allocated for fixed and
global registers. Clearly, if a mode requiring multiple hard regs needs
one beyond
On Wed, Apr 28, 2021 at 12:04:45PM +0100, Richard Earnshaw wrote:
> init_regs_for_mode iterates over all hard regs for the machine to test if
> the reg is OK for the mode, but an arithmetic overflow can lead to testing
> elements beyond the end of the arrays allocated for fixed and global
> registe
On Wed, Apr 28, 2021 at 1:02 PM Richard Biener wrote:
>
> This arranges for the x86 AVX and AVX2 masked load builtins to be
> pure to enable dead code elimination and more appropriate alias
> analysis.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu. OK for trunk?
>
> Thanks,
> Richard.
>
On Wed, 28 Apr 2021, Uros Bizjak wrote:
> On Wed, Apr 28, 2021 at 1:02 PM Richard Biener wrote:
> >
> > This arranges for the x86 AVX and AVX2 masked load builtins to be
> > pure to enable dead code elimination and more appropriate alias
> > analysis.
> >
> > Bootstrapped and tested on x86_64-unk
On 4/28/21 10:12 AM, Richard Biener wrote:
> On Wed, Apr 28, 2021 at 8:54 AM Andreas Krebbel via Gcc-patches
> wrote:
>>
>> The problem appears to be triggered by two locations in the front-end
>> where non-POINTER_SIZE pointers aren't handled right now.
>>
>> 1. An assertion in strip_typedefs is
The new inline definition of std::thread::hardware_concurrency() for
non-gthreads targets is missing the noexcept-specifier that is on the
declaration.
libstdc++-v3/ChangeLog:
PR libstdc++/100298
* include/bits/std_thread.h (thread::hardware_concurrency): Add
missing noexc
On Wed, Apr 28, 2021 at 1:46 PM Richard Biener wrote:
>
> On Wed, 28 Apr 2021, Uros Bizjak wrote:
>
> > On Wed, Apr 28, 2021 at 1:02 PM Richard Biener wrote:
> > >
> > > This arranges for the x86 AVX and AVX2 masked load builtins to be
> > > pure to enable dead code elimination and more appropria
I have been fixing a bug. It involved the Negative property of options, and I
have some confusion about it.
gcc/optc-gen.awk: 383
neg = opt_args("Negative", flags[i]);
if (neg != "")
idx = indices[neg]
else {
if (flag_set_p("RejectNegative", flags[i]))
idx = -1;
else {
if (opts[i
On 4/28/2021 1:10 AM, Richard Biener wrote:
On Tue, Apr 27, 2021 at 10:22 PM Jeff Law wrote:
This change:
d8e1f1d24179690fd9c0f63c27b12e030010d9ea is the first bad commit
commit d8e1f1d24179690fd9c0f63c27b12e030010d9ea
Author: Richard Biener
Date: Wed Apr 7 12:09:44 2021 +0200
tree
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the German team of translators. The file is available at:
https://translationproject.org/latest/gcc/de.po
(This file, 'gcc-11.1.0.de.po', has jus
-Wdeprecated-copy was depending only on the state of the warning at the
point where we call the function, making it hard to use #pragma diagnostic
to suppress the warning for a particular implicitly declared function.
But checking whether the warning is enabled at the location of the implicit
dec
On Wed, 28 Apr 2021, Uros Bizjak wrote:
> On Wed, Apr 28, 2021 at 1:46 PM Richard Biener wrote:
> >
> > On Wed, 28 Apr 2021, Uros Bizjak wrote:
> >
> > > On Wed, Apr 28, 2021 at 1:02 PM Richard Biener wrote:
> > > >
> > > > This arranges for the x86 AVX and AVX2 masked load builtins to be
> > >
Hi,
As subject, this patch rewrites the vmull[_high]_p8 Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling and
optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Hi,
As subject, this patch rewrites the vq[r]dmulh[q]_n Neon intrinsics to use
RTL builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/Chan
On Tue, Apr 27, 2021 at 03:36:38PM +0200, Tobias Burnus wrote:
> OpenMP 5's iterator can be used for
> - depend clause
> - affinity clause
> - mapping (unsupported and not touched)
>
> (a) This patch add the iterator support to the Fortran FE
> and adds support for it to the depend clause.
>
> (b
Hi,
As subject, this patch rewrites the vpaddq Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2
Hi,
As subject, this patch rewrites the [su]paddl[q] Neon intrinsics to use
RTL builtins rather than inline assembly code, allowing for better
scheduling and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeL
Hi,
As subject, this patch rewrites the vpadal_[su]32 Neon intrinsics to use
RTL builtins rather than inline assembly code, allowing for better
scheduling and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/Change
Use '@' to prevent Make from echoing the recipe, so that users don't see
this every time:
if [ -f ${doxygen_pdf} ]; then
mv ${doxygen_pdf} ${api_pdf} ;
echo ":: PDF file is ${api_pdf}";
else
echo "... error";
grep -F 'LaTeX Error' ${doxygen_outdir}/latex/refman.log;
grep -F
Hi,
As subject, this patch rewrites the vsli[q]_n_p* Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeL
On 4/28/21 2:24 AM, Richard Biener wrote:
The final thing I plan to incorporate is some documentation of ranger
technology. There are a lot of features and data available in the
Ranger ecosystem that could be useful elsewhere. No one really knows
about them, and rather than trying to write ev
Hi,
As subject, this patch rewrites the vsri[q]_n_p* Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeL
On Tue, Apr 27, 2021 at 12:22:44PM +0200, Tobias Burnus wrote:
> If configured with --enable-offload-defaulted, configured but not installed
> offload compilers and libgomp plugins are silently ignored. Useful for
> distribution compilers where those are in separate optional packages.
>
> 2021-04
On 28/04/2021 12:22, Jakub Jelinek via Gcc-patches wrote:
On Wed, Apr 28, 2021 at 12:04:45PM +0100, Richard Earnshaw wrote:
init_regs_for_mode iterates over all hard regs for the machine to test if
the reg is OK for the mode, but an arithmetic overflow can lead to testing
elements beyond the
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vmull[_high]_p8 Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling and
> optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu and
> aa
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Ukrainian team of translators. The file is available at:
https://translationproject.org/latest/gcc/uk.po
(This file, 'gcc-11.1.0.uk.po', has
On 4/27/21 12:22 PM, Tobias Burnus wrote:
> This is based on Jakub's patch* which is used with many distributions – and
> is has
> to be maintained by all of them; otherwise issues like lp #1878760 might
> creep in,
> as discussed in #gcc yesterday. - As I am a huge fan of reducing code
> duplic
On Wed, Apr 28, 2021 at 03:06:53PM +0100, Richard Earnshaw wrote:
> We could of course, change the patch below into a checking assert of the
> inverse condition: that would help to catch issues like this.
I have nothing against an assert, but am not sure that sel-sched is the best
spot for that, b
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vq[r]dmulh[q]_n Neon intrinsics to use
> RTL builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> i
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vpaddq Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issues.
>
Hi,
As subject, this patch rewrites the v[q]tbl Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
Hi,
As subject, this patch rewrites the v[q]tbx Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
Hi,
When running the test-case included in this patch using an
nvptx accelerator, it fails in execution.
The problem is that the expansion of GOMP_SIMT_XCHG_BFLY is optimized away
during pass_jump as "trivially dead insns".
This is caused by this code in expand_GOMP_SIMT_XCHG_BFLY:
...
class e
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the [su]paddl[q] Neon intrinsics to use
> RTL builtins rather than inline assembly code, allowing for better
> scheduling and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issu
Hi,
As subject, this patch rewrites the floating-point vml[as][q]_n Neon
intrinsics to use RTL builtins rather than inline assembly code, allowing
for better scheduling and optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
-
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vpadal_[su]32 Neon intrinsics to use
> RTL builtins rather than inline assembly code, allowing for better
> scheduling and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> iss
On Wed, Apr 28, 2021 at 04:30:30PM +0200, Tom de Vries wrote:
> gcc/ChangeLog:
>
> 2021-04-28 Tom de Vries
>
> PR target/100232
> * internal-fn.c (expand_GOMP_SIMT_ENTER_ALLOC)
> (expand_GOMP_SIMT_LAST_LANE, expand_GOMP_SIMT_ORDERED_PRED)
> (expand_GOMP_SIMT_VOTE_ANY, e
Hi,
As subject, this patch rewrites the floating-point vml[as][q] Neon intrinsics
to use RTL builtins rather than relying on the GCC vector extensions.
Using RTL builtins allows control over the emission of fmla/fmls
instructions (which we don't want here.)
With this commit, the code generated by
Use a GOT indirection for extern weak symbols instead of a literal - this is
the same as
PIC/PIE and mirrors LLVM behaviour. Ensure PIC/PIE use the same offset limits
for symbols
that don't use the GOT.
Passes bootstrap and regress. OK for commit?
ChangeLog:
2021-04-27 Wilco Dijkstra
Hi,
As subject, this patch rewrites the floating-point vml[as][q]_lane Neon
intrinsics to use RTL builtins rather than relying on the GCC vector
extensions. Using RTL builtins allows control over the emission of
fmla/fmls instructions (which we don't want here.)
With this commit, the code generat
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vsli[q]_n_p* Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issu
Hi,
As subject, this patch rewrites the floating-point vml[as][q]_laneq Neon
intrinsics to use RTL builtins rather than relying on the GCC vector
extensions. Using RTL builtins allows control over the emission of
fmla/fmls instructions (which we don't want here.)
With this commit, the code genera
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the vsri[q]_n_p* Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issu
Hi,
As subject, this patch adds compilation tests to make sure that the output
of vmla/vmls floating-point Neon intrinsics (fmul, fadd/fsub) is not fused
into fmla/fmls instructions.
Ok for master?
Thanks,
Jonathan
---
gcc/testsuite/ChangeLog:
2021-02-16 Jonathan Wright
* gcc.targ
Hi,
As subject, this patch rewrites the vcvtx Neon intrinsics to use RTL builtins
rather than inline assembly code, allowing for better scheduling and
optimization.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the v[q]tbl Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issues.
>
Hi,
As subject, this patch implements the v[r]addhn2 and v[r]subhn2 Neon
intrinsic RTL patterns using a vec_concat of a register_operand and an
ADDSUBHN unspec - instead of just an ADDSUBHN2 unspec. This more
relaxed pattern allows for more aggressive combinations and ultimately
better code genera
Hi,
As subject, this patch implements the saturating right-shift and narrow
high Neon intrinsic RTL patterns using a vec_concat of a register_operand
and a VQSHRN_N unspec - instead of just a VQSHRN2_N unspec. This
more relaxed pattern allows for more aggressive combinations and
ultimately better
Hi,
As subject, this patch updates the attributes of all intrinsics defined in
arm_fp16.h to be consistent with the attributes of the intrinsics defined
in arm_neon.h. Specifically, this means updating the attributes from:
__extension__ static __inline
__attribute__ ((__always_inline__))
to:
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the v[q]tbx Neon intrinsics to use RTL
> builtins rather than inline assembly code, allowing for better scheduling
> and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issues.
>
On Wed, Apr 28, 2021 at 3:32 PM Richard Biener wrote:
>
> On Wed, 28 Apr 2021, Uros Bizjak wrote:
>
> > On Wed, Apr 28, 2021 at 1:46 PM Richard Biener wrote:
> > >
> > > On Wed, 28 Apr 2021, Uros Bizjak wrote:
> > >
> > > > On Wed, Apr 28, 2021 at 1:02 PM Richard Biener
> > > > wrote:
> > > > >
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the floating-point vml[as][q]_n Neon
> intrinsics to use RTL builtins rather than inline assembly code, allowing
> for better scheduling and optimization.
>
> Regression tested and bootstrapped on aarch64-none-linux-
As noted in r11-1339-gb6ab9ecd550227684643b41e9e33a4d3466724d8 we define
a non-standard __cpp_lib_constexpr_char_traits feature test macro to
indicate support for P0426R1 and P1032R1. At some point last year the
__cpp_lib_constexpr_string macro was retconned to indicate support for
those papers. Th
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the floating-point vml[as][q] Neon intrinsics
> to use RTL builtins rather than relying on the GCC vector extensions.
> Using RTL builtins allows control over the emission of fmla/fmls
> instructions (which we don't
Wilco Dijkstra via Gcc-patches writes:
> Use a GOT indirection for extern weak symbols instead of a literal - this is
> the same as
> PIC/PIE and mirrors LLVM behaviour.
Just to check: I guess this part is an optimisation, because it
means that we can share the GOT entry with other TUs. Is that
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch rewrites the floating-point vml[as][q]_lane Neon
> intrinsics to use RTL builtins rather than relying on the GCC vector
> extensions. Using RTL builtins allows control over the emission of
> fmla/fmls instructions (which we d
Hi,
As subject, this patch updates the attributes of all intrinsics defined in
arm_acle.h to be consistent with the attributes of the intrinsics defined
in arm_neon.h. Specifically, this means updating the attributes from:
__extension__ static __inline
__attribute__ ((__always_inline__))
to:
Jonathan Wright via Gcc-patches writes:
> Hi,
>
> As subject, this patch adds compilation tests to make sure that the output
> of vmla/vmls floating-point Neon intrinsics (fmul, fadd/fsub) is not fused
> into fmla/fmls instructions.
>
> Ok for master?
>
> Thanks,
> Jonathan
>
> ---
>
> gcc/testsui
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