[PATCH 6/20] aarch64: Use RTL builtins for polynomial vsli[q]_n intrinsics

[Jonathan Wright via Gcc-patches]

Hi,

As subject, this patch rewrites the vsli[q]_n_p* Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better scheduling
and optimization.

Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-02-10  Jonathan Wright  <jonathan.wri...@arm.com>

        * config/aarch64/aarch64-simd-builtins.def: Use VALLP mode
        iterator for polynomial ssli_n builtin generator macro.
        * config/aarch64/arm_neon.h (vsli_n_p8): Use RTL builtin
        instead of inline asm.
        (vsli_n_p16): Likewise.
        (vsliq_n_p8): Likewise.
        (vsliq_n_p16): Likewise.
        * config/aarch64/iterators.md: Define VALLP mode iterator.

rb14146.patch
Description: rb14146.patch